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authorVinod Koul <vinod.koul@intel.com>2010-07-21 03:58:10 -0400
committerDan Williams <dan.j.williams@intel.com>2010-07-28 02:32:57 -0400
commitb3c567e474b5ba4447b6e16063a3b0cffc22d205 (patch)
treefa5f4f72fcf12dc53a5e58b5359038864595fe3e /drivers/dma/intel_mid_dma_regs.h
parent084a2ab9c258fb1efbb009f1bb1c6976da1f73f4 (diff)
intel_mid: Add Mrst & Mfld DMA Drivers
This patch add DMA drivers for DMA controllers in Langwell chipset of Intel(R) Moorestown platform and DMA controllers in Penwell of Intel(R) Medfield platfrom This patch adds support for Moorestown DMAC1 and DMAC2 controllers. It also add support for Medfiled GP DMA and DMAC1 controllers. These controllers supports memory to peripheral and peripheral to memory transfers. It support only single block transfers. This driver is based on Kernel DMA engine Anyone who wishes to use this controller should use DMA engine APIs This controller exposes DMA_SLAVE capabilities and notifies the client drivers of DMA transaction completion Config option required to be enabled CONFIG_INTEL_MID_DMAC=y Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/intel_mid_dma_regs.h')
-rw-r--r--drivers/dma/intel_mid_dma_regs.h260
1 files changed, 260 insertions, 0 deletions
diff --git a/drivers/dma/intel_mid_dma_regs.h b/drivers/dma/intel_mid_dma_regs.h
new file mode 100644
index 000000000000..d81aa658ab09
--- /dev/null
+++ b/drivers/dma/intel_mid_dma_regs.h
@@ -0,0 +1,260 @@
1/*
2 * intel_mid_dma_regs.h - Intel MID DMA Drivers
3 *
4 * Copyright (C) 2008-10 Intel Corp
5 * Author: Vinod Koul <vinod.koul@intel.com>
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 *
21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
22 *
23 *
24 */
25#ifndef __INTEL_MID_DMAC_REGS_H__
26#define __INTEL_MID_DMAC_REGS_H__
27
28#include <linux/dmaengine.h>
29#include <linux/dmapool.h>
30#include <linux/pci_ids.h>
31
32#define INTEL_MID_DMA_DRIVER_VERSION "1.0.5"
33
34#define REG_BIT0 0x00000001
35#define REG_BIT8 0x00000100
36
37#define UNMASK_INTR_REG(chan_num) \
38 ((REG_BIT0 << chan_num) | (REG_BIT8 << chan_num))
39#define MASK_INTR_REG(chan_num) (REG_BIT8 << chan_num)
40
41#define ENABLE_CHANNEL(chan_num) \
42 ((REG_BIT0 << chan_num) | (REG_BIT8 << chan_num))
43
44#define DESCS_PER_CHANNEL 16
45/*DMA Registers*/
46/*registers associated with channel programming*/
47#define DMA_REG_SIZE 0x400
48#define DMA_CH_SIZE 0x58
49
50/*CH X REG = (DMA_CH_SIZE)*CH_NO + REG*/
51#define SAR 0x00 /* Source Address Register*/
52#define DAR 0x08 /* Destination Address Register*/
53#define CTL_LOW 0x18 /* Control Register*/
54#define CTL_HIGH 0x1C /* Control Register*/
55#define CFG_LOW 0x40 /* Configuration Register Low*/
56#define CFG_HIGH 0x44 /* Configuration Register high*/
57
58#define STATUS_TFR 0x2E8
59#define STATUS_BLOCK 0x2F0
60#define STATUS_ERR 0x308
61
62#define RAW_TFR 0x2C0
63#define RAW_BLOCK 0x2C8
64#define RAW_ERR 0x2E0
65
66#define MASK_TFR 0x310
67#define MASK_BLOCK 0x318
68#define MASK_SRC_TRAN 0x320
69#define MASK_DST_TRAN 0x328
70#define MASK_ERR 0x330
71
72#define CLEAR_TFR 0x338
73#define CLEAR_BLOCK 0x340
74#define CLEAR_SRC_TRAN 0x348
75#define CLEAR_DST_TRAN 0x350
76#define CLEAR_ERR 0x358
77
78#define INTR_STATUS 0x360
79#define DMA_CFG 0x398
80#define DMA_CHAN_EN 0x3A0
81
82/*DMA channel control registers*/
83union intel_mid_dma_ctl_lo {
84 struct {
85 u32 int_en:1; /*enable or disable interrupts*/
86 /*should be 0*/
87 u32 dst_tr_width:3; /*destination transfer width*/
88 /*usually 32 bits = 010*/
89 u32 src_tr_width:3; /*source transfer width*/
90 /*usually 32 bits = 010*/
91 u32 dinc:2; /*destination address inc/dec*/
92 /*For mem:INC=00, Periphral NoINC=11*/
93 u32 sinc:2; /*source address inc or dec, as above*/
94 u32 dst_msize:3; /*destination burst transaction length*/
95 /*always = 16 ie 011*/
96 u32 src_msize:3; /*source burst transaction length*/
97 /*always = 16 ie 011*/
98 u32 reser1:3;
99 u32 tt_fc:3; /*transfer type and flow controller*/
100 /*M-M = 000
101 P-M = 010
102 M-P = 001*/
103 u32 dms:2; /*destination master select = 0*/
104 u32 sms:2; /*source master select = 0*/
105 u32 llp_dst_en:1; /*enable/disable destination LLP = 0*/
106 u32 llp_src_en:1; /*enable/disable source LLP = 0*/
107 u32 reser2:3;
108 } ctlx;
109 u32 ctl_lo;
110};
111
112union intel_mid_dma_ctl_hi {
113 struct {
114 u32 block_ts:12; /*block transfer size*/
115 /*configured by DMAC*/
116 u32 reser:20;
117 } ctlx;
118 u32 ctl_hi;
119
120};
121
122/*DMA channel configuration registers*/
123union intel_mid_dma_cfg_lo {
124 struct {
125 u32 reser1:5;
126 u32 ch_prior:3; /*channel priority = 0*/
127 u32 ch_susp:1; /*channel suspend = 0*/
128 u32 fifo_empty:1; /*FIFO empty or not R bit = 0*/
129 u32 hs_sel_dst:1; /*select HW/SW destn handshaking*/
130 /*HW = 0, SW = 1*/
131 u32 hs_sel_src:1; /*select HW/SW src handshaking*/
132 u32 reser2:6;
133 u32 dst_hs_pol:1; /*dest HS interface polarity*/
134 u32 src_hs_pol:1; /*src HS interface polarity*/
135 u32 max_abrst:10; /*max AMBA burst len = 0 (no sw limit*/
136 u32 reload_src:1; /*auto reload src addr =1 if src is P*/
137 u32 reload_dst:1; /*AR destn addr =1 if dstn is P*/
138 } cfgx;
139 u32 cfg_lo;
140};
141
142union intel_mid_dma_cfg_hi {
143 struct {
144 u32 fcmode:1; /*flow control mode = 1*/
145 u32 fifo_mode:1; /*FIFO mode select = 1*/
146 u32 protctl:3; /*protection control = 0*/
147 u32 rsvd:2;
148 u32 src_per:4; /*src hw HS interface*/
149 u32 dst_per:4; /*dstn hw HS interface*/
150 u32 reser2:17;
151 } cfgx;
152 u32 cfg_hi;
153};
154
155/**
156 * struct intel_mid_dma_chan - internal mid representation of a DMA channel
157 * @chan: dma_chan strcture represetation for mid chan
158 * @ch_regs: MMIO register space pointer to channel register
159 * @dma_base: MMIO register space DMA engine base pointer
160 * @ch_id: DMA channel id
161 * @lock: channel spinlock
162 * @completed: DMA cookie
163 * @active_list: current active descriptors
164 * @queue: current queued up descriptors
165 * @free_list: current free descriptors
166 * @slave: dma slave struture
167 * @descs_allocated: total number of decsiptors allocated
168 * @dma: dma device struture pointer
169 * @in_use: bool representing if ch is in use or not
170 */
171struct intel_mid_dma_chan {
172 struct dma_chan chan;
173 void __iomem *ch_regs;
174 void __iomem *dma_base;
175 int ch_id;
176 spinlock_t lock;
177 dma_cookie_t completed;
178 struct list_head active_list;
179 struct list_head queue;
180 struct list_head free_list;
181 struct intel_mid_dma_slave *slave;
182 unsigned int descs_allocated;
183 struct middma_device *dma;
184 bool in_use;
185};
186
187static inline struct intel_mid_dma_chan *to_intel_mid_dma_chan(
188 struct dma_chan *chan)
189{
190 return container_of(chan, struct intel_mid_dma_chan, chan);
191}
192
193/**
194 * struct middma_device - internal representation of a DMA device
195 * @pdev: PCI device
196 * @dma_base: MMIO register space pointer of DMA
197 * @dma_pool: for allocating DMA descriptors
198 * @common: embedded struct dma_device
199 * @tasklet: dma tasklet for processing interrupts
200 * @ch: per channel data
201 * @pci_id: DMA device PCI ID
202 * @intr_mask: Interrupt mask to be used
203 * @mask_reg: MMIO register for periphral mask
204 * @chan_base: Base ch index (read from driver data)
205 * @max_chan: max number of chs supported (from drv_data)
206 * @block_size: Block size of DMA transfer supported (from drv_data)
207 * @pimr_mask: MMIO register addr for periphral interrupt (from drv_data)
208 */
209struct middma_device {
210 struct pci_dev *pdev;
211 void __iomem *dma_base;
212 struct pci_pool *dma_pool;
213 struct dma_device common;
214 struct tasklet_struct tasklet;
215 struct intel_mid_dma_chan ch[MAX_CHAN];
216 unsigned int pci_id;
217 unsigned int intr_mask;
218 void __iomem *mask_reg;
219 int chan_base;
220 int max_chan;
221 int block_size;
222 unsigned int pimr_mask;
223};
224
225static inline struct middma_device *to_middma_device(struct dma_device *common)
226{
227 return container_of(common, struct middma_device, common);
228}
229
230struct intel_mid_dma_desc {
231 void __iomem *block; /*ch ptr*/
232 struct list_head desc_node;
233 struct dma_async_tx_descriptor txd;
234 size_t len;
235 dma_addr_t sar;
236 dma_addr_t dar;
237 u32 cfg_hi;
238 u32 cfg_lo;
239 u32 ctl_lo;
240 u32 ctl_hi;
241 dma_addr_t next;
242 enum dma_data_direction dirn;
243 enum dma_status status;
244 enum intel_mid_dma_width width; /*width of DMA txn*/
245 enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
246
247};
248
249static inline int test_ch_en(void __iomem *dma, u32 ch_no)
250{
251 u32 en_reg = ioread32(dma + DMA_CHAN_EN);
252 return (en_reg >> ch_no) & 0x1;
253}
254
255static inline struct intel_mid_dma_desc *to_intel_mid_dma_desc
256 (struct dma_async_tx_descriptor *txd)
257{
258 return container_of(txd, struct intel_mid_dma_desc, txd);
259}
260#endif /*__INTEL_MID_DMAC_REGS_H__*/