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authorSascha Hauer <s.hauer@pengutronix.de>2013-08-26 07:48:36 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:01:40 -0400
commitc88d901225dccd1dd7ca63c92ffc714c740b385a (patch)
treeffd08813c7c329cb3f90f357cdb9fc267c1ddb7f /drivers/cpufreq
parent4ab58164b858beb3f12578bb47d04ba56313a2e1 (diff)
cpufreq: imx6q: Fix clock enable balance
For changing the cpu frequency the i.MX6q has to be switched to some intermediate clock during the PLL reprogramming. The driver tries to be clever to keep the enable count correct but gets it wrong. If the cpufreq is increased it calls clk_disable_unprepare twice on pll2_pfd2_396m. This puts all other devices which get their clock from pll2_pfd2_396m into a nonworking state. Fix this by removing the clk enabling/disabling altogether since the clk core will do this automatically during a reparent. [shawn.guo: The driver assumes that cpu always boots with 800MHz, and the first transition on 400MHz must be entering 400MHz setpoint. But it turns out that's not always the case. In some system, cpu boots up at 400MHz and then the first transition on 400MHz will be leaving 400MHz setpoint rather than entering. In this case, the use count of pll2_pfd2_396m will be wrong. Anyway, since clock framework has been nicely handling the clk enabling during reparent, we should not need to worry about it.] Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'drivers/cpufreq')
-rw-r--r--drivers/cpufreq/cpufreq-imx6.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/drivers/cpufreq/cpufreq-imx6.c b/drivers/cpufreq/cpufreq-imx6.c
index 24dfa7a4b1f7..51861d668ee3 100644
--- a/drivers/cpufreq/cpufreq-imx6.c
+++ b/drivers/cpufreq/cpufreq-imx6.c
@@ -156,28 +156,11 @@ static int imx6_set_target(struct cpufreq_policy *policy,
156 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 156 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
157 * - Disable pll2_pfd2_396m_clk 157 * - Disable pll2_pfd2_396m_clk
158 */ 158 */
159 clk_prepare_enable(pll2_pfd2_396m_clk);
160 clk_set_parent(step_clk, pll2_pfd2_396m_clk); 159 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
161 clk_set_parent(pll1_sw_clk, step_clk); 160 clk_set_parent(pll1_sw_clk, step_clk);
162 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { 161 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
163 clk_set_rate(pll1_sys_clk, freqs.new * 1000); 162 clk_set_rate(pll1_sys_clk, freqs.new * 1000);
164 /*
165 * If we are leaving 396 MHz set-point, we need to enable
166 * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep
167 * their use count correct.
168 */
169 if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) {
170 clk_prepare_enable(pll1_sys_clk);
171 clk_disable_unprepare(pll2_pfd2_396m_clk);
172 }
173 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 163 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
174 clk_disable_unprepare(pll2_pfd2_396m_clk);
175 } else {
176 /*
177 * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
178 * to provide the frequency.
179 */
180 clk_disable_unprepare(pll1_sys_clk);
181 } 164 }
182 165
183 /* Ensure the arm clock divider is what we expect */ 166 /* Ensure the arm clock divider is what we expect */