ENGR00277271 ARM: imx: Disable WAIT mode for i.MX6SL during kernel boot up

WAIT mode is enabled by default due to hardware reset,
so we need to disable it during kernel boot up, otherwise,
system may crash without proper setting for WAIT mode.

CPUIdle driver will enable WAIT mode later. Below is the
stack dump when crash, this patch fix it:

Bad mode in data abort handler detected
Internal error: Oops - bad mode: 0 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.9+ #369
task: 807dba88 ti: 807d0000 task.ti: 807d0000
PC is at 0xffff1044
LR is at arch_cpu_idle+0x48/0x54
pc : [<ffff1044>]    lr : [<8000f7dc>]    psr: 60000192
sp : 807d1f60  ip : 00000000  fp : 00000000
r10: 807d8954  r9 : 8059980c  r8 : 80819280
r7 : 00000001  r6 : 80819280  r5 : 00000000  r4 : 807d0000
r3 : 8001cbe0  r2 : 807d9510  r1 : 0104b000  r0 : 80819540
Flags: nZCv  IRQs off  FIQs on  Mode IRQ_32  ISA ARM  Segment kernel
Control: 10c53c7d  Table: af28804a  DAC: 00000017
Process swapper/0 (pid: 0, stack limit = 0x807d0238)
Stack: (0x807d1f60 to 0x807d2000)
1f60: 80819540 0104b000 807d9510 8001cbe0 807d0000 00000000 80819280 00000001
1f80: 80819280 8059980c 807d8954 00000000 00000000 807d1f60 8000f7dc ffff1044
1fa0: 60000192 ffffffff 807d0000 8005de44 807d89d0 808193c0 807bf084 807dc86c
1fc0: 8000406a 412fc09a 00000000 8077fb58 ffffffff ffffffff 8077f6b4 00000000
1fe0: 00000000 807bf088 00000000 10c53c7d 807d88d0 80008074 00000000 00000000
[<8000f7dc>] (arch_cpu_idle+0x48/0x54) from [<0104b000>] (0x104b000)
Code: bad PC value
---[ end trace c2c7dd3b2230692c ]---
Kernel panic - not syncing: Attempted to kill the idle task

Signed-off-by: Anson Huang <b20788@freescale.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 267de6142029..dc9cd5f79794 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -281,6 +281,10 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 
         /* set perclk to source from OSC 24MHz */
         clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
+
+        /* Set initial power mode */
+        imx6_set_lpm(WAIT_CLOCKED);
+
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
         base = of_iomap(np, 0);
         WARN_ON(!base);