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authorViresh Kumar <viresh.kumar@linaro.org>2013-04-04 08:54:10 -0400
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2013-04-08 07:02:30 -0400
commitceff98e3338cc53e31491aa8db395dd66327b210 (patch)
tree556e52f0a24b2691fc0af1faf8cd334b3b6dcd40 /arch
parenta0ea048a6f72fbe9083b52ba26cd642e23ca026c (diff)
cpufreq: tegra: Move driver to drivers/cpufreq
This patch moves cpufreq driver of ARM based tegra platform to drivers/cpufreq. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/Makefile1
-rw-r--r--arch/arm/mach-tegra/cpu-tegra.c294
2 files changed, 0 insertions, 295 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f6b46ae2b7f8..09b578f9eb84 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -24,7 +24,6 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
24endif 24endif
25obj-$(CONFIG_SMP) += platsmp.o headsmp.o 25obj-$(CONFIG_SMP) += platsmp.o headsmp.o
26obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 26obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
27obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
28obj-$(CONFIG_TEGRA_PCI) += pcie.o 27obj-$(CONFIG_TEGRA_PCI) += pcie.o
29 28
30obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o 29obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
deleted file mode 100644
index 11ca730970f8..000000000000
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * arch/arm/mach-tegra/cpu-tegra.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/types.h>
24#include <linux/sched.h>
25#include <linux/cpufreq.h>
26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/err.h>
29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/suspend.h>
32
33/* Frequency table index must be sequential starting at 0 */
34static struct cpufreq_frequency_table freq_table[] = {
35 { 0, 216000 },
36 { 1, 312000 },
37 { 2, 456000 },
38 { 3, 608000 },
39 { 4, 760000 },
40 { 5, 816000 },
41 { 6, 912000 },
42 { 7, 1000000 },
43 { 8, CPUFREQ_TABLE_END },
44};
45
46#define NUM_CPUS 2
47
48static struct clk *cpu_clk;
49static struct clk *pll_x_clk;
50static struct clk *pll_p_clk;
51static struct clk *emc_clk;
52
53static unsigned long target_cpu_speed[NUM_CPUS];
54static DEFINE_MUTEX(tegra_cpu_lock);
55static bool is_suspended;
56
57static int tegra_verify_speed(struct cpufreq_policy *policy)
58{
59 return cpufreq_frequency_table_verify(policy, freq_table);
60}
61
62static unsigned int tegra_getspeed(unsigned int cpu)
63{
64 unsigned long rate;
65
66 if (cpu >= NUM_CPUS)
67 return 0;
68
69 rate = clk_get_rate(cpu_clk) / 1000;
70 return rate;
71}
72
73static int tegra_cpu_clk_set_rate(unsigned long rate)
74{
75 int ret;
76
77 /*
78 * Take an extra reference to the main pll so it doesn't turn
79 * off when we move the cpu off of it
80 */
81 clk_prepare_enable(pll_x_clk);
82
83 ret = clk_set_parent(cpu_clk, pll_p_clk);
84 if (ret) {
85 pr_err("Failed to switch cpu to clock pll_p\n");
86 goto out;
87 }
88
89 if (rate == clk_get_rate(pll_p_clk))
90 goto out;
91
92 ret = clk_set_rate(pll_x_clk, rate);
93 if (ret) {
94 pr_err("Failed to change pll_x to %lu\n", rate);
95 goto out;
96 }
97
98 ret = clk_set_parent(cpu_clk, pll_x_clk);
99 if (ret) {
100 pr_err("Failed to switch cpu to clock pll_x\n");
101 goto out;
102 }
103
104out:
105 clk_disable_unprepare(pll_x_clk);
106 return ret;
107}
108
109static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
110 unsigned long rate)
111{
112 int ret = 0;
113 struct cpufreq_freqs freqs;
114
115 freqs.old = tegra_getspeed(0);
116 freqs.new = rate;
117
118 if (freqs.old == freqs.new)
119 return ret;
120
121 /*
122 * Vote on memory bus frequency based on cpu frequency
123 * This sets the minimum frequency, display or avp may request higher
124 */
125 if (rate >= 816000)
126 clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
127 else if (rate >= 456000)
128 clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
129 else
130 clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
131
132 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
133
134#ifdef CONFIG_CPU_FREQ_DEBUG
135 printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
136 freqs.old, freqs.new);
137#endif
138
139 ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
140 if (ret) {
141 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
142 freqs.new);
143 return ret;
144 }
145
146 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
147
148 return 0;
149}
150
151static unsigned long tegra_cpu_highest_speed(void)
152{
153 unsigned long rate = 0;
154 int i;
155
156 for_each_online_cpu(i)
157 rate = max(rate, target_cpu_speed[i]);
158 return rate;
159}
160
161static int tegra_target(struct cpufreq_policy *policy,
162 unsigned int target_freq,
163 unsigned int relation)
164{
165 unsigned int idx;
166 unsigned int freq;
167 int ret = 0;
168
169 mutex_lock(&tegra_cpu_lock);
170
171 if (is_suspended) {
172 ret = -EBUSY;
173 goto out;
174 }
175
176 cpufreq_frequency_table_target(policy, freq_table, target_freq,
177 relation, &idx);
178
179 freq = freq_table[idx].frequency;
180
181 target_cpu_speed[policy->cpu] = freq;
182
183 ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
184
185out:
186 mutex_unlock(&tegra_cpu_lock);
187 return ret;
188}
189
190static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
191 void *dummy)
192{
193 mutex_lock(&tegra_cpu_lock);
194 if (event == PM_SUSPEND_PREPARE) {
195 struct cpufreq_policy *policy = cpufreq_cpu_get(0);
196 is_suspended = true;
197 pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
198 freq_table[0].frequency);
199 tegra_update_cpu_speed(policy, freq_table[0].frequency);
200 cpufreq_cpu_put(policy);
201 } else if (event == PM_POST_SUSPEND) {
202 is_suspended = false;
203 }
204 mutex_unlock(&tegra_cpu_lock);
205
206 return NOTIFY_OK;
207}
208
209static struct notifier_block tegra_cpu_pm_notifier = {
210 .notifier_call = tegra_pm_notify,
211};
212
213static int tegra_cpu_init(struct cpufreq_policy *policy)
214{
215 if (policy->cpu >= NUM_CPUS)
216 return -EINVAL;
217
218 clk_prepare_enable(emc_clk);
219 clk_prepare_enable(cpu_clk);
220
221 cpufreq_frequency_table_cpuinfo(policy, freq_table);
222 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
223 policy->cur = tegra_getspeed(policy->cpu);
224 target_cpu_speed[policy->cpu] = policy->cur;
225
226 /* FIXME: what's the actual transition time? */
227 policy->cpuinfo.transition_latency = 300 * 1000;
228
229 cpumask_copy(policy->cpus, cpu_possible_mask);
230
231 if (policy->cpu == 0)
232 register_pm_notifier(&tegra_cpu_pm_notifier);
233
234 return 0;
235}
236
237static int tegra_cpu_exit(struct cpufreq_policy *policy)
238{
239 cpufreq_frequency_table_cpuinfo(policy, freq_table);
240 clk_disable_unprepare(emc_clk);
241 return 0;
242}
243
244static struct freq_attr *tegra_cpufreq_attr[] = {
245 &cpufreq_freq_attr_scaling_available_freqs,
246 NULL,
247};
248
249static struct cpufreq_driver tegra_cpufreq_driver = {
250 .verify = tegra_verify_speed,
251 .target = tegra_target,
252 .get = tegra_getspeed,
253 .init = tegra_cpu_init,
254 .exit = tegra_cpu_exit,
255 .name = "tegra",
256 .attr = tegra_cpufreq_attr,
257};
258
259static int __init tegra_cpufreq_init(void)
260{
261 cpu_clk = clk_get_sys(NULL, "cpu");
262 if (IS_ERR(cpu_clk))
263 return PTR_ERR(cpu_clk);
264
265 pll_x_clk = clk_get_sys(NULL, "pll_x");
266 if (IS_ERR(pll_x_clk))
267 return PTR_ERR(pll_x_clk);
268
269 pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
270 if (IS_ERR(pll_p_clk))
271 return PTR_ERR(pll_p_clk);
272
273 emc_clk = clk_get_sys("cpu", "emc");
274 if (IS_ERR(emc_clk)) {
275 clk_put(cpu_clk);
276 return PTR_ERR(emc_clk);
277 }
278
279 return cpufreq_register_driver(&tegra_cpufreq_driver);
280}
281
282static void __exit tegra_cpufreq_exit(void)
283{
284 cpufreq_unregister_driver(&tegra_cpufreq_driver);
285 clk_put(emc_clk);
286 clk_put(cpu_clk);
287}
288
289
290MODULE_AUTHOR("Colin Cross <ccross@android.com>");
291MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
292MODULE_LICENSE("GPL");
293module_init(tegra_cpufreq_init);
294module_exit(tegra_cpufreq_exit);