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authorNicolin Chen <b42378@freescale.com>2013-08-30 03:21:19 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:01:33 -0400
commitb4a5d5138f04fdaa2586ada4b441a8325f05e2b9 (patch)
treee5525ca4bdc73b828833875f7f084ca7f6036b0d /arch
parent7990e90e7c4bff2d9dc1a1b5ff2201ebee997a11 (diff)
ENGR00277458-2 ARM: imx6q: Set pll3_pfd3_454m clock as spdif's parent
Provisionally use pll3_pfd3_454m clock as spdif's parent clock, which can fairly meet our playback and capture requirement. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 66aa00405b03..3c7fd8515496 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -511,6 +511,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
511 clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]); 511 clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]);
512 clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]); 512 clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]);
513 clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]); 513 clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]);
514 clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
514 515
515 /* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */ 516 /* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */
516 clk_set_rate(clk[pll4_audio_div], 541900800); 517 clk_set_rate(clk[pll4_audio_div], 541900800);