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authorRichard Zhu <r65037@freescale.com>2013-08-29 00:54:53 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:01:31 -0400
commita523a371b6157471753d0cb04295292324d99677 (patch)
tree7ae0c706a19dc8156c8222d7a02d093f2c56c19d /arch
parent28fd8737ec3845fc602484c30dcb6746f2fa9340 (diff)
ENGR00277241 imx: pcie: Re-correct the pcie dts
pcie dts node should be placed into imx6qdl dts file Signed-off-by: Richard Zhu <r65037@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi18
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi18
2 files changed, 18 insertions, 18 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 6353b927df55..ed515cd3f97f 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -132,24 +132,6 @@
132 status = "disabled"; 132 status = "disabled";
133 }; 133 };
134 134
135 pcie: pcie@01000000 {
136 compatible = "fsl,imx-pcie";
137 device_type = "pci";
138 reg = <0x01ffc000 0x4000>;
139 reg-names = "pcie_reg";
140 interrupts = <0 123 0x04>;
141 interrupt-names = "imx_pcie";
142 clocks = <&clks 144>, <&clks 189>, <&clks 211>, <&clks 212>;
143 clock-names = "pcie_axi", "pcie_ref", "pcie_bus_in", "pcie_bus_out";
144 #address-cells = <3>;
145 #size-cells = <2>;
146 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
147 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
148 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
149 num-lanes = <1>;
150 status = "disabled";
151 };
152
153 aips-bus@02000000 { /* AIPS1 */ 135 aips-bus@02000000 { /* AIPS1 */
154 spba-bus@02000000 { 136 spba-bus@02000000 {
155 ecspi5: ecspi@02018000 { 137 ecspi5: ecspi@02018000 {
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 53c6b5240b1a..a348bef4a737 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -116,6 +116,24 @@
116 interrupts = <0 94 0x04>; 116 interrupts = <0 94 0x04>;
117 }; 117 };
118 118
119 pcie: pcie@01000000 {
120 compatible = "fsl,imx-pcie";
121 device_type = "pci";
122 reg = <0x01ffc000 0x4000>;
123 reg-names = "pcie_reg";
124 interrupts = <0 123 0x04>;
125 interrupt-names = "imx_pcie";
126 clocks = <&clks 144>, <&clks 189>, <&clks 211>, <&clks 212>;
127 clock-names = "pcie_axi", "pcie_ref", "pcie_bus_in", "pcie_bus_out";
128 #address-cells = <3>;
129 #size-cells = <2>;
130 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
131 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
132 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
133 num-lanes = <1>;
134 status = "disabled";
135 };
136
119 aips-bus@02000000 { /* AIPS1 */ 137 aips-bus@02000000 { /* AIPS1 */
120 compatible = "fsl,aips-bus", "simple-bus"; 138 compatible = "fsl,aips-bus", "simple-bus";
121 #address-cells = <1>; 139 #address-cells = <1>;