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authorTang Yuantian <Yuantian.Tang@freescale.com>2012-07-12 22:27:35 -0400
committerKumar Gala <galak@kernel.crashing.org>2012-07-26 09:09:52 -0400
commit771e6089e3638ea1e06700a9dc4660cd678e35bb (patch)
tree8b627f2d9a0e3e2581fb4692a6571eb986079835 /arch
parent574ce79cea9d3fda109ffcc82f81733de4740e5c (diff)
powerpc/85xx: Fix pci base address error for p2020rdb-pc in dts
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/p2020rdb-pc_32b.dts4
-rw-r--r--arch/powerpc/boot/dts/p2020rdb-pc_36b.dts4
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
index 852e5b27485d..57573bd52caa 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
@@ -56,7 +56,7 @@
56 ranges = <0x0 0x0 0xffe00000 0x100000>; 56 ranges = <0x0 0x0 0xffe00000 0x100000>;
57 }; 57 };
58 58
59 pci0: pcie@ffe08000 { 59 pci2: pcie@ffe08000 {
60 reg = <0 0xffe08000 0 0x1000>; 60 reg = <0 0xffe08000 0 0x1000>;
61 status = "disabled"; 61 status = "disabled";
62 }; 62 };
@@ -76,7 +76,7 @@
76 }; 76 };
77 }; 77 };
78 78
79 pci2: pcie@ffe0a000 { 79 pci0: pcie@ffe0a000 {
80 reg = <0 0xffe0a000 0 0x1000>; 80 reg = <0 0xffe0a000 0 0x1000>;
81 ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000 81 ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
82 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 82 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
index b5a56ca51cf7..470247ea68b4 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
@@ -56,7 +56,7 @@
56 ranges = <0x0 0xf 0xffe00000 0x100000>; 56 ranges = <0x0 0xf 0xffe00000 0x100000>;
57 }; 57 };
58 58
59 pci0: pcie@fffe08000 { 59 pci2: pcie@fffe08000 {
60 reg = <0xf 0xffe08000 0 0x1000>; 60 reg = <0xf 0xffe08000 0 0x1000>;
61 status = "disabled"; 61 status = "disabled";
62 }; 62 };
@@ -76,7 +76,7 @@
76 }; 76 };
77 }; 77 };
78 78
79 pci2: pcie@fffe0a000 { 79 pci0: pcie@fffe0a000 {
80 reg = <0xf 0xffe0a000 0 0x1000>; 80 reg = <0xf 0xffe0a000 0 0x1000>;
81 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 81 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
82 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; 82 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;