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authorShawn Guo <shawn.guo@linaro.org>2013-05-02 23:26:30 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:00:34 -0400
commit6129960215037c6d4e4019512dc9c473c143f95b (patch)
tree77f6375388f8849e5762ff87c962bb5e568e0c51 /arch
parent218e0b20deac77c7fc552a5bc12fc6427bc301d5 (diff)
ARM: dts: add device tree source for imx6sl SoC
Commit e29fe21cff967eeae8f081ed0de51f53a2a002bf upstream. Add SoC level device tree source for imx6sl. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi779
1 files changed, 779 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
new file mode 100644
index 000000000000..c5e5da02d7e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -0,0 +1,779 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include "skeleton.dtsi"
11#include "imx6sl-pinfunc.h"
12#include <dt-bindings/clock/imx6sl-clock.h>
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 compatible = "arm,cortex-a9";
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38 };
39
40 intc: interrupt-controller@00a01000 {
41 compatible = "arm,cortex-a9-gic";
42 #interrupt-cells = <3>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 interrupt-controller;
46 reg = <0x00a01000 0x1000>,
47 <0x00a00100 0x100>;
48 };
49
50 clocks {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 ckil {
55 compatible = "fixed-clock";
56 clock-frequency = <32768>;
57 };
58
59 osc {
60 compatible = "fixed-clock";
61 clock-frequency = <24000000>;
62 };
63 };
64
65 soc {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "simple-bus";
69 interrupt-parent = <&intc>;
70 ranges;
71
72 L2: l2-cache@00a02000 {
73 compatible = "arm,pl310-cache";
74 reg = <0x00a02000 0x1000>;
75 interrupts = <0 92 0x04>;
76 cache-unified;
77 cache-level = <2>;
78 arm,tag-latency = <4 2 3>;
79 arm,data-latency = <4 2 3>;
80 };
81
82 pmu {
83 compatible = "arm,cortex-a9-pmu";
84 interrupts = <0 94 0x04>;
85 };
86
87 aips1: aips-bus@02000000 {
88 compatible = "fsl,aips-bus", "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 reg = <0x02000000 0x100000>;
92 ranges;
93
94 spba: spba-bus@02000000 {
95 compatible = "fsl,spba-bus", "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 reg = <0x02000000 0x40000>;
99 ranges;
100
101 spdif: spdif@02004000 {
102 reg = <0x02004000 0x4000>;
103 interrupts = <0 52 0x04>;
104 };
105
106 ecspi1: ecspi@02008000 {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
110 reg = <0x02008000 0x4000>;
111 interrupts = <0 31 0x04>;
112 clocks = <&clks IMX6SL_CLK_ECSPI1>,
113 <&clks IMX6SL_CLK_ECSPI1>;
114 clock-names = "ipg", "per";
115 status = "disabled";
116 };
117
118 ecspi2: ecspi@0200c000 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
122 reg = <0x0200c000 0x4000>;
123 interrupts = <0 32 0x04>;
124 clocks = <&clks IMX6SL_CLK_ECSPI2>,
125 <&clks IMX6SL_CLK_ECSPI2>;
126 clock-names = "ipg", "per";
127 status = "disabled";
128 };
129
130 ecspi3: ecspi@02010000 {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
134 reg = <0x02010000 0x4000>;
135 interrupts = <0 33 0x04>;
136 clocks = <&clks IMX6SL_CLK_ECSPI3>,
137 <&clks IMX6SL_CLK_ECSPI3>;
138 clock-names = "ipg", "per";
139 status = "disabled";
140 };
141
142 ecspi4: ecspi@02014000 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
146 reg = <0x02014000 0x4000>;
147 interrupts = <0 34 0x04>;
148 clocks = <&clks IMX6SL_CLK_ECSPI4>,
149 <&clks IMX6SL_CLK_ECSPI4>;
150 clock-names = "ipg", "per";
151 status = "disabled";
152 };
153
154 uart5: serial@02018000 {
155 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
156 reg = <0x02018000 0x4000>;
157 interrupts = <0 30 0x04>;
158 clocks = <&clks IMX6SL_CLK_UART>,
159 <&clks IMX6SL_CLK_UART_SERIAL>;
160 clock-names = "ipg", "per";
161 status = "disabled";
162 };
163
164 uart1: serial@02020000 {
165 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
166 reg = <0x02020000 0x4000>;
167 interrupts = <0 26 0x04>;
168 clocks = <&clks IMX6SL_CLK_UART>,
169 <&clks IMX6SL_CLK_UART_SERIAL>;
170 clock-names = "ipg", "per";
171 status = "disabled";
172 };
173
174 uart2: serial@02024000 {
175 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
176 reg = <0x02024000 0x4000>;
177 interrupts = <0 27 0x04>;
178 clocks = <&clks IMX6SL_CLK_UART>,
179 <&clks IMX6SL_CLK_UART_SERIAL>;
180 clock-names = "ipg", "per";
181 status = "disabled";
182 };
183
184 ssi1: ssi@02028000 {
185 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
186 reg = <0x02028000 0x4000>;
187 interrupts = <0 46 0x04>;
188 clocks = <&clks IMX6SL_CLK_SSI1>;
189 fsl,fifo-depth = <15>;
190 status = "disabled";
191 };
192
193 ssi2: ssi@0202c000 {
194 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
195 reg = <0x0202c000 0x4000>;
196 interrupts = <0 47 0x04>;
197 clocks = <&clks IMX6SL_CLK_SSI2>;
198 fsl,fifo-depth = <15>;
199 status = "disabled";
200 };
201
202 ssi3: ssi@02030000 {
203 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
204 reg = <0x02030000 0x4000>;
205 interrupts = <0 48 0x04>;
206 clocks = <&clks IMX6SL_CLK_SSI3>;
207 fsl,fifo-depth = <15>;
208 status = "disabled";
209 };
210
211 uart3: serial@02034000 {
212 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
213 reg = <0x02034000 0x4000>;
214 interrupts = <0 28 0x04>;
215 clocks = <&clks IMX6SL_CLK_UART>,
216 <&clks IMX6SL_CLK_UART_SERIAL>;
217 clock-names = "ipg", "per";
218 status = "disabled";
219 };
220
221 uart4: serial@02038000 {
222 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
223 reg = <0x02038000 0x4000>;
224 interrupts = <0 29 0x04>;
225 clocks = <&clks IMX6SL_CLK_UART>,
226 <&clks IMX6SL_CLK_UART_SERIAL>;
227 clock-names = "ipg", "per";
228 status = "disabled";
229 };
230 };
231
232 pwm1: pwm@02080000 {
233 #pwm-cells = <2>;
234 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
235 reg = <0x02080000 0x4000>;
236 interrupts = <0 83 0x04>;
237 clocks = <&clks IMX6SL_CLK_PWM1>,
238 <&clks IMX6SL_CLK_PWM1>;
239 clock-names = "ipg", "per";
240 };
241
242 pwm2: pwm@02084000 {
243 #pwm-cells = <2>;
244 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
245 reg = <0x02084000 0x4000>;
246 interrupts = <0 84 0x04>;
247 clocks = <&clks IMX6SL_CLK_PWM2>,
248 <&clks IMX6SL_CLK_PWM2>;
249 clock-names = "ipg", "per";
250 };
251
252 pwm3: pwm@02088000 {
253 #pwm-cells = <2>;
254 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
255 reg = <0x02088000 0x4000>;
256 interrupts = <0 85 0x04>;
257 clocks = <&clks IMX6SL_CLK_PWM3>,
258 <&clks IMX6SL_CLK_PWM3>;
259 clock-names = "ipg", "per";
260 };
261
262 pwm4: pwm@0208c000 {
263 #pwm-cells = <2>;
264 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
265 reg = <0x0208c000 0x4000>;
266 interrupts = <0 86 0x04>;
267 clocks = <&clks IMX6SL_CLK_PWM4>,
268 <&clks IMX6SL_CLK_PWM4>;
269 clock-names = "ipg", "per";
270 };
271
272 gpt: gpt@02098000 {
273 compatible = "fsl,imx6sl-gpt";
274 reg = <0x02098000 0x4000>;
275 interrupts = <0 55 0x04>;
276 clocks = <&clks IMX6SL_CLK_GPT>,
277 <&clks IMX6SL_CLK_GPT_SERIAL>;
278 clock-names = "ipg", "per";
279 };
280
281 gpio1: gpio@0209c000 {
282 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
283 reg = <0x0209c000 0x4000>;
284 interrupts = <0 66 0x04 0 67 0x04>;
285 gpio-controller;
286 #gpio-cells = <2>;
287 interrupt-controller;
288 #interrupt-cells = <2>;
289 };
290
291 gpio2: gpio@020a0000 {
292 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
293 reg = <0x020a0000 0x4000>;
294 interrupts = <0 68 0x04 0 69 0x04>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 };
300
301 gpio3: gpio@020a4000 {
302 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
303 reg = <0x020a4000 0x4000>;
304 interrupts = <0 70 0x04 0 71 0x04>;
305 gpio-controller;
306 #gpio-cells = <2>;
307 interrupt-controller;
308 #interrupt-cells = <2>;
309 };
310
311 gpio4: gpio@020a8000 {
312 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
313 reg = <0x020a8000 0x4000>;
314 interrupts = <0 72 0x04 0 73 0x04>;
315 gpio-controller;
316 #gpio-cells = <2>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 };
320
321 gpio5: gpio@020ac000 {
322 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
323 reg = <0x020ac000 0x4000>;
324 interrupts = <0 74 0x04 0 75 0x04>;
325 gpio-controller;
326 #gpio-cells = <2>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
329 };
330
331 kpp: kpp@020b8000 {
332 reg = <0x020b8000 0x4000>;
333 interrupts = <0 82 0x04>;
334 };
335
336 wdog1: wdog@020bc000 {
337 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
338 reg = <0x020bc000 0x4000>;
339 interrupts = <0 80 0x04>;
340 clocks = <&clks IMX6SL_CLK_DUMMY>;
341 };
342
343 wdog2: wdog@020c0000 {
344 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
345 reg = <0x020c0000 0x4000>;
346 interrupts = <0 81 0x04>;
347 clocks = <&clks IMX6SL_CLK_DUMMY>;
348 status = "disabled";
349 };
350
351 clks: ccm@020c4000 {
352 compatible = "fsl,imx6sl-ccm";
353 reg = <0x020c4000 0x4000>;
354 interrupts = <0 87 0x04 0 88 0x04>;
355 #clock-cells = <1>;
356 };
357
358 anatop: anatop@020c8000 {
359 compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
360 reg = <0x020c8000 0x1000>;
361 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
362
363 regulator-1p1@110 {
364 compatible = "fsl,anatop-regulator";
365 regulator-name = "vdd1p1";
366 regulator-min-microvolt = <800000>;
367 regulator-max-microvolt = <1375000>;
368 regulator-always-on;
369 anatop-reg-offset = <0x110>;
370 anatop-vol-bit-shift = <8>;
371 anatop-vol-bit-width = <5>;
372 anatop-min-bit-val = <4>;
373 anatop-min-voltage = <800000>;
374 anatop-max-voltage = <1375000>;
375 };
376
377 regulator-3p0@120 {
378 compatible = "fsl,anatop-regulator";
379 regulator-name = "vdd3p0";
380 regulator-min-microvolt = <2800000>;
381 regulator-max-microvolt = <3150000>;
382 regulator-always-on;
383 anatop-reg-offset = <0x120>;
384 anatop-vol-bit-shift = <8>;
385 anatop-vol-bit-width = <5>;
386 anatop-min-bit-val = <0>;
387 anatop-min-voltage = <2625000>;
388 anatop-max-voltage = <3400000>;
389 };
390
391 regulator-2p5@130 {
392 compatible = "fsl,anatop-regulator";
393 regulator-name = "vdd2p5";
394 regulator-min-microvolt = <2100000>;
395 regulator-max-microvolt = <2850000>;
396 regulator-always-on;
397 anatop-reg-offset = <0x130>;
398 anatop-vol-bit-shift = <8>;
399 anatop-vol-bit-width = <5>;
400 anatop-min-bit-val = <0>;
401 anatop-min-voltage = <2100000>;
402 anatop-max-voltage = <2850000>;
403 };
404
405 reg_arm: regulator-vddcore@140 {
406 compatible = "fsl,anatop-regulator";
407 regulator-name = "cpu";
408 regulator-min-microvolt = <725000>;
409 regulator-max-microvolt = <1450000>;
410 regulator-always-on;
411 anatop-reg-offset = <0x140>;
412 anatop-vol-bit-shift = <0>;
413 anatop-vol-bit-width = <5>;
414 anatop-delay-reg-offset = <0x170>;
415 anatop-delay-bit-shift = <24>;
416 anatop-delay-bit-width = <2>;
417 anatop-min-bit-val = <1>;
418 anatop-min-voltage = <725000>;
419 anatop-max-voltage = <1450000>;
420 };
421
422 reg_pu: regulator-vddpu@140 {
423 compatible = "fsl,anatop-regulator";
424 regulator-name = "vddpu";
425 regulator-min-microvolt = <725000>;
426 regulator-max-microvolt = <1450000>;
427 regulator-always-on;
428 anatop-reg-offset = <0x140>;
429 anatop-vol-bit-shift = <9>;
430 anatop-vol-bit-width = <5>;
431 anatop-delay-reg-offset = <0x170>;
432 anatop-delay-bit-shift = <26>;
433 anatop-delay-bit-width = <2>;
434 anatop-min-bit-val = <1>;
435 anatop-min-voltage = <725000>;
436 anatop-max-voltage = <1450000>;
437 };
438
439 reg_soc: regulator-vddsoc@140 {
440 compatible = "fsl,anatop-regulator";
441 regulator-name = "vddsoc";
442 regulator-min-microvolt = <725000>;
443 regulator-max-microvolt = <1450000>;
444 regulator-always-on;
445 anatop-reg-offset = <0x140>;
446 anatop-vol-bit-shift = <18>;
447 anatop-vol-bit-width = <5>;
448 anatop-delay-reg-offset = <0x170>;
449 anatop-delay-bit-shift = <28>;
450 anatop-delay-bit-width = <2>;
451 anatop-min-bit-val = <1>;
452 anatop-min-voltage = <725000>;
453 anatop-max-voltage = <1450000>;
454 };
455 };
456
457 usbphy1: usbphy@020c9000 {
458 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
459 reg = <0x020c9000 0x1000>;
460 interrupts = <0 44 0x04>;
461 clocks = <&clks IMX6SL_CLK_USBPHY1>;
462 };
463
464 usbphy2: usbphy@020ca000 {
465 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
466 reg = <0x020ca000 0x1000>;
467 interrupts = <0 45 0x04>;
468 clocks = <&clks IMX6SL_CLK_USBPHY2>;
469 };
470
471 snvs@020cc000 {
472 compatible = "fsl,sec-v4.0-mon", "simple-bus";
473 #address-cells = <1>;
474 #size-cells = <1>;
475 ranges = <0 0x020cc000 0x4000>;
476
477 snvs-rtc-lp@34 {
478 compatible = "fsl,sec-v4.0-mon-rtc-lp";
479 reg = <0x34 0x58>;
480 interrupts = <0 19 0x04 0 20 0x04>;
481 };
482 };
483
484 epit1: epit@020d0000 {
485 reg = <0x020d0000 0x4000>;
486 interrupts = <0 56 0x04>;
487 };
488
489 epit2: epit@020d4000 {
490 reg = <0x020d4000 0x4000>;
491 interrupts = <0 57 0x04>;
492 };
493
494 src: src@020d8000 {
495 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
496 reg = <0x020d8000 0x4000>;
497 interrupts = <0 91 0x04 0 96 0x04>;
498 #reset-cells = <1>;
499 };
500
501 gpc: gpc@020dc000 {
502 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
503 reg = <0x020dc000 0x4000>;
504 interrupts = <0 89 0x04>;
505 };
506
507 iomuxc: iomuxc@020e0000 {
508 compatible = "fsl,imx6sl-iomuxc";
509 reg = <0x020e0000 0x4000>;
510
511 fec {
512 pinctrl_fec_1: fecgrp-1 {
513 fsl,pins = <
514 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
515 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
516 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
517 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
518 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
519 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
520 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
521 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
522 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
523 >;
524 };
525 };
526
527 uart1 {
528 pinctrl_uart1_1: uart1grp-1 {
529 fsl,pins = <
530 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
531 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
532 >;
533 };
534 };
535
536 usdhc1 {
537 pinctrl_usdhc1_1: usdhc1grp-1 {
538 fsl,pins = <
539 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
540 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
541 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
542 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
543 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
544 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
545 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
546 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
547 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
548 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
549 >;
550 };
551 };
552
553 usdhc2 {
554 pinctrl_usdhc2_1: usdhc2grp-1 {
555 fsl,pins = <
556 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
557 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
558 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
559 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
560 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
561 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
562 >;
563 };
564 };
565
566 usdhc3 {
567 pinctrl_usdhc3_1: usdhc3grp-1 {
568 fsl,pins = <
569 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
570 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
571 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
572 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
573 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
574 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
575 >;
576 };
577 };
578 };
579
580 csi: csi@020e4000 {
581 reg = <0x020e4000 0x4000>;
582 interrupts = <0 7 0x04>;
583 };
584
585 spdc: spdc@020e8000 {
586 reg = <0x020e8000 0x4000>;
587 interrupts = <0 6 0x04>;
588 };
589
590 sdma: sdma@020ec000 {
591 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
592 reg = <0x020ec000 0x4000>;
593 interrupts = <0 2 0x04>;
594 clocks = <&clks IMX6SL_CLK_SDMA>,
595 <&clks IMX6SL_CLK_SDMA>;
596 clock-names = "ipg", "ahb";
597 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
598 };
599
600 pxp: pxp@020f0000 {
601 reg = <0x020f0000 0x4000>;
602 interrupts = <0 98 0x04>;
603 };
604
605 epdc: epdc@020f4000 {
606 reg = <0x020f4000 0x4000>;
607 interrupts = <0 97 0x04>;
608 };
609
610 lcdif: lcdif@020f8000 {
611 reg = <0x020f8000 0x4000>;
612 interrupts = <0 39 0x04>;
613 };
614
615 dcp: dcp@020fc000 {
616 reg = <0x020fc000 0x4000>;
617 interrupts = <0 99 0x04>;
618 };
619 };
620
621 aips2: aips-bus@02100000 {
622 compatible = "fsl,aips-bus", "simple-bus";
623 #address-cells = <1>;
624 #size-cells = <1>;
625 reg = <0x02100000 0x100000>;
626 ranges;
627
628 usbotg1: usb@02184000 {
629 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
630 reg = <0x02184000 0x200>;
631 interrupts = <0 43 0x04>;
632 clocks = <&clks IMX6SL_CLK_USBOH3>;
633 fsl,usbphy = <&usbphy1>;
634 fsl,usbmisc = <&usbmisc 0>;
635 status = "disabled";
636 };
637
638 usbotg2: usb@02184200 {
639 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
640 reg = <0x02184200 0x200>;
641 interrupts = <0 40 0x04>;
642 clocks = <&clks IMX6SL_CLK_USBOH3>;
643 fsl,usbphy = <&usbphy2>;
644 fsl,usbmisc = <&usbmisc 1>;
645 status = "disabled";
646 };
647
648 usbh: usb@02184400 {
649 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
650 reg = <0x02184400 0x200>;
651 interrupts = <0 42 0x04>;
652 clocks = <&clks IMX6SL_CLK_USBOH3>;
653 fsl,usbmisc = <&usbmisc 2>;
654 status = "disabled";
655 };
656
657 usbmisc: usbmisc@02184800 {
658 #index-cells = <1>;
659 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
660 reg = <0x02184800 0x200>;
661 clocks = <&clks IMX6SL_CLK_USBOH3>;
662 };
663
664 fec: ethernet@02188000 {
665 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
666 reg = <0x02188000 0x4000>;
667 interrupts = <0 114 0x04>;
668 clocks = <&clks IMX6SL_CLK_ENET_REF>,
669 <&clks IMX6SL_CLK_ENET_REF>;
670 clock-names = "ipg", "ahb";
671 status = "disabled";
672 };
673
674 usdhc1: usdhc@02190000 {
675 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
676 reg = <0x02190000 0x4000>;
677 interrupts = <0 22 0x04>;
678 clocks = <&clks IMX6SL_CLK_USDHC1>,
679 <&clks IMX6SL_CLK_USDHC1>,
680 <&clks IMX6SL_CLK_USDHC1>;
681 clock-names = "ipg", "ahb", "per";
682 bus-width = <4>;
683 status = "disabled";
684 };
685
686 usdhc2: usdhc@02194000 {
687 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
688 reg = <0x02194000 0x4000>;
689 interrupts = <0 23 0x04>;
690 clocks = <&clks IMX6SL_CLK_USDHC2>,
691 <&clks IMX6SL_CLK_USDHC2>,
692 <&clks IMX6SL_CLK_USDHC2>;
693 clock-names = "ipg", "ahb", "per";
694 bus-width = <4>;
695 status = "disabled";
696 };
697
698 usdhc3: usdhc@02198000 {
699 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
700 reg = <0x02198000 0x4000>;
701 interrupts = <0 24 0x04>;
702 clocks = <&clks IMX6SL_CLK_USDHC3>,
703 <&clks IMX6SL_CLK_USDHC3>,
704 <&clks IMX6SL_CLK_USDHC3>;
705 clock-names = "ipg", "ahb", "per";
706 bus-width = <4>;
707 status = "disabled";
708 };
709
710 usdhc4: usdhc@0219c000 {
711 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
712 reg = <0x0219c000 0x4000>;
713 interrupts = <0 25 0x04>;
714 clocks = <&clks IMX6SL_CLK_USDHC4>,
715 <&clks IMX6SL_CLK_USDHC4>,
716 <&clks IMX6SL_CLK_USDHC4>;
717 clock-names = "ipg", "ahb", "per";
718 bus-width = <4>;
719 status = "disabled";
720 };
721
722 i2c1: i2c@021a0000 {
723 #address-cells = <1>;
724 #size-cells = <0>;
725 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
726 reg = <0x021a0000 0x4000>;
727 interrupts = <0 36 0x04>;
728 clocks = <&clks IMX6SL_CLK_I2C1>;
729 status = "disabled";
730 };
731
732 i2c2: i2c@021a4000 {
733 #address-cells = <1>;
734 #size-cells = <0>;
735 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
736 reg = <0x021a4000 0x4000>;
737 interrupts = <0 37 0x04>;
738 clocks = <&clks IMX6SL_CLK_I2C2>;
739 status = "disabled";
740 };
741
742 i2c3: i2c@021a8000 {
743 #address-cells = <1>;
744 #size-cells = <0>;
745 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
746 reg = <0x021a8000 0x4000>;
747 interrupts = <0 38 0x04>;
748 clocks = <&clks IMX6SL_CLK_I2C3>;
749 status = "disabled";
750 };
751
752 mmdc: mmdc@021b0000 {
753 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
754 reg = <0x021b0000 0x4000>;
755 };
756
757 rngb: rngb@021b4000 {
758 reg = <0x021b4000 0x4000>;
759 interrupts = <0 5 0x04>;
760 };
761
762 weim: weim@021b8000 {
763 reg = <0x021b8000 0x4000>;
764 interrupts = <0 14 0x04>;
765 };
766
767 ocotp: ocotp@021bc000 {
768 compatible = "fsl,imx6sl-ocotp";
769 reg = <0x021bc000 0x4000>;
770 };
771
772 audmux: audmux@021d8000 {
773 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
774 reg = <0x021d8000 0x4000>;
775 status = "disabled";
776 };
777 };
778 };
779};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 00:55:06 -0500