aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorRussell King <rmk+kernel@arm.linux.org.uk>2010-07-29 10:48:02 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-07-29 10:48:02 -0400
commit129961ecaf21c9ee899ad9067d917c1aa172fb7a (patch)
tree49eafdcf4d6ac490ecdd92c36c285817872eaf34 /arch
parent392c57a2ec811db37ae45adc513704cf92ba3e69 (diff)
parentcccf59abea4e1c36322e365d6e61ff7de1f3ee07 (diff)
Merge branch 'wells/lpc32xx-arch_v2' of git://git.lpclinux.com/linux-2.6-lpc into devel-stable
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig15
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/mach-clps711x/include/mach/debug-macro.S1
-rw-r--r--arch/arm/mach-footbridge/common.c2
-rw-r--r--arch/arm/mach-h720x/include/mach/debug-macro.S6
-rw-r--r--arch/arm/mach-kirkwood/tsx1x-common.h2
-rw-r--r--arch/arm/mach-lpc32xx/Kconfig33
-rw-r--r--arch/arm/mach-lpc32xx/Makefile8
-rw-r--r--arch/arm/mach-lpc32xx/Makefile.boot4
-rw-r--r--arch/arm/mach-lpc32xx/clock.c1137
-rw-r--r--arch/arm/mach-lpc32xx/clock.h38
-rw-r--r--arch/arm/mach-lpc32xx/common.c271
-rw-r--r--arch/arm/mach-lpc32xx/common.h73
-rw-r--r--arch/arm/mach-lpc32xx/gpiolib.c446
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/clkdev.h25
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/debug-macro.S31
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/entry-macro.S47
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/gpio.h74
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/hardware.h34
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/i2c.h63
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/io.h27
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/irqs.h117
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/memory.h27
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/platform.h694
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/system.h52
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/timex.h28
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/uncompress.h60
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/vmalloc.h24
-rw-r--r--arch/arm/mach-lpc32xx/irq.c432
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c397
-rw-r--r--arch/arm/mach-lpc32xx/pm.c146
-rw-r--r--arch/arm/mach-lpc32xx/serial.c190
-rw-r--r--arch/arm/mach-lpc32xx/suspend.S151
-rw-r--r--arch/arm/mach-lpc32xx/timer.c182
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/debug-macro.S1
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/uncompress.h30
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c17
-rw-r--r--arch/arm/mach-pxa/colibri-pxa300.c3
-rw-r--r--arch/arm/mach-pxa/corgi.c2
-rw-r--r--arch/arm/mach-pxa/cpufreq-pxa2xx.c8
-rw-r--r--arch/arm/mach-pxa/pxa27x.c6
-rw-r--r--arch/arm/mach-shark/include/mach/debug-macro.S3
-rw-r--r--arch/arm/mach-w90x900/cpu.c2
-rw-r--r--arch/arm/plat-spear/include/plat/debug-macro.S4
-rw-r--r--arch/avr32/include/asm/ioctls.h3
-rw-r--r--arch/avr32/mach-at32ap/include/mach/board.h2
-rw-r--r--arch/mips/alchemy/common/platform.c9
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c8
-rw-r--r--arch/mips/bcm63xx/dev-enet.c3
-rw-r--r--arch/mips/include/asm/atomic.h24
-rw-r--r--arch/mips/include/asm/unistd.h5
-rw-r--r--arch/mips/kernel/scall64-n32.S1
-rw-r--r--arch/mips/kernel/vdso.c4
-rw-r--r--arch/mips/mti-malta/malta-pci.c2
-rw-r--r--arch/mips/nxp/pnx8550/common/pci.c1
-rw-r--r--arch/mips/nxp/pnx8550/common/setup.c2
-rw-r--r--arch/mips/pci/ops-pmcmsp.c1
-rw-r--r--arch/mips/pci/pci-yosemite.c1
-rw-r--r--arch/mips/powertv/asic/asic_devices.c5
-rw-r--r--arch/powerpc/include/asm/kexec.h6
-rw-r--r--arch/powerpc/include/asm/mmu-hash64.h4
-rw-r--r--arch/powerpc/kernel/perf_event_fsl_emb.c6
-rw-r--r--arch/powerpc/kernel/prom.c2
-rw-r--r--arch/powerpc/mm/hash_low_64.S9
-rw-r--r--arch/powerpc/mm/hash_utils_64.c53
-rw-r--r--arch/powerpc/mm/hugetlbpage-hash64.c40
-rw-r--r--arch/powerpc/mm/numa.c24
-rw-r--r--arch/powerpc/platforms/pseries/hotplug-memory.c22
-rw-r--r--arch/sparc/configs/sparc64_defconfig49
-rw-r--r--arch/sparc/include/asm/cache.h1
-rw-r--r--arch/sparc/include/asm/pgtable_32.h5
-rw-r--r--arch/sparc/kernel/perf_event.c1
-rw-r--r--arch/sparc/kernel/sun4d_irq.c2
-rw-r--r--arch/sparc/kernel/ttable.S2
-rw-r--r--arch/sparc/mm/srmmu.c2
-rw-r--r--arch/sparc/mm/sun4c.c3
-rw-r--r--arch/x86/kernel/acpi/cstate.c9
-rw-r--r--arch/x86/kernel/acpi/sleep.c9
-rw-r--r--arch/x86/kernel/apic/apic.c2
-rw-r--r--arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c41
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k8.c11
-rw-r--r--arch/x86/kernel/early-quirks.c18
-rw-r--r--arch/x86/kernel/entry_64.S4
-rw-r--r--arch/x86/kernel/hpet.c2
-rw-r--r--arch/x86/kernel/i8259.c25
-rw-r--r--arch/x86/kernel/kprobes.c2
-rw-r--r--arch/x86/kernel/quirks.c5
-rw-r--r--arch/x86/kernel/setup_percpu.c17
-rw-r--r--arch/x86/kvm/mmu.c2
-rw-r--r--arch/x86/kvm/paging_tmpl.h1
-rw-r--r--arch/x86/kvm/x86.c4
-rw-r--r--arch/x86/pci/i386.c1
-rw-r--r--arch/x86/pci/mrst.c7
93 files changed, 5152 insertions, 224 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c1e0cdfd1147..738f404d5e34 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -483,6 +483,19 @@ config ARCH_LOKI
483 help 483 help
484 Support for the Marvell Loki (88RC8480) SoC. 484 Support for the Marvell Loki (88RC8480) SoC.
485 485
486config ARCH_LPC32XX
487 bool "NXP LPC32XX"
488 select CPU_ARM926T
489 select ARCH_REQUIRE_GPIOLIB
490 select HAVE_IDE
491 select ARM_AMBA
492 select USB_ARCH_HAS_OHCI
493 select COMMON_CLKDEV
494 select GENERIC_TIME
495 select GENERIC_CLOCKEVENTS
496 help
497 Support for the NXP LPC32XX family of processors
498
486config ARCH_MV78XX0 499config ARCH_MV78XX0
487 bool "Marvell MV78xx0" 500 bool "Marvell MV78xx0"
488 select CPU_FEROCEON 501 select CPU_FEROCEON
@@ -847,6 +860,8 @@ source "arch/arm/mach-lh7a40x/Kconfig"
847 860
848source "arch/arm/mach-loki/Kconfig" 861source "arch/arm/mach-loki/Kconfig"
849 862
863source "arch/arm/mach-lpc32xx/Kconfig"
864
850source "arch/arm/mach-msm/Kconfig" 865source "arch/arm/mach-msm/Kconfig"
851 866
852source "arch/arm/mach-mv78xx0/Kconfig" 867source "arch/arm/mach-mv78xx0/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ddf6da158ad8..71cbb17ff89c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -146,6 +146,7 @@ machine-$(CONFIG_ARCH_KS8695) := ks8695
146machine-$(CONFIG_ARCH_L7200) := l7200 146machine-$(CONFIG_ARCH_L7200) := l7200
147machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x 147machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
148machine-$(CONFIG_ARCH_LOKI) := loki 148machine-$(CONFIG_ARCH_LOKI) := loki
149machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
149machine-$(CONFIG_ARCH_MMP) := mmp 150machine-$(CONFIG_ARCH_MMP) := mmp
150machine-$(CONFIG_ARCH_MSM) := msm 151machine-$(CONFIG_ARCH_MSM) := msm
151machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 152machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index fedd8076a689..072cc6b61ba3 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -11,6 +11,7 @@
11 * 11 *
12*/ 12*/
13 13
14#include <mach/hardware.h>
14#include <asm/hardware/clps7111.h> 15#include <asm/hardware/clps7111.h>
15 16
16 .macro addruart, rx, tmp 17 .macro addruart, rx, tmp
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index e3bc3f6f6b10..88b3dd89be89 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -232,7 +232,7 @@ EXPORT_SYMBOL(__bus_to_virt);
232 232
233unsigned long __pfn_to_bus(unsigned long pfn) 233unsigned long __pfn_to_bus(unsigned long pfn)
234{ 234{
235 return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET)); 235 return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
236} 236}
237EXPORT_SYMBOL(__pfn_to_bus); 237EXPORT_SYMBOL(__pfn_to_bus);
238 238
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
index a9ee8f0d48b7..27cafd12f033 100644
--- a/arch/arm/mach-h720x/include/mach/debug-macro.S
+++ b/arch/arm/mach-h720x/include/mach/debug-macro.S
@@ -11,8 +11,10 @@
11 * 11 *
12*/ 12*/
13 13
14 .equ io_virt, IO_BASE 14#include <mach/hardware.h>
15 .equ io_phys, IO_START 15
16 .equ io_virt, IO_VIRT
17 .equ io_phys, IO_PHYS
16 18
17 .macro addruart, rx, tmp 19 .macro addruart, rx, tmp
18 mrc p15, 0, \rx, c1, c0 20 mrc p15, 0, \rx, c1, c0
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.h b/arch/arm/mach-kirkwood/tsx1x-common.h
index 9a592962a6ea..7fa037361b55 100644
--- a/arch/arm/mach-kirkwood/tsx1x-common.h
+++ b/arch/arm/mach-kirkwood/tsx1x-common.h
@@ -1,7 +1,7 @@
1#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H 1#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H
2#define __ARCH_KIRKWOOD_TSX1X_COMMON_H 2#define __ARCH_KIRKWOOD_TSX1X_COMMON_H
3 3
4extern void qnap_tsx1x_register_flash(void); 4extern void __init qnap_tsx1x_register_flash(void);
5extern void qnap_tsx1x_power_off(void); 5extern void qnap_tsx1x_power_off(void);
6 6
7#endif 7#endif
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
new file mode 100644
index 000000000000..fde663508696
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -0,0 +1,33 @@
1if ARCH_LPC32XX
2
3menu "Individual UART enable selections"
4
5config ARCH_LPC32XX_UART3_SELECT
6 bool "Add support for standard UART3"
7 help
8 Adds support for standard UART 3 when the 8250 serial support
9 is enabled.
10
11config ARCH_LPC32XX_UART4_SELECT
12 bool "Add support for standard UART4"
13 help
14 Adds support for standard UART 4 when the 8250 serial support
15 is enabled.
16
17config ARCH_LPC32XX_UART5_SELECT
18 bool "Add support for standard UART5"
19 default y
20 help
21 Adds support for standard UART 5 when the 8250 serial support
22 is enabled.
23
24config ARCH_LPC32XX_UART6_SELECT
25 bool "Add support for standard UART6"
26 help
27 Adds support for standard UART 6 when the 8250 serial support
28 is enabled.
29
30endmenu
31
32endif
33
diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile
new file mode 100644
index 000000000000..a5fc5d0eeaeb
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := timer.o irq.o common.o serial.o clock.o
6obj-y += gpiolib.o pm.o suspend.o
7obj-y += phy3250.o
8
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
new file mode 100644
index 000000000000..b796b41ebf8f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Makefile.boot
@@ -0,0 +1,4 @@
1 zreladdr-y := 0x80008000
2params_phys-y := 0x80000100
3initrd_phys-y := 0x82000000
4
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
new file mode 100644
index 000000000000..32d63796430a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -0,0 +1,1137 @@
1/*
2 * arch/arm/mach-lpc32xx/clock.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19/*
20 * LPC32xx clock management driver overview
21 *
22 * The LPC32XX contains a number of high level system clocks that can be
23 * generated from different sources. These system clocks are used to
24 * generate the CPU and bus rates and the individual peripheral clocks in
25 * the system. When Linux is started by the boot loader, the system
26 * clocks are already running. Stopping a system clock during normal
27 * Linux operation should never be attempted, as peripherals that require
28 * those clocks will quit working (ie, DRAM).
29 *
30 * The LPC32xx high level clock tree looks as follows. Clocks marked with
31 * an asterisk are always on and cannot be disabled. Clocks marked with
32 * an ampersand can only be disabled in CPU suspend mode. Clocks marked
33 * with a caret are always on if it is the selected clock for the SYSCLK
34 * source. The clock that isn't used for SYSCLK can be enabled and
35 * disabled normally.
36 * 32KHz oscillator*
37 * / | \
38 * RTC* PLL397^ TOUCH
39 * /
40 * Main oscillator^ /
41 * | \ /
42 * | SYSCLK&
43 * | \
44 * | \
45 * USB_PLL HCLK_PLL&
46 * | | |
47 * USB host/device PCLK& |
48 * | |
49 * Peripherals
50 *
51 * The CPU and chip bus rates are derived from the HCLK PLL, which can
52 * generate various clock rates up to 266MHz and beyond. The internal bus
53 * rates (PCLK and HCLK) are generated from dividers based on the HCLK
54 * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
55 * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
56 * level clocks are based on either HCLK or PCLK, but have their own
57 * dividers as part of the IP itself. Because of this, the system clock
58 * rates should not be changed.
59 *
60 * The HCLK PLL is clocked from SYSCLK, which can be derived from the
61 * main oscillator or PLL397. PLL397 generates a rate that is 397 times
62 * the 32KHz oscillator rate. The main oscillator runs at the selected
63 * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
64 * is normally 13MHz, but depends on the selection of external crystals
65 * or oscillators. If USB operation is required, the main oscillator must
66 * be used in the system.
67 *
68 * Switching SYSCLK between sources during normal Linux operation is not
69 * supported. SYSCLK is preset in the bootloader. Because of the
70 * complexities of clock management during clock frequency changes,
71 * there are some limitations to the clock driver explained below:
72 * - The PLL397 and main oscillator can be enabled and disabled by the
73 * clk_enable() and clk_disable() functions unless SYSCLK is based
74 * on that clock. This allows the other oscillator that isn't driving
75 * the HCLK PLL to be used as another system clock that can be routed
76 * to an external pin.
77 * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
78 * this driver.
79 * - HCLK and PCLK rates cannot be changed as part of this driver.
80 * - Most peripherals have their own dividers are part of the peripheral
81 * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
82 * will also impact the individual peripheral rates.
83 */
84
85#include <linux/kernel.h>
86#include <linux/list.h>
87#include <linux/errno.h>
88#include <linux/device.h>
89#include <linux/err.h>
90#include <linux/clk.h>
91#include <linux/amba/bus.h>
92#include <linux/amba/clcd.h>
93
94#include <mach/hardware.h>
95#include <asm/clkdev.h>
96#include <mach/clkdev.h>
97#include <mach/platform.h>
98#include "clock.h"
99#include "common.h"
100
101static struct clk clk_armpll;
102static struct clk clk_usbpll;
103static DEFINE_MUTEX(clkm_lock);
104
105/*
106 * Post divider values for PLLs based on selected register value
107 */
108static const u32 pll_postdivs[4] = {1, 2, 4, 8};
109
110static unsigned long local_return_parent_rate(struct clk *clk)
111{
112 /*
113 * If a clock has a rate of 0, then it inherits it's parent
114 * clock rate
115 */
116 while (clk->rate == 0)
117 clk = clk->parent;
118
119 return clk->rate;
120}
121
122/* 32KHz clock has a fixed rate and is not stoppable */
123static struct clk osc_32KHz = {
124 .rate = LPC32XX_CLOCK_OSC_FREQ,
125 .get_rate = local_return_parent_rate,
126};
127
128static int local_pll397_enable(struct clk *clk, int enable)
129{
130 u32 reg;
131 unsigned long timeout = 1 + msecs_to_jiffies(10);
132
133 reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
134
135 if (enable == 0) {
136 reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
137 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
138 } else {
139 /* Enable PLL397 */
140 reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
141 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
142
143 /* Wait for PLL397 lock */
144 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
145 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
146 (timeout > jiffies))
147 cpu_relax();
148
149 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
150 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
151 return -ENODEV;
152 }
153
154 return 0;
155}
156
157static int local_oscmain_enable(struct clk *clk, int enable)
158{
159 u32 reg;
160 unsigned long timeout = 1 + msecs_to_jiffies(10);
161
162 reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
163
164 if (enable == 0) {
165 reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
166 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
167 } else {
168 /* Enable main oscillator */
169 reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
170 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
171
172 /* Wait for main oscillator to start */
173 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
174 LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
175 (timeout > jiffies))
176 cpu_relax();
177
178 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
179 LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
180 return -ENODEV;
181 }
182
183 return 0;
184}
185
186static struct clk osc_pll397 = {
187 .parent = &osc_32KHz,
188 .enable = local_pll397_enable,
189 .rate = LPC32XX_CLOCK_OSC_FREQ * 397,
190 .get_rate = local_return_parent_rate,
191};
192
193static struct clk osc_main = {
194 .enable = local_oscmain_enable,
195 .rate = LPC32XX_MAIN_OSC_FREQ,
196 .get_rate = local_return_parent_rate,
197};
198
199static struct clk clk_sys;
200
201/*
202 * Convert a PLL register value to a PLL output frequency
203 */
204u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
205{
206 struct clk_pll_setup pllcfg;
207
208 pllcfg.cco_bypass_b15 = 0;
209 pllcfg.direct_output_b14 = 0;
210 pllcfg.fdbk_div_ctrl_b13 = 0;
211 if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
212 pllcfg.cco_bypass_b15 = 1;
213 if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
214 pllcfg.direct_output_b14 = 1;
215 if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
216 pllcfg.fdbk_div_ctrl_b13 = 1;
217 pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
218 pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
219 pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
220
221 return clk_check_pll_setup(inputclk, &pllcfg);
222}
223
224/*
225 * Setup the HCLK PLL with a PLL structure
226 */
227static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
228{
229 u32 tv, tmp = 0;
230
231 if (PllSetup->analog_on != 0)
232 tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
233 if (PllSetup->cco_bypass_b15 != 0)
234 tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
235 if (PllSetup->direct_output_b14 != 0)
236 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
237 if (PllSetup->fdbk_div_ctrl_b13 != 0)
238 tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
239
240 tv = ffs(PllSetup->pll_p) - 1;
241 if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
242 return 0;
243
244 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
245 tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
246 tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
247
248 return tmp;
249}
250
251/*
252 * Update the ARM core PLL frequency rate variable from the actual PLL setting
253 */
254static void local_update_armpll_rate(void)
255{
256 u32 clkin, pllreg;
257
258 clkin = clk_armpll.parent->rate;
259 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
260
261 clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
262}
263
264/*
265 * Find a PLL configuration for the selected input frequency
266 */
267static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
268 struct clk_pll_setup *pllsetup)
269{
270 u32 ifreq, freqtol, m, n, p, fclkout;
271
272 /* Determine frequency tolerance limits */
273 freqtol = target_freq / 250;
274 ifreq = pllin_freq;
275
276 /* Is direct bypass mode possible? */
277 if (abs(pllin_freq - target_freq) <= freqtol) {
278 pllsetup->analog_on = 0;
279 pllsetup->cco_bypass_b15 = 1;
280 pllsetup->direct_output_b14 = 1;
281 pllsetup->fdbk_div_ctrl_b13 = 1;
282 pllsetup->pll_p = pll_postdivs[0];
283 pllsetup->pll_n = 1;
284 pllsetup->pll_m = 1;
285 return clk_check_pll_setup(ifreq, pllsetup);
286 } else if (target_freq <= ifreq) {
287 pllsetup->analog_on = 0;
288 pllsetup->cco_bypass_b15 = 1;
289 pllsetup->direct_output_b14 = 0;
290 pllsetup->fdbk_div_ctrl_b13 = 1;
291 pllsetup->pll_n = 1;
292 pllsetup->pll_m = 1;
293 for (p = 0; p <= 3; p++) {
294 pllsetup->pll_p = pll_postdivs[p];
295 fclkout = clk_check_pll_setup(ifreq, pllsetup);
296 if (abs(target_freq - fclkout) <= freqtol)
297 return fclkout;
298 }
299 }
300
301 /* Is direct mode possible? */
302 pllsetup->analog_on = 1;
303 pllsetup->cco_bypass_b15 = 0;
304 pllsetup->direct_output_b14 = 1;
305 pllsetup->fdbk_div_ctrl_b13 = 0;
306 pllsetup->pll_p = pll_postdivs[0];
307 for (m = 1; m <= 256; m++) {
308 for (n = 1; n <= 4; n++) {
309 /* Compute output frequency for this value */
310 pllsetup->pll_n = n;
311 pllsetup->pll_m = m;
312 fclkout = clk_check_pll_setup(ifreq,
313 pllsetup);
314 if (abs(target_freq - fclkout) <=
315 freqtol)
316 return fclkout;
317 }
318 }
319
320 /* Is integer mode possible? */
321 pllsetup->analog_on = 1;
322 pllsetup->cco_bypass_b15 = 0;
323 pllsetup->direct_output_b14 = 0;
324 pllsetup->fdbk_div_ctrl_b13 = 1;
325 for (m = 1; m <= 256; m++) {
326 for (n = 1; n <= 4; n++) {
327 for (p = 0; p < 4; p++) {
328 /* Compute output frequency */
329 pllsetup->pll_p = pll_postdivs[p];
330 pllsetup->pll_n = n;
331 pllsetup->pll_m = m;
332 fclkout = clk_check_pll_setup(
333 ifreq, pllsetup);
334 if (abs(target_freq - fclkout) <= freqtol)
335 return fclkout;
336 }
337 }
338 }
339
340 /* Try non-integer mode */
341 pllsetup->analog_on = 1;
342 pllsetup->cco_bypass_b15 = 0;
343 pllsetup->direct_output_b14 = 0;
344 pllsetup->fdbk_div_ctrl_b13 = 0;
345 for (m = 1; m <= 256; m++) {
346 for (n = 1; n <= 4; n++) {
347 for (p = 0; p < 4; p++) {
348 /* Compute output frequency */
349 pllsetup->pll_p = pll_postdivs[p];
350 pllsetup->pll_n = n;
351 pllsetup->pll_m = m;
352 fclkout = clk_check_pll_setup(
353 ifreq, pllsetup);
354 if (abs(target_freq - fclkout) <= freqtol)
355 return fclkout;
356 }
357 }
358 }
359
360 return 0;
361}
362
363static struct clk clk_armpll = {
364 .parent = &clk_sys,
365 .get_rate = local_return_parent_rate,
366};
367
368/*
369 * Setup the USB PLL with a PLL structure
370 */
371static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
372{
373 u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
374
375 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
376 reg |= tmp;
377 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
378
379 return clk_check_pll_setup(clk_usbpll.parent->rate,
380 pHCLKPllSetup);
381}
382
383static int local_usbpll_enable(struct clk *clk, int enable)
384{
385 u32 reg;
386 int ret = -ENODEV;
387 unsigned long timeout = 1 + msecs_to_jiffies(10);
388
389 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
390
391 if (enable == 0) {
392 reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
393 LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
394 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
395 } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
396 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
397 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
398
399 /* Wait for PLL lock */
400 while ((timeout > jiffies) & (ret == -ENODEV)) {
401 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
402 if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
403 ret = 0;
404 }
405
406 if (ret == 0) {
407 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
408 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
409 }
410 }
411
412 return ret;
413}
414
415static unsigned long local_usbpll_round_rate(struct clk *clk,
416 unsigned long rate)
417{
418 u32 clkin, usbdiv;
419 struct clk_pll_setup pllsetup;
420
421 /*
422 * Unlike other clocks, this clock has a KHz input rate, so bump
423 * it up to work with the PLL function
424 */
425 rate = rate * 1000;
426
427 clkin = clk->parent->rate;
428 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
429 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
430 clkin = clkin / usbdiv;
431
432 /* Try to find a good rate setup */
433 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
434 return 0;
435
436 return clk_check_pll_setup(clkin, &pllsetup);
437}
438
439static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
440{
441 u32 clkin, reg, usbdiv;
442 struct clk_pll_setup pllsetup;
443
444 /*
445 * Unlike other clocks, this clock has a KHz input rate, so bump
446 * it up to work with the PLL function
447 */
448 rate = rate * 1000;
449
450 clkin = clk->get_rate(clk);
451 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
452 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
453 clkin = clkin / usbdiv;
454
455 /* Try to find a good rate setup */
456 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
457 return -EINVAL;
458
459 local_usbpll_enable(clk, 0);
460
461 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
462 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
463 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
464
465 pllsetup.analog_on = 1;
466 local_clk_usbpll_setup(&pllsetup);
467
468 clk->rate = clk_check_pll_setup(clkin, &pllsetup);
469
470 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
471 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
472 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
473
474 return 0;
475}
476
477static struct clk clk_usbpll = {
478 .parent = &osc_main,
479 .set_rate = local_usbpll_set_rate,
480 .enable = local_usbpll_enable,
481 .rate = 48000, /* In KHz */
482 .get_rate = local_return_parent_rate,
483 .round_rate = local_usbpll_round_rate,
484};
485
486static u32 clk_get_hclk_div(void)
487{
488 static const u32 hclkdivs[4] = {1, 2, 4, 4};
489 return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
490 __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
491}
492
493static struct clk clk_hclk = {
494 .parent = &clk_armpll,
495 .get_rate = local_return_parent_rate,
496};
497
498static struct clk clk_pclk = {
499 .parent = &clk_armpll,
500 .get_rate = local_return_parent_rate,
501};
502
503static int local_onoff_enable(struct clk *clk, int enable)
504{
505 u32 tmp;
506
507 tmp = __raw_readl(clk->enable_reg);
508
509 if (enable == 0)
510 tmp &= ~clk->enable_mask;
511 else
512 tmp |= clk->enable_mask;
513
514 __raw_writel(tmp, clk->enable_reg);
515
516 return 0;
517}
518
519/* Peripheral clock sources */
520static struct clk clk_timer0 = {
521 .parent = &clk_pclk,
522 .enable = local_onoff_enable,
523 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
524 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
525 .get_rate = local_return_parent_rate,
526};
527static struct clk clk_timer1 = {
528 .parent = &clk_pclk,
529 .enable = local_onoff_enable,
530 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
531 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
532 .get_rate = local_return_parent_rate,
533};
534static struct clk clk_timer2 = {
535 .parent = &clk_pclk,
536 .enable = local_onoff_enable,
537 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
538 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
539 .get_rate = local_return_parent_rate,
540};
541static struct clk clk_timer3 = {
542 .parent = &clk_pclk,
543 .enable = local_onoff_enable,
544 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
545 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
546 .get_rate = local_return_parent_rate,
547};
548static struct clk clk_wdt = {
549 .parent = &clk_pclk,
550 .enable = local_onoff_enable,
551 .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
552 .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
553 .get_rate = local_return_parent_rate,
554};
555static struct clk clk_vfp9 = {
556 .parent = &clk_pclk,
557 .enable = local_onoff_enable,
558 .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
559 .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
560 .get_rate = local_return_parent_rate,
561};
562static struct clk clk_dma = {
563 .parent = &clk_hclk,
564 .enable = local_onoff_enable,
565 .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
566 .enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
567 .get_rate = local_return_parent_rate,
568};
569
570static struct clk clk_uart3 = {
571 .parent = &clk_pclk,
572 .enable = local_onoff_enable,
573 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
574 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
575 .get_rate = local_return_parent_rate,
576};
577
578static struct clk clk_uart4 = {
579 .parent = &clk_pclk,
580 .enable = local_onoff_enable,
581 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
582 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
583 .get_rate = local_return_parent_rate,
584};
585
586static struct clk clk_uart5 = {
587 .parent = &clk_pclk,
588 .enable = local_onoff_enable,
589 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
590 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
591 .get_rate = local_return_parent_rate,
592};
593
594static struct clk clk_uart6 = {
595 .parent = &clk_pclk,
596 .enable = local_onoff_enable,
597 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
598 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
599 .get_rate = local_return_parent_rate,
600};
601
602static struct clk clk_i2c0 = {
603 .parent = &clk_hclk,
604 .enable = local_onoff_enable,
605 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
606 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
607 .get_rate = local_return_parent_rate,
608};
609
610static struct clk clk_i2c1 = {
611 .parent = &clk_hclk,
612 .enable = local_onoff_enable,
613 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
614 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
615 .get_rate = local_return_parent_rate,
616};
617
618static struct clk clk_i2c2 = {
619 .parent = &clk_pclk,
620 .enable = local_onoff_enable,
621 .enable_reg = io_p2v(LPC32XX_USB_BASE + 0xFF4),
622 .enable_mask = 0x4,
623 .get_rate = local_return_parent_rate,
624};
625
626static struct clk clk_ssp0 = {
627 .parent = &clk_hclk,
628 .enable = local_onoff_enable,
629 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
630 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
631 .get_rate = local_return_parent_rate,
632};
633
634static struct clk clk_ssp1 = {
635 .parent = &clk_hclk,
636 .enable = local_onoff_enable,
637 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
638 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
639 .get_rate = local_return_parent_rate,
640};
641
642static struct clk clk_kscan = {
643 .parent = &osc_32KHz,
644 .enable = local_onoff_enable,
645 .enable_reg = LPC32XX_CLKPWR_KEY_CLK_CTRL,
646 .enable_mask = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
647 .get_rate = local_return_parent_rate,
648};
649
650static struct clk clk_nand = {
651 .parent = &clk_hclk,
652 .enable = local_onoff_enable,
653 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
654 .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
655 .get_rate = local_return_parent_rate,
656};
657
658static struct clk clk_i2s0 = {
659 .parent = &clk_hclk,
660 .enable = local_onoff_enable,
661 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
662 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
663 .get_rate = local_return_parent_rate,
664};
665
666static struct clk clk_i2s1 = {
667 .parent = &clk_hclk,
668 .enable = local_onoff_enable,
669 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
670 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
671 .get_rate = local_return_parent_rate,
672};
673
674static struct clk clk_net = {
675 .parent = &clk_hclk,
676 .enable = local_onoff_enable,
677 .enable_reg = LPC32XX_CLKPWR_MACCLK_CTRL,
678 .enable_mask = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
679 LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
680 LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
681 .get_rate = local_return_parent_rate,
682};
683
684static struct clk clk_rtc = {
685 .parent = &osc_32KHz,
686 .rate = 1, /* 1 Hz */
687 .get_rate = local_return_parent_rate,
688};
689
690static struct clk clk_usbd = {
691 .parent = &clk_usbpll,
692 .enable = local_onoff_enable,
693 .enable_reg = LPC32XX_CLKPWR_USB_CTRL,
694 .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
695 .get_rate = local_return_parent_rate,
696};
697
698static int tsc_onoff_enable(struct clk *clk, int enable)
699{
700 u32 tmp;
701
702 /* Make sure 32KHz clock is the selected clock */
703 tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
704 tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
705 __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
706
707 if (enable == 0)
708 __raw_writel(0, clk->enable_reg);
709 else
710 __raw_writel(clk->enable_mask, clk->enable_reg);
711
712 return 0;
713}
714
715static struct clk clk_tsc = {
716 .parent = &osc_32KHz,
717 .enable = tsc_onoff_enable,
718 .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
719 .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
720 .get_rate = local_return_parent_rate,
721};
722
723static int mmc_onoff_enable(struct clk *clk, int enable)
724{
725 u32 tmp;
726
727 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
728 ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
729
730 /* If rate is 0, disable clock */
731 if (enable != 0)
732 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
733
734 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
735
736 return 0;
737}
738
739static unsigned long mmc_get_rate(struct clk *clk)
740{
741 u32 div, rate, oldclk;
742
743 /* The MMC clock must be on when accessing an MMC register */
744 oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
745 __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
746 LPC32XX_CLKPWR_MS_CTRL);
747 div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
748 __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
749
750 /* Get the parent clock rate */
751 rate = clk->parent->get_rate(clk->parent);
752
753 /* Get the MMC controller clock divider value */
754 div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
755
756 if (!div)
757 div = 1;
758
759 return rate / div;
760}
761
762static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
763{
764 unsigned long div, prate;
765
766 /* Get the parent clock rate */
767 prate = clk->parent->get_rate(clk->parent);
768
769 if (rate >= prate)
770 return prate;
771
772 div = prate / rate;
773 if (div > 0xf)
774 div = 0xf;
775
776 return prate / div;
777}
778
779static int mmc_set_rate(struct clk *clk, unsigned long rate)
780{
781 u32 oldclk, tmp;
782 unsigned long prate, div, crate = mmc_round_rate(clk, rate);
783
784 prate = clk->parent->get_rate(clk->parent);
785
786 div = prate / crate;
787
788 /* The MMC clock must be on when accessing an MMC register */
789 oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
790 __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
791 LPC32XX_CLKPWR_MS_CTRL);
792 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
793 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
794 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
795 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
796
797 __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
798
799 return 0;
800}
801
802static struct clk clk_mmc = {
803 .parent = &clk_armpll,
804 .set_rate = mmc_set_rate,
805 .get_rate = mmc_get_rate,
806 .round_rate = mmc_round_rate,
807 .enable = mmc_onoff_enable,
808 .enable_reg = LPC32XX_CLKPWR_MS_CTRL,
809 .enable_mask = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
810};
811
812static unsigned long clcd_get_rate(struct clk *clk)
813{
814 u32 tmp, div, rate, oldclk;
815
816 /* The LCD clock must be on when accessing an LCD register */
817 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
818 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
819 LPC32XX_CLKPWR_LCDCLK_CTRL);
820 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
821 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
822
823 rate = clk->parent->get_rate(clk->parent);
824
825 /* Only supports internal clocking */
826 if (tmp & TIM2_BCD)
827 return rate;
828
829 div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
830 tmp = rate / (2 + div);
831
832 return tmp;
833}
834
835static int clcd_set_rate(struct clk *clk, unsigned long rate)
836{
837 u32 tmp, prate, div, oldclk;
838
839 /* The LCD clock must be on when accessing an LCD register */
840 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
841 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
842 LPC32XX_CLKPWR_LCDCLK_CTRL);
843
844 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
845 prate = clk->parent->get_rate(clk->parent);
846
847 if (rate < prate) {
848 /* Find closest divider */
849 div = prate / rate;
850 if (div >= 2) {
851 div -= 2;
852 tmp &= ~TIM2_BCD;
853 }
854
855 tmp &= ~(0xF800001F);
856 tmp |= (div & 0x1F);
857 tmp |= (((div >> 5) & 0x1F) << 27);
858 }
859
860 __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
861 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
862
863 return 0;
864}
865
866static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
867{
868 u32 prate, div;
869
870 prate = clk->parent->get_rate(clk->parent);
871
872 if (rate >= prate)
873 rate = prate;
874 else {
875 div = prate / rate;
876 if (div > 0x3ff)
877 div = 0x3ff;
878
879 rate = prate / div;
880 }
881
882 return rate;
883}
884
885static struct clk clk_lcd = {
886 .parent = &clk_hclk,
887 .set_rate = clcd_set_rate,
888 .get_rate = clcd_get_rate,
889 .round_rate = clcd_round_rate,
890 .enable = local_onoff_enable,
891 .enable_reg = LPC32XX_CLKPWR_LCDCLK_CTRL,
892 .enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
893};
894
895static inline void clk_lock(void)
896{
897 mutex_lock(&clkm_lock);
898}
899
900static inline void clk_unlock(void)
901{
902 mutex_unlock(&clkm_lock);
903}
904
905static void local_clk_disable(struct clk *clk)
906{
907 WARN_ON(clk->usecount == 0);
908
909 /* Don't attempt to disable clock if it has no users */
910 if (clk->usecount > 0) {
911 clk->usecount--;
912
913 /* Only disable clock when it has no more users */
914 if ((clk->usecount == 0) && (clk->enable))
915 clk->enable(clk, 0);
916
917 /* Check parent clocks, they may need to be disabled too */
918 if (clk->parent)
919 local_clk_disable(clk->parent);
920 }
921}
922
923static int local_clk_enable(struct clk *clk)
924{
925 int ret = 0;
926
927 /* Enable parent clocks first and update use counts */
928 if (clk->parent)
929 ret = local_clk_enable(clk->parent);
930
931 if (!ret) {
932 /* Only enable clock if it's currently disabled */
933 if ((clk->usecount == 0) && (clk->enable))
934 ret = clk->enable(clk, 1);
935
936 if (!ret)
937 clk->usecount++;
938 else if (clk->parent)
939 local_clk_disable(clk->parent);
940 }
941
942 return ret;
943}
944
945/*
946 * clk_enable - inform the system when the clock source should be running.
947 */
948int clk_enable(struct clk *clk)
949{
950 int ret;
951
952 clk_lock();
953 ret = local_clk_enable(clk);
954 clk_unlock();
955
956 return ret;
957}
958EXPORT_SYMBOL(clk_enable);
959
960/*
961 * clk_disable - inform the system when the clock source is no longer required
962 */
963void clk_disable(struct clk *clk)
964{
965 clk_lock();
966 local_clk_disable(clk);
967 clk_unlock();
968}
969EXPORT_SYMBOL(clk_disable);
970
971/*
972 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
973 */
974unsigned long clk_get_rate(struct clk *clk)
975{
976 unsigned long rate;
977
978 clk_lock();
979 rate = clk->get_rate(clk);
980 clk_unlock();
981
982 return rate;
983}
984EXPORT_SYMBOL(clk_get_rate);
985
986/*
987 * clk_set_rate - set the clock rate for a clock source
988 */
989int clk_set_rate(struct clk *clk, unsigned long rate)
990{
991 int ret = -EINVAL;
992
993 /*
994 * Most system clocks can only be enabled or disabled, with
995 * the actual rate set as part of the peripheral dividers
996 * instead of high level clock control
997 */
998 if (clk->set_rate) {
999 clk_lock();
1000 ret = clk->set_rate(clk, rate);
1001 clk_unlock();
1002 }
1003
1004 return ret;
1005}
1006EXPORT_SYMBOL(clk_set_rate);
1007
1008/*
1009 * clk_round_rate - adjust a rate to the exact rate a clock can provide
1010 */
1011long clk_round_rate(struct clk *clk, unsigned long rate)
1012{
1013 clk_lock();
1014
1015 if (clk->round_rate)
1016 rate = clk->round_rate(clk, rate);
1017 else
1018 rate = clk->get_rate(clk);
1019
1020 clk_unlock();
1021
1022 return rate;
1023}
1024EXPORT_SYMBOL(clk_round_rate);
1025
1026/*
1027 * clk_set_parent - set the parent clock source for this clock
1028 */
1029int clk_set_parent(struct clk *clk, struct clk *parent)
1030{
1031 /* Clock re-parenting is not supported */
1032 return -EINVAL;
1033}
1034EXPORT_SYMBOL(clk_set_parent);
1035
1036/*
1037 * clk_get_parent - get the parent clock source for this clock
1038 */
1039struct clk *clk_get_parent(struct clk *clk)
1040{
1041 return clk->parent;
1042}
1043EXPORT_SYMBOL(clk_get_parent);
1044
1045#define _REGISTER_CLOCK(d, n, c) \
1046 { \
1047 .dev_id = (d), \
1048 .con_id = (n), \
1049 .clk = &(c), \
1050 },
1051
1052static struct clk_lookup lookups[] = {
1053 _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
1054 _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
1055 _REGISTER_CLOCK(NULL, "osc_main", osc_main)
1056 _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
1057 _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
1058 _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
1059 _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
1060 _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
1061 _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
1062 _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
1063 _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
1064 _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
1065 _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
1066 _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
1067 _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
1068 _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
1069 _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
1070 _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
1071 _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
1072 _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
1073 _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
1074 _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
1075 _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
1076 _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
1077 _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
1078 _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
1079 _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
1080 _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
1081 _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
1082 _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
1083 _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
1084 _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
1085 _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
1086 _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
1087};
1088
1089static int __init clk_init(void)
1090{
1091 int i;
1092
1093 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1094 clkdev_add(&lookups[i]);
1095
1096 /*
1097 * Setup muxed SYSCLK for HCLK PLL base -this selects the
1098 * parent clock used for the ARM PLL and is used to derive
1099 * the many system clock rates in the device.
1100 */
1101 if (clk_is_sysclk_mainosc() != 0)
1102 clk_sys.parent = &osc_main;
1103 else
1104 clk_sys.parent = &osc_pll397;
1105
1106 clk_sys.rate = clk_sys.parent->rate;
1107
1108 /* Compute the current ARM PLL and USB PLL frequencies */
1109 local_update_armpll_rate();
1110
1111 /* Compute HCLK and PCLK bus rates */
1112 clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
1113 clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
1114
1115 /*
1116 * Enable system clocks - this step is somewhat formal, as the
1117 * clocks are already running, but it does get the clock data
1118 * inline with the actual system state. Never disable these
1119 * clocks as they will only stop if the system is going to sleep.
1120 * In that case, the chip/system power management functions will
1121 * handle clock gating.
1122 */
1123 if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
1124 printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
1125
1126 /*
1127 * Timers 0 and 1 were enabled and are being used by the high
1128 * resolution tick function prior to this driver being initialized.
1129 * Tag them now as used.
1130 */
1131 if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
1132 printk(KERN_ERR "Error enabling timer tick clocks\n");
1133
1134 return 0;
1135}
1136core_initcall(clk_init);
1137
diff --git a/arch/arm/mach-lpc32xx/clock.h b/arch/arm/mach-lpc32xx/clock.h
new file mode 100644
index 000000000000..c0a8434307f7
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/clock.h
@@ -0,0 +1,38 @@
1/*
2 * arch/arm/mach-lpc32xx/clock.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __LPC32XX_CLOCK_H
20#define __LPC32XX_CLOCK_H
21
22struct clk {
23 struct list_head node;
24 struct clk *parent;
25 u32 rate;
26 u32 usecount;
27
28 int (*set_rate) (struct clk *, unsigned long);
29 unsigned long (*round_rate) (struct clk *, unsigned long);
30 unsigned long (*get_rate) (struct clk *clk);
31 int (*enable) (struct clk *, int);
32
33 /* Register address and bit mask for simple clocks */
34 void __iomem *enable_reg;
35 u32 enable_mask;
36};
37
38#endif
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
new file mode 100644
index 000000000000..ee24dc28e93e
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -0,0 +1,271 @@
1/*
2 * arch/arm/mach-lpc32xx/common.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/err.h>
24#include <linux/i2c.h>
25#include <linux/i2c-pnx.h>
26#include <linux/io.h>
27
28#include <asm/mach/map.h>
29
30#include <mach/i2c.h>
31#include <mach/hardware.h>
32#include <mach/platform.h>
33#include "common.h"
34
35/*
36 * Watchdog timer
37 */
38static struct resource watchdog_resources[] = {
39 [0] = {
40 .start = LPC32XX_WDTIM_BASE,
41 .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
42 .flags = IORESOURCE_MEM,
43 },
44};
45
46struct platform_device lpc32xx_watchdog_device = {
47 .name = "pnx4008-watchdog",
48 .id = -1,
49 .num_resources = ARRAY_SIZE(watchdog_resources),
50 .resource = watchdog_resources,
51};
52
53/*
54 * I2C busses
55 */
56static struct i2c_pnx_data i2c0_data = {
57 .name = I2C_CHIP_NAME "1",
58 .base = LPC32XX_I2C1_BASE,
59 .irq = IRQ_LPC32XX_I2C_1,
60};
61
62static struct i2c_pnx_data i2c1_data = {
63 .name = I2C_CHIP_NAME "2",
64 .base = LPC32XX_I2C2_BASE,
65 .irq = IRQ_LPC32XX_I2C_2,
66};
67
68static struct i2c_pnx_data i2c2_data = {
69 .name = "USB-I2C",
70 .base = LPC32XX_OTG_I2C_BASE,
71 .irq = IRQ_LPC32XX_USB_I2C,
72};
73
74struct platform_device lpc32xx_i2c0_device = {
75 .name = "pnx-i2c",
76 .id = 0,
77 .dev = {
78 .platform_data = &i2c0_data,
79 },
80};
81
82struct platform_device lpc32xx_i2c1_device = {
83 .name = "pnx-i2c",
84 .id = 1,
85 .dev = {
86 .platform_data = &i2c1_data,
87 },
88};
89
90struct platform_device lpc32xx_i2c2_device = {
91 .name = "pnx-i2c",
92 .id = 2,
93 .dev = {
94 .platform_data = &i2c2_data,
95 },
96};
97
98/*
99 * Returns the unique ID for the device
100 */
101void lpc32xx_get_uid(u32 devid[4])
102{
103 int i;
104
105 for (i = 0; i < 4; i++)
106 devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
107}
108
109/*
110 * Returns SYSCLK source
111 * 0 = PLL397, 1 = main oscillator
112 */
113int clk_is_sysclk_mainosc(void)
114{
115 if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
116 LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
117 return 1;
118
119 return 0;
120}
121
122/*
123 * System reset via the watchdog timer
124 */
125void lpc32xx_watchdog_reset(void)
126{
127 /* Make sure WDT clocks are enabled */
128 __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
129 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
130
131 /* Instant assert of RESETOUT_N with pulse length 1mS */
132 __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
133 __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
134}
135
136/*
137 * Detects and returns IRAM size for the device variation
138 */
139#define LPC32XX_IRAM_BANK_SIZE SZ_128K
140static u32 iram_size;
141u32 lpc32xx_return_iram_size(void)
142{
143 if (iram_size == 0) {
144 u32 savedval1, savedval2;
145 void __iomem *iramptr1, *iramptr2;
146
147 iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
148 iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
149 savedval1 = __raw_readl(iramptr1);
150 savedval2 = __raw_readl(iramptr2);
151
152 if (savedval1 == savedval2) {
153 __raw_writel(savedval2 + 1, iramptr2);
154 if (__raw_readl(iramptr1) == savedval2 + 1)
155 iram_size = LPC32XX_IRAM_BANK_SIZE;
156 else
157 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
158 __raw_writel(savedval2, iramptr2);
159 } else
160 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
161 }
162
163 return iram_size;
164}
165
166/*
167 * Computes PLL rate from PLL register and input clock
168 */
169u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
170{
171 u32 ilfreq, p, m, n, fcco, fref, cfreq;
172 int mode;
173
174 /*
175 * PLL requirements
176 * ifreq must be >= 1MHz and <= 20MHz
177 * FCCO must be >= 156MHz and <= 320MHz
178 * FREF must be >= 1MHz and <= 27MHz
179 * Assume the passed input data is not valid
180 */
181
182 ilfreq = ifreq;
183 m = pllsetup->pll_m;
184 n = pllsetup->pll_n;
185 p = pllsetup->pll_p;
186
187 mode = (pllsetup->cco_bypass_b15 << 2) |
188 (pllsetup->direct_output_b14 << 1) |
189 pllsetup->fdbk_div_ctrl_b13;
190
191 switch (mode) {
192 case 0x0: /* Non-integer mode */
193 cfreq = (m * ilfreq) / (2 * p * n);
194 fcco = (m * ilfreq) / n;
195 fref = ilfreq / n;
196 break;
197
198 case 0x1: /* integer mode */
199 cfreq = (m * ilfreq) / n;
200 fcco = (m * ilfreq) / (n * 2 * p);
201 fref = ilfreq / n;
202 break;
203
204 case 0x2:
205 case 0x3: /* Direct mode */
206 cfreq = (m * ilfreq) / n;
207 fcco = cfreq;
208 fref = ilfreq / n;
209 break;
210
211 case 0x4:
212 case 0x5: /* Bypass mode */
213 cfreq = ilfreq / (2 * p);
214 fcco = 156000000;
215 fref = 1000000;
216 break;
217
218 case 0x6:
219 case 0x7: /* Direct bypass mode */
220 default:
221 cfreq = ilfreq;
222 fcco = 156000000;
223 fref = 1000000;
224 break;
225 }
226
227 if (fcco < 156000000 || fcco > 320000000)
228 cfreq = 0;
229
230 if (fref < 1000000 || fref > 27000000)
231 cfreq = 0;
232
233 return (u32) cfreq;
234}
235
236u32 clk_get_pclk_div(void)
237{
238 return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
239}
240
241static struct map_desc lpc32xx_io_desc[] __initdata = {
242 {
243 .virtual = IO_ADDRESS(LPC32XX_AHB0_START),
244 .pfn = __phys_to_pfn(LPC32XX_AHB0_START),
245 .length = LPC32XX_AHB0_SIZE,
246 .type = MT_DEVICE
247 },
248 {
249 .virtual = IO_ADDRESS(LPC32XX_AHB1_START),
250 .pfn = __phys_to_pfn(LPC32XX_AHB1_START),
251 .length = LPC32XX_AHB1_SIZE,
252 .type = MT_DEVICE
253 },
254 {
255 .virtual = IO_ADDRESS(LPC32XX_FABAPB_START),
256 .pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
257 .length = LPC32XX_FABAPB_SIZE,
258 .type = MT_DEVICE
259 },
260 {
261 .virtual = IO_ADDRESS(LPC32XX_IRAM_BASE),
262 .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
263 .length = (LPC32XX_IRAM_BANK_SIZE * 2),
264 .type = MT_DEVICE
265 },
266};
267
268void __init lpc32xx_map_io(void)
269{
270 iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
271}
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
new file mode 100644
index 000000000000..f82211fd80c1
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -0,0 +1,73 @@
1/*
2 * arch/arm/mach-lpc32xx/common.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2009-2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __LPC32XX_COMMON_H
20#define __LPC32XX_COMMON_H
21
22#include <linux/platform_device.h>
23
24/*
25 * Arch specific platform device structures
26 */
27extern struct platform_device lpc32xx_watchdog_device;
28extern struct platform_device lpc32xx_i2c0_device;
29extern struct platform_device lpc32xx_i2c1_device;
30extern struct platform_device lpc32xx_i2c2_device;
31
32/*
33 * Other arch specific structures and functions
34 */
35extern struct sys_timer lpc32xx_timer;
36extern void __init lpc32xx_init_irq(void);
37extern void __init lpc32xx_map_io(void);
38extern void __init lpc32xx_serial_init(void);
39extern void __init lpc32xx_gpio_init(void);
40
41/*
42 * Structure used for setting up and querying the PLLS
43 */
44struct clk_pll_setup {
45 int analog_on;
46 int cco_bypass_b15;
47 int direct_output_b14;
48 int fdbk_div_ctrl_b13;
49 int pll_p;
50 int pll_n;
51 u32 pll_m;
52};
53
54extern int clk_is_sysclk_mainosc(void);
55extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup);
56extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
57extern u32 clk_get_pclk_div(void);
58
59/*
60 * Returns the LPC32xx unique 128-bit chip ID
61 */
62extern void lpc32xx_get_uid(u32 devid[4]);
63
64extern void lpc32xx_watchdog_reset(void);
65extern u32 lpc32xx_return_iram_size(void);
66
67/*
68 * Pointers used for sizing and copying suspend function data
69 */
70extern int lpc32xx_sys_suspend(void);
71extern int lpc32xx_sys_suspend_sz;
72
73#endif
diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c
new file mode 100644
index 000000000000..69061ea8997a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/gpiolib.c
@@ -0,0 +1,446 @@
1/*
2 * arch/arm/mach-lpc32xx/gpiolib.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/errno.h>
23#include <linux/gpio.h>
24
25#include <mach/hardware.h>
26#include <mach/platform.h>
27#include "common.h"
28
29#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
30#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
31#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
32#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
33#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
34#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
35#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
36#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
37#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
38#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
39#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
40#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
41#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
42#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
43#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
44#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
45#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
46#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
47#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
48#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
49#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
50#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
51#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
52#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
53#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
54#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
55#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
56
57#define GPIO012_PIN_TO_BIT(x) (1 << (x))
58#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
59#define GPO3_PIN_TO_BIT(x) (1 << (x))
60#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
61#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
62#define GPIO3_PIN_IN_SEL(x, y) ((x) >> GPIO3_PIN_IN_SHIFT(y))
63#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
64#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
65
66struct gpio_regs {
67 void __iomem *inp_state;
68 void __iomem *outp_set;
69 void __iomem *outp_clr;
70 void __iomem *dir_set;
71 void __iomem *dir_clr;
72};
73
74/*
75 * GPIO names
76 */
77static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
78 "p0.0", "p0.1", "p0.2", "p0.3",
79 "p0.4", "p0.5", "p0.6", "p0.7"
80};
81
82static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
83 "p1.0", "p1.1", "p1.2", "p1.3",
84 "p1.4", "p1.5", "p1.6", "p1.7",
85 "p1.8", "p1.9", "p1.10", "p1.11",
86 "p1.12", "p1.13", "p1.14", "p1.15",
87 "p1.16", "p1.17", "p1.18", "p1.19",
88 "p1.20", "p1.21", "p1.22", "p1.23",
89};
90
91static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
92 "p2.0", "p2.1", "p2.2", "p2.3",
93 "p2.4", "p2.5", "p2.6", "p2.7",
94 "p2.8", "p2.9", "p2.10", "p2.11",
95 "p2.12"
96};
97
98static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
99 "gpi000", "gpio01", "gpio02", "gpio03",
100 "gpio04", "gpio05"
101};
102
103static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
104 "gpi00", "gpi01", "gpi02", "gpi03",
105 "gpi04", "gpi05", "gpi06", "gpi07",
106 "gpi08", "gpi09", NULL, NULL,
107 NULL, NULL, NULL, "gpi15",
108 "gpi16", "gpi17", "gpi18", "gpi19",
109 "gpi20", "gpi21", "gpi22", "gpi23",
110 "gpi24", "gpi25", "gpi26", "gpi27"
111};
112
113static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
114 "gpo00", "gpo01", "gpo02", "gpo03",
115 "gpo04", "gpo05", "gpo06", "gpo07",
116 "gpo08", "gpo09", "gpo10", "gpo11",
117 "gpo12", "gpo13", "gpo14", "gpo15",
118 "gpo16", "gpo17", "gpo18", "gpo19",
119 "gpo20", "gpo21", "gpo22", "gpo23"
120};
121
122static struct gpio_regs gpio_grp_regs_p0 = {
123 .inp_state = LPC32XX_GPIO_P0_INP_STATE,
124 .outp_set = LPC32XX_GPIO_P0_OUTP_SET,
125 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
126 .dir_set = LPC32XX_GPIO_P0_DIR_SET,
127 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
128};
129
130static struct gpio_regs gpio_grp_regs_p1 = {
131 .inp_state = LPC32XX_GPIO_P1_INP_STATE,
132 .outp_set = LPC32XX_GPIO_P1_OUTP_SET,
133 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
134 .dir_set = LPC32XX_GPIO_P1_DIR_SET,
135 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
136};
137
138static struct gpio_regs gpio_grp_regs_p2 = {
139 .inp_state = LPC32XX_GPIO_P2_INP_STATE,
140 .outp_set = LPC32XX_GPIO_P2_OUTP_SET,
141 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
142 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
143 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
144};
145
146static struct gpio_regs gpio_grp_regs_p3 = {
147 .inp_state = LPC32XX_GPIO_P3_INP_STATE,
148 .outp_set = LPC32XX_GPIO_P3_OUTP_SET,
149 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
150 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
151 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
152};
153
154struct lpc32xx_gpio_chip {
155 struct gpio_chip chip;
156 struct gpio_regs *gpio_grp;
157};
158
159static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
160 struct gpio_chip *gpc)
161{
162 return container_of(gpc, struct lpc32xx_gpio_chip, chip);
163}
164
165static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
166 unsigned pin, int input)
167{
168 if (input)
169 __raw_writel(GPIO012_PIN_TO_BIT(pin),
170 group->gpio_grp->dir_clr);
171 else
172 __raw_writel(GPIO012_PIN_TO_BIT(pin),
173 group->gpio_grp->dir_set);
174}
175
176static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
177 unsigned pin, int input)
178{
179 u32 u = GPIO3_PIN_TO_BIT(pin);
180
181 if (input)
182 __raw_writel(u, group->gpio_grp->dir_clr);
183 else
184 __raw_writel(u, group->gpio_grp->dir_set);
185}
186
187static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
188 unsigned pin, int high)
189{
190 if (high)
191 __raw_writel(GPIO012_PIN_TO_BIT(pin),
192 group->gpio_grp->outp_set);
193 else
194 __raw_writel(GPIO012_PIN_TO_BIT(pin),
195 group->gpio_grp->outp_clr);
196}
197
198static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
199 unsigned pin, int high)
200{
201 u32 u = GPIO3_PIN_TO_BIT(pin);
202
203 if (high)
204 __raw_writel(u, group->gpio_grp->outp_set);
205 else
206 __raw_writel(u, group->gpio_grp->outp_clr);
207}
208
209static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
210 unsigned pin, int high)
211{
212 if (high)
213 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
214 else
215 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
216}
217
218static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
219 unsigned pin)
220{
221 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
222 pin);
223}
224
225static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
226 unsigned pin)
227{
228 int state = __raw_readl(group->gpio_grp->inp_state);
229
230 /*
231 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
232 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
233 */
234 return GPIO3_PIN_IN_SEL(state, pin);
235}
236
237static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
238 unsigned pin)
239{
240 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
241}
242
243/*
244 * GENERIC_GPIO primitives.
245 */
246static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
247 unsigned pin)
248{
249 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
250
251 __set_gpio_dir_p012(group, pin, 1);
252
253 return 0;
254}
255
256static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
257 unsigned pin)
258{
259 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
260
261 __set_gpio_dir_p3(group, pin, 1);
262
263 return 0;
264}
265
266static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
267 unsigned pin)
268{
269 return 0;
270}
271
272static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
273{
274 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
275
276 return __get_gpio_state_p012(group, pin);
277}
278
279static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
280{
281 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
282
283 return __get_gpio_state_p3(group, pin);
284}
285
286static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
287{
288 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
289
290 return __get_gpi_state_p3(group, pin);
291}
292
293static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
294 int value)
295{
296 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
297
298 __set_gpio_dir_p012(group, pin, 0);
299
300 return 0;
301}
302
303static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
304 int value)
305{
306 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
307
308 __set_gpio_dir_p3(group, pin, 0);
309
310 return 0;
311}
312
313static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
314 int value)
315{
316 return 0;
317}
318
319static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
320 int value)
321{
322 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
323
324 __set_gpio_level_p012(group, pin, value);
325}
326
327static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
328 int value)
329{
330 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
331
332 __set_gpio_level_p3(group, pin, value);
333}
334
335static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
336 int value)
337{
338 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
339
340 __set_gpo_level_p3(group, pin, value);
341}
342
343static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
344{
345 if (pin < chip->ngpio)
346 return 0;
347
348 return -EINVAL;
349}
350
351static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
352 {
353 .chip = {
354 .label = "gpio_p0",
355 .direction_input = lpc32xx_gpio_dir_input_p012,
356 .get = lpc32xx_gpio_get_value_p012,
357 .direction_output = lpc32xx_gpio_dir_output_p012,
358 .set = lpc32xx_gpio_set_value_p012,
359 .request = lpc32xx_gpio_request,
360 .base = LPC32XX_GPIO_P0_GRP,
361 .ngpio = LPC32XX_GPIO_P0_MAX,
362 .names = gpio_p0_names,
363 .can_sleep = 0,
364 },
365 .gpio_grp = &gpio_grp_regs_p0,
366 },
367 {
368 .chip = {
369 .label = "gpio_p1",
370 .direction_input = lpc32xx_gpio_dir_input_p012,
371 .get = lpc32xx_gpio_get_value_p012,
372 .direction_output = lpc32xx_gpio_dir_output_p012,
373 .set = lpc32xx_gpio_set_value_p012,
374 .request = lpc32xx_gpio_request,
375 .base = LPC32XX_GPIO_P1_GRP,
376 .ngpio = LPC32XX_GPIO_P1_MAX,
377 .names = gpio_p1_names,
378 .can_sleep = 0,
379 },
380 .gpio_grp = &gpio_grp_regs_p1,
381 },
382 {
383 .chip = {
384 .label = "gpio_p2",
385 .direction_input = lpc32xx_gpio_dir_input_p012,
386 .get = lpc32xx_gpio_get_value_p012,
387 .direction_output = lpc32xx_gpio_dir_output_p012,
388 .set = lpc32xx_gpio_set_value_p012,
389 .request = lpc32xx_gpio_request,
390 .base = LPC32XX_GPIO_P2_GRP,
391 .ngpio = LPC32XX_GPIO_P2_MAX,
392 .names = gpio_p2_names,
393 .can_sleep = 0,
394 },
395 .gpio_grp = &gpio_grp_regs_p2,
396 },
397 {
398 .chip = {
399 .label = "gpio_p3",
400 .direction_input = lpc32xx_gpio_dir_input_p3,
401 .get = lpc32xx_gpio_get_value_p3,
402 .direction_output = lpc32xx_gpio_dir_output_p3,
403 .set = lpc32xx_gpio_set_value_p3,
404 .request = lpc32xx_gpio_request,
405 .base = LPC32XX_GPIO_P3_GRP,
406 .ngpio = LPC32XX_GPIO_P3_MAX,
407 .names = gpio_p3_names,
408 .can_sleep = 0,
409 },
410 .gpio_grp = &gpio_grp_regs_p3,
411 },
412 {
413 .chip = {
414 .label = "gpi_p3",
415 .direction_input = lpc32xx_gpio_dir_in_always,
416 .get = lpc32xx_gpi_get_value,
417 .request = lpc32xx_gpio_request,
418 .base = LPC32XX_GPI_P3_GRP,
419 .ngpio = LPC32XX_GPI_P3_MAX,
420 .names = gpi_p3_names,
421 .can_sleep = 0,
422 },
423 .gpio_grp = &gpio_grp_regs_p3,
424 },
425 {
426 .chip = {
427 .label = "gpo_p3",
428 .direction_output = lpc32xx_gpio_dir_out_always,
429 .set = lpc32xx_gpo_set_value,
430 .request = lpc32xx_gpio_request,
431 .base = LPC32XX_GPO_P3_GRP,
432 .ngpio = LPC32XX_GPO_P3_MAX,
433 .names = gpo_p3_names,
434 .can_sleep = 0,
435 },
436 .gpio_grp = &gpio_grp_regs_p3,
437 },
438};
439
440void __init lpc32xx_gpio_init(void)
441{
442 int i;
443
444 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++)
445 gpiochip_add(&lpc32xx_gpiochip[i].chip);
446}
diff --git a/arch/arm/mach-lpc32xx/include/mach/clkdev.h b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
new file mode 100644
index 000000000000..9bf0637e29ce
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
@@ -0,0 +1,25 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/clkdev.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_CLKDEV_H
20#define __ASM_ARCH_CLKDEV_H
21
22#define __clk_get(clk) ({ 1; })
23#define __clk_put(clk) do { } while (0)
24
25#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..621744d6b152
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -0,0 +1,31 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/debug-macro.S
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19/*
20 * Debug output is hardcoded to standard UART 5
21*/
22
23 .macro addruart,rx, tmp
24 mrc p15, 0, \rx, c1, c0
25 tst \rx, #1 @ MMU enabled?
26 ldreq \rx, =0x40090000
27 ldrne \rx, =0xF4090000
28 .endm
29
30#define UART_SHIFT 2
31#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..870227c96602
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -0,0 +1,47 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/entry-macro.S
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <mach/hardware.h>
20#include <mach/platform.h>
21
22#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
23
24 .macro disable_fiq
25 .endm
26
27 .macro get_irqnr_preamble, base, tmp
28 ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
29 .endm
30
31 .macro arch_ret_to_user, tmp1, tmp2
32 .endm
33
34/*
35 * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
36 * as set if an interrupt is pending.
37 */
38 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
39 ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
40 clz \irqnr, \irqstat
41 rsb \irqnr, \irqnr, #31
42 teq \irqstat, #0
43 .endm
44
45 .macro irq_prio_table
46 .endm
47
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
new file mode 100644
index 000000000000..67d03da1eee9
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -0,0 +1,74 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/gpio.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_GPIO_H
20#define __ASM_ARCH_GPIO_H
21
22#include <asm-generic/gpio.h>
23
24/*
25 * Note!
26 * Muxed GP pins need to be setup to the GP state in the board level
27 * code prior to using this driver.
28 * GPI pins : 28xP3 group
29 * GPO pins : 24xP3 group
30 * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
31 */
32
33#define LPC32XX_GPIO_P0_MAX 8
34#define LPC32XX_GPIO_P1_MAX 24
35#define LPC32XX_GPIO_P2_MAX 13
36#define LPC32XX_GPIO_P3_MAX 6
37#define LPC32XX_GPI_P3_MAX 28
38#define LPC32XX_GPO_P3_MAX 24
39
40#define LPC32XX_GPIO_P0_GRP 0
41#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
42#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
43#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
44#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
45#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
46
47/*
48 * A specific GPIO can be selected with this macro
49 * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
50 * See the LPC32x0 User's guide for GPIO group numbers
51 */
52#define LPC32XX_GPIO(x, y) ((x) + (y))
53
54static inline int gpio_get_value(unsigned gpio)
55{
56 return __gpio_get_value(gpio);
57}
58
59static inline void gpio_set_value(unsigned gpio, int value)
60{
61 __gpio_set_value(gpio, value);
62}
63
64static inline int gpio_cansleep(unsigned gpio)
65{
66 return __gpio_cansleep(gpio);
67}
68
69static inline int gpio_to_irq(unsigned gpio)
70{
71 return __gpio_to_irq(gpio);
72}
73
74#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
new file mode 100644
index 000000000000..33e1dde37bd9
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h
@@ -0,0 +1,34 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/hardware.h
3 *
4 * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __ASM_ARCH_HARDWARE_H
18#define __ASM_ARCH_HARDWARE_H
19
20/*
21 * Start of virtual addresses for IO devices
22 */
23#define IO_BASE 0xF0000000
24
25/*
26 * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
27 */
28#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
29 IO_BASE)
30
31#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
32#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
33
34#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/i2c.h b/arch/arm/mach-lpc32xx/include/mach/i2c.h
new file mode 100644
index 000000000000..034dc9286bcc
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/i2c.h
@@ -0,0 +1,63 @@
1/*
2 * PNX4008-specific tweaks for I2C IP3204 block
3 *
4 * Author: Vitaly Wool <vwool@ru.mvista.com>
5 *
6 * 2005 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifndef __ASM_ARCH_I2C_H
13#define __ASM_ARCH_I2C_H
14
15enum {
16 mstatus_tdi = 0x00000001,
17 mstatus_afi = 0x00000002,
18 mstatus_nai = 0x00000004,
19 mstatus_drmi = 0x00000008,
20 mstatus_active = 0x00000020,
21 mstatus_scl = 0x00000040,
22 mstatus_sda = 0x00000080,
23 mstatus_rff = 0x00000100,
24 mstatus_rfe = 0x00000200,
25 mstatus_tff = 0x00000400,
26 mstatus_tfe = 0x00000800,
27};
28
29enum {
30 mcntrl_tdie = 0x00000001,
31 mcntrl_afie = 0x00000002,
32 mcntrl_naie = 0x00000004,
33 mcntrl_drmie = 0x00000008,
34 mcntrl_daie = 0x00000020,
35 mcntrl_rffie = 0x00000040,
36 mcntrl_tffie = 0x00000080,
37 mcntrl_reset = 0x00000100,
38 mcntrl_cdbmode = 0x00000400,
39};
40
41enum {
42 rw_bit = 1 << 0,
43 start_bit = 1 << 8,
44 stop_bit = 1 << 9,
45};
46
47#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
48#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
49#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
50#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
51#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
52#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
53#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
54#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
55#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
56#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
57#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
58#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
59#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
60
61#define I2C_CHIP_NAME "PNX4008-I2C"
62
63#endif /* __ASM_ARCH_I2C_H */
diff --git a/arch/arm/mach-lpc32xx/include/mach/io.h b/arch/arm/mach-lpc32xx/include/mach/io.h
new file mode 100644
index 000000000000..9b59ab5cef89
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/io.h
@@ -0,0 +1,27 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/io.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARM_ARCH_IO_H
21
22#define IO_SPACE_LIMIT 0xffffffff
23
24#define __io(a) __typesafe_io(a)
25#define __mem_pci(a) (a)
26
27#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
new file mode 100644
index 000000000000..2667f52e3b04
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -0,0 +1,117 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/irqs.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARM_ARCH_IRQS_H
20#define __ASM_ARM_ARCH_IRQS_H
21
22#define LPC32XX_SIC1_IRQ(n) (32 + (n))
23#define LPC32XX_SIC2_IRQ(n) (64 + (n))
24
25/*
26 * MIC interrupts
27 */
28#define IRQ_LPC32XX_SUB1IRQ 0
29#define IRQ_LPC32XX_SUB2IRQ 1
30#define IRQ_LPC32XX_PWM3 3
31#define IRQ_LPC32XX_PWM4 4
32#define IRQ_LPC32XX_HSTIMER 5
33#define IRQ_LPC32XX_WATCH 6
34#define IRQ_LPC32XX_UART_IIR3 7
35#define IRQ_LPC32XX_UART_IIR4 8
36#define IRQ_LPC32XX_UART_IIR5 9
37#define IRQ_LPC32XX_UART_IIR6 10
38#define IRQ_LPC32XX_FLASH 11
39#define IRQ_LPC32XX_SD1 13
40#define IRQ_LPC32XX_LCD 14
41#define IRQ_LPC32XX_SD0 15
42#define IRQ_LPC32XX_TIMER0 16
43#define IRQ_LPC32XX_TIMER1 17
44#define IRQ_LPC32XX_TIMER2 18
45#define IRQ_LPC32XX_TIMER3 19
46#define IRQ_LPC32XX_SSP0 20
47#define IRQ_LPC32XX_SSP1 21
48#define IRQ_LPC32XX_I2S0 22
49#define IRQ_LPC32XX_I2S1 23
50#define IRQ_LPC32XX_UART_IIR7 24
51#define IRQ_LPC32XX_UART_IIR2 25
52#define IRQ_LPC32XX_UART_IIR1 26
53#define IRQ_LPC32XX_MSTIMER 27
54#define IRQ_LPC32XX_DMA 28
55#define IRQ_LPC32XX_ETHERNET 29
56#define IRQ_LPC32XX_SUB1FIQ 30
57#define IRQ_LPC32XX_SUB2FIQ 31
58
59/*
60 * SIC1 interrupts start at offset 32
61 */
62#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
63#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
64#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4)
65#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
66#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
67#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
68#define IRQ_LPC32XX_SPI2 LPC32XX_SIC1_IRQ(12)
69#define IRQ_LPC32XX_PLLUSB LPC32XX_SIC1_IRQ(13)
70#define IRQ_LPC32XX_PLLHCLK LPC32XX_SIC1_IRQ(14)
71#define IRQ_LPC32XX_PLL397 LPC32XX_SIC1_IRQ(17)
72#define IRQ_LPC32XX_I2C_2 LPC32XX_SIC1_IRQ(18)
73#define IRQ_LPC32XX_I2C_1 LPC32XX_SIC1_IRQ(19)
74#define IRQ_LPC32XX_RTC LPC32XX_SIC1_IRQ(20)
75#define IRQ_LPC32XX_KEY LPC32XX_SIC1_IRQ(22)
76#define IRQ_LPC32XX_SPI1 LPC32XX_SIC1_IRQ(23)
77#define IRQ_LPC32XX_SW LPC32XX_SIC1_IRQ(24)
78#define IRQ_LPC32XX_USB_OTG_TIMER LPC32XX_SIC1_IRQ(25)
79#define IRQ_LPC32XX_USB_OTG_ATX LPC32XX_SIC1_IRQ(26)
80#define IRQ_LPC32XX_USB_HOST LPC32XX_SIC1_IRQ(27)
81#define IRQ_LPC32XX_USB_DEV_DMA LPC32XX_SIC1_IRQ(28)
82#define IRQ_LPC32XX_USB_DEV_LP LPC32XX_SIC1_IRQ(29)
83#define IRQ_LPC32XX_USB_DEV_HP LPC32XX_SIC1_IRQ(30)
84#define IRQ_LPC32XX_USB_I2C LPC32XX_SIC1_IRQ(31)
85
86/*
87 * SIC2 interrupts start at offset 64
88 */
89#define IRQ_LPC32XX_GPIO_00 LPC32XX_SIC2_IRQ(0)
90#define IRQ_LPC32XX_GPIO_01 LPC32XX_SIC2_IRQ(1)
91#define IRQ_LPC32XX_GPIO_02 LPC32XX_SIC2_IRQ(2)
92#define IRQ_LPC32XX_GPIO_03 LPC32XX_SIC2_IRQ(3)
93#define IRQ_LPC32XX_GPIO_04 LPC32XX_SIC2_IRQ(4)
94#define IRQ_LPC32XX_GPIO_05 LPC32XX_SIC2_IRQ(5)
95#define IRQ_LPC32XX_SPI2_DATAIN LPC32XX_SIC2_IRQ(6)
96#define IRQ_LPC32XX_U2_HCTS LPC32XX_SIC2_IRQ(7)
97#define IRQ_LPC32XX_P0_P1_IRQ LPC32XX_SIC2_IRQ(8)
98#define IRQ_LPC32XX_GPI_08 LPC32XX_SIC2_IRQ(9)
99#define IRQ_LPC32XX_GPI_09 LPC32XX_SIC2_IRQ(10)
100#define IRQ_LPC32XX_GPI_19 LPC32XX_SIC2_IRQ(11)
101#define IRQ_LPC32XX_U7_HCTS LPC32XX_SIC2_IRQ(12)
102#define IRQ_LPC32XX_GPI_07 LPC32XX_SIC2_IRQ(15)
103#define IRQ_LPC32XX_SDIO LPC32XX_SIC2_IRQ(18)
104#define IRQ_LPC32XX_U5_RX LPC32XX_SIC2_IRQ(19)
105#define IRQ_LPC32XX_SPI1_DATAIN LPC32XX_SIC2_IRQ(20)
106#define IRQ_LPC32XX_GPI_00 LPC32XX_SIC2_IRQ(22)
107#define IRQ_LPC32XX_GPI_01 LPC32XX_SIC2_IRQ(23)
108#define IRQ_LPC32XX_GPI_02 LPC32XX_SIC2_IRQ(24)
109#define IRQ_LPC32XX_GPI_03 LPC32XX_SIC2_IRQ(25)
110#define IRQ_LPC32XX_GPI_04 LPC32XX_SIC2_IRQ(26)
111#define IRQ_LPC32XX_GPI_05 LPC32XX_SIC2_IRQ(27)
112#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28)
113#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31)
114
115#define NR_IRQS 96
116
117#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/memory.h b/arch/arm/mach-lpc32xx/include/mach/memory.h
new file mode 100644
index 000000000000..044e1acecbe6
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/memory.h
@@ -0,0 +1,27 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/memory.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_MEMORY_H
20#define __ASM_ARCH_MEMORY_H
21
22/*
23 * Physical DRAM offset of bank 0
24 */
25#define PHYS_OFFSET UL(0x80000000)
26
27#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
new file mode 100644
index 000000000000..14ea8d1aadb5
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -0,0 +1,694 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/platform.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_PLATFORM_H
20#define __ASM_ARCH_PLATFORM_H
21
22#define _SBF(f, v) ((v) << (f))
23#define _BIT(n) _SBF(n, 1)
24
25/*
26 * AHB 0 physical base addresses
27 */
28#define LPC32XX_SLC_BASE 0x20020000
29#define LPC32XX_SSP0_BASE 0x20084000
30#define LPC32XX_SPI1_BASE 0x20088000
31#define LPC32XX_SSP1_BASE 0x2008C000
32#define LPC32XX_SPI2_BASE 0x20090000
33#define LPC32XX_I2S0_BASE 0x20094000
34#define LPC32XX_SD_BASE 0x20098000
35#define LPC32XX_I2S1_BASE 0x2009C000
36#define LPC32XX_MLC_BASE 0x200A8000
37#define LPC32XX_AHB0_START LPC32XX_SLC_BASE
38#define LPC32XX_AHB0_SIZE 0x00089000
39
40/*
41 * AHB 1 physical base addresses
42 */
43#define LPC32XX_DMA_BASE 0x31000000
44#define LPC32XX_USB_BASE 0x31020000
45#define LPC32XX_USBH_BASE 0x31020000
46#define LPC32XX_USB_OTG_BASE 0x31020000
47#define LPC32XX_OTG_I2C_BASE 0x31020300
48#define LPC32XX_LCD_BASE 0x31040000
49#define LPC32XX_ETHERNET_BASE 0x31060000
50#define LPC32XX_EMC_BASE 0x31080000
51#define LPC32XX_ETB_CFG_BASE 0x310C0000
52#define LPC32XX_ETB_DATA_BASE 0x310E0000
53#define LPC32XX_AHB1_START LPC32XX_DMA_BASE
54#define LPC32XX_AHB1_SIZE 0x000E1000
55
56/*
57 * FAB physical base addresses
58 */
59#define LPC32XX_CLK_PM_BASE 0x40004000
60#define LPC32XX_MIC_BASE 0x40008000
61#define LPC32XX_SIC1_BASE 0x4000C000
62#define LPC32XX_SIC2_BASE 0x40010000
63#define LPC32XX_HS_UART1_BASE 0x40014000
64#define LPC32XX_HS_UART2_BASE 0x40018000
65#define LPC32XX_HS_UART7_BASE 0x4001C000
66#define LPC32XX_RTC_BASE 0x40024000
67#define LPC32XX_RTC_RAM_BASE 0x40024080
68#define LPC32XX_GPIO_BASE 0x40028000
69#define LPC32XX_PWM3_BASE 0x4002C000
70#define LPC32XX_PWM4_BASE 0x40030000
71#define LPC32XX_MSTIM_BASE 0x40034000
72#define LPC32XX_HSTIM_BASE 0x40038000
73#define LPC32XX_WDTIM_BASE 0x4003C000
74#define LPC32XX_DEBUG_CTRL_BASE 0x40040000
75#define LPC32XX_TIMER0_BASE 0x40044000
76#define LPC32XX_ADC_BASE 0x40048000
77#define LPC32XX_TIMER1_BASE 0x4004C000
78#define LPC32XX_KSCAN_BASE 0x40050000
79#define LPC32XX_UART_CTRL_BASE 0x40054000
80#define LPC32XX_TIMER2_BASE 0x40058000
81#define LPC32XX_PWM1_BASE 0x4005C000
82#define LPC32XX_PWM2_BASE 0x4005C004
83#define LPC32XX_TIMER3_BASE 0x40060000
84
85/*
86 * APB physical base addresses
87 */
88#define LPC32XX_UART3_BASE 0x40080000
89#define LPC32XX_UART4_BASE 0x40088000
90#define LPC32XX_UART5_BASE 0x40090000
91#define LPC32XX_UART6_BASE 0x40098000
92#define LPC32XX_I2C1_BASE 0x400A0000
93#define LPC32XX_I2C2_BASE 0x400A8000
94
95/*
96 * FAB and APB base and sizing
97 */
98#define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE
99#define LPC32XX_FABAPB_SIZE 0x000A5000
100
101/*
102 * Internal memory bases and sizes
103 */
104#define LPC32XX_IRAM_BASE 0x08000000
105#define LPC32XX_IROM_BASE 0x0C000000
106
107/*
108 * External Static Memory Bank Address Space Bases
109 */
110#define LPC32XX_EMC_CS0_BASE 0xE0000000
111#define LPC32XX_EMC_CS1_BASE 0xE1000000
112#define LPC32XX_EMC_CS2_BASE 0xE2000000
113#define LPC32XX_EMC_CS3_BASE 0xE3000000
114
115/*
116 * External SDRAM Memory Bank Address Space Bases
117 */
118#define LPC32XX_EMC_DYCS0_BASE 0x80000000
119#define LPC32XX_EMC_DYCS1_BASE 0xA0000000
120
121/*
122 * Clock and crystal information
123 */
124#define LPC32XX_MAIN_OSC_FREQ 13000000
125#define LPC32XX_CLOCK_OSC_FREQ 32768
126
127/*
128 * Clock and Power control register offsets
129 */
130#define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\
131 (x))
132#define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000)
133#define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014)
134#define LPC32XX_CLKPWR_P01_ER _PMREG(0x018)
135#define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C)
136#define LPC32XX_CLKPWR_INT_ER _PMREG(0x020)
137#define LPC32XX_CLKPWR_INT_RS _PMREG(0x024)
138#define LPC32XX_CLKPWR_INT_SR _PMREG(0x028)
139#define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C)
140#define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030)
141#define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034)
142#define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038)
143#define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C)
144#define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040)
145#define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044)
146#define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048)
147#define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C)
148#define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050)
149#define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054)
150#define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058)
151#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060)
152#define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064)
153#define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068)
154#define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C)
155#define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070)
156#define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074)
157#define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078)
158#define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C)
159#define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080)
160#define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090)
161#define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4)
162#define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8)
163#define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC)
164#define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0)
165#define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4)
166#define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8)
167#define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC)
168#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0)
169#define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4)
170#define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8)
171#define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0)
172#define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4)
173#define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8)
174#define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC)
175#define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0)
176#define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4)
177#define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8)
178#define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC)
179#define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x))
180
181/*
182 * clkpwr_debug_ctrl register definitions
183*/
184#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4)
185
186/*
187 * clkpwr_bootmap register definitions
188 */
189#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1)
190
191/*
192 * clkpwr_start_gpio register bit definitions
193 */
194#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31)
195#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30)
196#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29)
197#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28)
198#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27)
199#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26)
200#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25)
201#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24)
202#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23)
203#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22)
204#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21)
205#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20)
206#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19)
207#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18)
208#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17)
209#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16)
210#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15)
211#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14)
212#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13)
213#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12)
214#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11)
215#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10)
216#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9)
217#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8)
218#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7)
219#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6)
220#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5)
221#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4)
222#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3)
223#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2)
224#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1)
225#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0)
226
227/*
228 * clkpwr_usbclk_pdiv register definitions
229 */
230#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF
231
232/*
233 * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int,
234 * clkpwr_start_pol_int, register bit definitions
235 */
236#define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31)
237#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30)
238#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29)
239#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26)
240#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25)
241#define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24)
242#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23)
243#define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22)
244#define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21)
245#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20)
246#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19)
247#define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16)
248#define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7)
249#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6)
250#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5)
251#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4)
252#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3)
253#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2)
254#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1)
255#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0)
256
257/*
258 * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin,
259 * clkpwr_start_pol_pin register bit definitions
260 */
261#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31)
262#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30)
263#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28)
264#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26)
265#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25)
266#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24)
267#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23)
268#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22)
269#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21)
270#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18)
271#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17)
272#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16)
273#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15)
274#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14)
275#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13)
276#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12)
277#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11)
278#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10)
279#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9)
280#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8)
281#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7)
282#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6)
283#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5)
284#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4)
285#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3)
286
287/*
288 * clkpwr_hclk_div register definitions
289 */
290#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7)
291#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7)
292#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7)
293#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2)
294#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3)
295
296/*
297 * clkpwr_pwr_ctrl register definitions
298 */
299#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10)
300#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9)
301#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8)
302#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7)
303#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5)
304#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4)
305#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3)
306#define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2)
307#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1)
308#define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0)
309
310/*
311 * clkpwr_pll397_ctrl register definitions
312 */
313#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10)
314#define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9)
315#define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000
316#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040
317#define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080
318#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0
319#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100
320#define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140
321#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180
322#define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0
323#define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0
324#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1)
325#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0)
326
327/*
328 * clkpwr_main_osc_ctrl register definitions
329 */
330#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2)
331#define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2)
332#define LPC32XX_CLKPWR_TEST_MODE _BIT(1)
333#define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0)
334
335/*
336 * clkpwr_sysclk_ctrl register definitions
337 */
338#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2)
339#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2)
340#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1)
341#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0)
342
343/*
344 * clkpwr_lcdclk_ctrl register definitions
345 */
346#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000
347#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040
348#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080
349#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0
350#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100
351#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140
352#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180
353#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0
354#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0
355#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020
356#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F)
357#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F
358
359/*
360 * clkpwr_hclkpll_ctrl register definitions
361 */
362#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16)
363#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15)
364#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14)
365#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13)
366#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
367#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
368#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1)
369#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0)
370
371/*
372 * clkpwr_adc_clk_ctrl_1 register definitions
373 */
374#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0)
375#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8)
376
377/*
378 * clkpwr_usb_ctrl register definitions
379 */
380#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24)
381#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23)
382#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22)
383#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21)
384#define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19)
385#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19)
386#define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19)
387#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18)
388#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17)
389#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16)
390#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15)
391#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14)
392#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13)
393#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
394#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
395#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1)
396#define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0)
397
398/*
399 * clkpwr_sdramclk_ctrl register definitions
400 */
401#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22)
402#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21)
403#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20)
404#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19)
405#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14)
406#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13)
407#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10)
408#define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9)
409#define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8)
410#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7)
411#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2)
412#define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1)
413#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0)
414
415/*
416 * clkpwr_ssp_blk_ctrl register definitions
417 */
418#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5)
419#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4)
420#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3)
421#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2)
422#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1)
423#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0)
424
425/*
426 * clkpwr_i2s_clk_ctrl register definitions
427 */
428#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6)
429#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5)
430#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4)
431#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3)
432#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2)
433#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1)
434#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0)
435
436/*
437 * clkpwr_ms_ctrl register definitions
438 */
439#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10)
440#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9)
441#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8)
442#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7)
443#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6)
444#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5)
445#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF)
446
447/*
448 * clkpwr_macclk_ctrl register definitions
449 */
450#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00
451#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08
452#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18
453#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18
454#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2)
455#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1)
456#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0)
457
458/*
459 * clkpwr_test_clk_sel register definitions
460 */
461#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5)
462#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5)
463#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5)
464#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5)
465#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4)
466#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1)
467#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1)
468#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1)
469#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1)
470#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1)
471#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1)
472#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0)
473
474/*
475 * clkpwr_sw_int register definitions
476 */
477#define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1))
478#define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1)
479
480/*
481 * clkpwr_i2c_clk_ctrl register definitions
482 */
483#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4)
484#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3)
485#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2)
486#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1)
487#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0)
488
489/*
490 * clkpwr_key_clk_ctrl register definitions
491 */
492#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1
493
494/*
495 * clkpwr_adc_clk_ctrl register definitions
496 */
497#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1
498
499/*
500 * clkpwr_pwm_clk_ctrl register definitions
501 */
502#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8)
503#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4)
504#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8
505#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4
506#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2
507#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1
508
509/*
510 * clkpwr_timer_clk_ctrl register definitions
511 */
512#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2
513#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1
514
515/*
516 * clkpwr_timers_pwms_clk_ctrl_1 register definitions
517 */
518#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20
519#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10
520#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08
521#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04
522#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02
523#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01
524
525/*
526 * clkpwr_spi_clk_ctrl register definitions
527 */
528#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80
529#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40
530#define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20
531#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10
532#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08
533#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04
534#define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02
535#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01
536
537/*
538 * clkpwr_nand_clk_ctrl register definitions
539 */
540#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20
541#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10
542#define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08
543#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04
544#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02
545#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01
546
547/*
548 * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl
549 * and clkpwr_uart6_clk_ctrl register definitions
550 */
551#define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF)
552#define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8)
553#define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16)
554
555/*
556 * clkpwr_irda_clk_ctrl register definitions
557 */
558#define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF)
559#define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8)
560
561/*
562 * clkpwr_uart_clk_ctrl register definitions
563 */
564#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3)
565#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2)
566#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1)
567#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0)
568
569/*
570 * clkpwr_dmaclk_ctrl register definitions
571 */
572#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1
573
574/*
575 * clkpwr_autoclock register definitions
576 */
577#define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40
578#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02
579#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01
580
581/*
582 * Interrupt controller register offsets
583 */
584#define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00)
585#define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04)
586#define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08)
587#define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C)
588#define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10)
589#define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14)
590
591/*
592 * Timer/counter register offsets
593 */
594#define LCP32XX_TIMER_IR(x) io_p2v((x) + 0x00)
595#define LCP32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
596#define LCP32XX_TIMER_TC(x) io_p2v((x) + 0x08)
597#define LCP32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
598#define LCP32XX_TIMER_PC(x) io_p2v((x) + 0x10)
599#define LCP32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
600#define LCP32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
601#define LCP32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
602#define LCP32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
603#define LCP32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
604#define LCP32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
605#define LCP32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
606#define LCP32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
607#define LCP32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
608#define LCP32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
609#define LCP32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
610#define LCP32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
611
612/*
613 * ir register definitions
614 */
615#define LCP32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
616#define LCP32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
617
618/*
619 * tcr register definitions
620 */
621#define LCP32XX_TIMER_CNTR_TCR_EN 0x1
622#define LCP32XX_TIMER_CNTR_TCR_RESET 0x2
623
624/*
625 * mcr register definitions
626 */
627#define LCP32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
628#define LCP32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
629#define LCP32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
630
631/*
632 * Standard UART register offsets
633 */
634#define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00)
635#define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04)
636#define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08)
637#define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C)
638#define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10)
639#define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14)
640#define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18)
641#define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C)
642
643/*
644 * UART control structure offsets
645 */
646#define _UCREG(x) io_p2v(\
647 LPC32XX_UART_CTRL_BASE + (x))
648#define LPC32XX_UARTCTL_CTRL _UCREG(0x00)
649#define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04)
650#define LPC32XX_UARTCTL_CLOOP _UCREG(0x08)
651
652/*
653 * ctrl register definitions
654 */
655#define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11)
656#define LPC32XX_UART_IRRX6_INV_EN _BIT(10)
657#define LPC32XX_UART_HDPX_EN _BIT(9)
658#define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5)
659#define LPC32XX_RT_IRTX6_INV_EN _BIT(4)
660#define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3)
661#define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2)
662#define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1)
663#define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0)
664
665/*
666 * clkmode register definitions
667 */
668#define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F)
669#define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1)
670#define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14)
671#define LPC32XX_UART_CLKMODE_OFF 0x0
672#define LPC32XX_UART_CLKMODE_ON 0x1
673#define LPC32XX_UART_CLKMODE_AUTO 0x2
674#define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4))
675#define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4))
676
677/*
678 * GPIO Module Register offsets
679 */
680#define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x))
681#define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100)
682#define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104)
683#define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108)
684#define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110)
685#define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114)
686#define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118)
687#define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120)
688#define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124)
689#define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128)
690#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130)
691#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134)
692#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138)
693
694#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h
new file mode 100644
index 000000000000..df3b0dea4d7b
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/system.h
@@ -0,0 +1,52 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/system.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_SYSTEM_H
20#define __ASM_ARCH_SYSTEM_H
21
22static void arch_idle(void)
23{
24 cpu_do_idle();
25}
26
27static inline void arch_reset(char mode, const char *cmd)
28{
29 extern void lpc32xx_watchdog_reset(void);
30
31 switch (mode) {
32 case 's':
33 case 'h':
34 printk(KERN_CRIT "RESET: Rebooting system\n");
35
36 /* Disable interrupts */
37 local_irq_disable();
38
39 lpc32xx_watchdog_reset();
40 break;
41
42 default:
43 /* Do nothing */
44 break;
45 }
46
47 /* Wait for watchdog to reset system */
48 while (1)
49 ;
50}
51
52#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/timex.h b/arch/arm/mach-lpc32xx/include/mach/timex.h
new file mode 100644
index 000000000000..8d4066b16b3f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/timex.h
@@ -0,0 +1,28 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/timex.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_TIMEX_H
20#define __ASM_ARCH_TIMEX_H
21
22/*
23 * Rate in Hz of the main system oscillator. This value should match
24 * the value 'MAIN_OSC_FREQ' in platform.h
25 */
26#define CLOCK_TICK_RATE 13000000
27
28#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c142487d299a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
@@ -0,0 +1,60 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/uncompress.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H
20#define __ASM_ARM_ARCH_UNCOMPRESS_H
21
22#include <linux/io.h>
23
24#include <mach/hardware.h>
25#include <mach/platform.h>
26
27/*
28 * Uncompress output is hardcoded to standard UART 5
29 */
30
31#define UART_FIFO_CTL_TX_RESET (1 << 2)
32#define UART_STATUS_TX_MT (1 << 6)
33
34#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x))
35
36#define LPC32XX_UART_DLLFIFO_O 0x00
37#define LPC32XX_UART_IIRFCR_O 0x08
38#define LPC32XX_UART_LSR_O 0x14
39
40static inline void putc(int ch)
41{
42 /* Wait for transmit FIFO to empty */
43 while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) &
44 UART_STATUS_TX_MT) == 0)
45 ;
46
47 __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O));
48}
49
50static inline void flush(void)
51{
52 __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) |
53 UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O));
54}
55
56/* NULL functions; we don't presently need them */
57#define arch_decomp_setup()
58#define arch_decomp_wdog()
59
60#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..d1d936c7236d
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/vmalloc.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_VMALLOC_H
20#define __ASM_ARCH_VMALLOC_H
21
22#define VMALLOC_END 0xF0000000
23
24#endif
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
new file mode 100644
index 000000000000..bd0df26c415b
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -0,0 +1,432 @@
1/*
2 * arch/arm/mach-lpc32xx/irq.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/err.h>
24#include <linux/io.h>
25
26#include <mach/irqs.h>
27#include <mach/hardware.h>
28#include <mach/platform.h>
29#include "common.h"
30
31/*
32 * Default value representing the Activation polarity of all internal
33 * interrupt sources
34 */
35#define MIC_APR_DEFAULT 0x3FF0EFE0
36#define SIC1_APR_DEFAULT 0xFBD27186
37#define SIC2_APR_DEFAULT 0x801810C0
38
39/*
40 * Default value representing the Activation Type of all internal
41 * interrupt sources. All are level sensitive.
42 */
43#define MIC_ATR_DEFAULT 0x00000000
44#define SIC1_ATR_DEFAULT 0x00026000
45#define SIC2_ATR_DEFAULT 0x00000000
46
47struct lpc32xx_event_group_regs {
48 void __iomem *enab_reg;
49 void __iomem *edge_reg;
50 void __iomem *maskstat_reg;
51 void __iomem *rawstat_reg;
52};
53
54static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = {
55 .enab_reg = LPC32XX_CLKPWR_INT_ER,
56 .edge_reg = LPC32XX_CLKPWR_INT_AP,
57 .maskstat_reg = LPC32XX_CLKPWR_INT_SR,
58 .rawstat_reg = LPC32XX_CLKPWR_INT_RS,
59};
60
61static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = {
62 .enab_reg = LPC32XX_CLKPWR_PIN_ER,
63 .edge_reg = LPC32XX_CLKPWR_PIN_AP,
64 .maskstat_reg = LPC32XX_CLKPWR_PIN_SR,
65 .rawstat_reg = LPC32XX_CLKPWR_PIN_RS,
66};
67
68struct lpc32xx_event_info {
69 const struct lpc32xx_event_group_regs *event_group;
70 u32 mask;
71};
72
73/*
74 * Maps an IRQ number to and event mask and register
75 */
76static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
77 [IRQ_LPC32XX_GPI_08] = {
78 .event_group = &lpc32xx_event_pin_regs,
79 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
80 },
81 [IRQ_LPC32XX_GPI_09] = {
82 .event_group = &lpc32xx_event_pin_regs,
83 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
84 },
85 [IRQ_LPC32XX_GPI_19] = {
86 .event_group = &lpc32xx_event_pin_regs,
87 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
88 },
89 [IRQ_LPC32XX_GPI_07] = {
90 .event_group = &lpc32xx_event_pin_regs,
91 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
92 },
93 [IRQ_LPC32XX_GPI_00] = {
94 .event_group = &lpc32xx_event_pin_regs,
95 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
96 },
97 [IRQ_LPC32XX_GPI_01] = {
98 .event_group = &lpc32xx_event_pin_regs,
99 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
100 },
101 [IRQ_LPC32XX_GPI_02] = {
102 .event_group = &lpc32xx_event_pin_regs,
103 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
104 },
105 [IRQ_LPC32XX_GPI_03] = {
106 .event_group = &lpc32xx_event_pin_regs,
107 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
108 },
109 [IRQ_LPC32XX_GPI_04] = {
110 .event_group = &lpc32xx_event_pin_regs,
111 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
112 },
113 [IRQ_LPC32XX_GPI_05] = {
114 .event_group = &lpc32xx_event_pin_regs,
115 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
116 },
117 [IRQ_LPC32XX_GPI_06] = {
118 .event_group = &lpc32xx_event_pin_regs,
119 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
120 },
121 [IRQ_LPC32XX_GPIO_00] = {
122 .event_group = &lpc32xx_event_int_regs,
123 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
124 },
125 [IRQ_LPC32XX_GPIO_01] = {
126 .event_group = &lpc32xx_event_int_regs,
127 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
128 },
129 [IRQ_LPC32XX_GPIO_02] = {
130 .event_group = &lpc32xx_event_int_regs,
131 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
132 },
133 [IRQ_LPC32XX_GPIO_03] = {
134 .event_group = &lpc32xx_event_int_regs,
135 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
136 },
137 [IRQ_LPC32XX_GPIO_04] = {
138 .event_group = &lpc32xx_event_int_regs,
139 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
140 },
141 [IRQ_LPC32XX_GPIO_05] = {
142 .event_group = &lpc32xx_event_int_regs,
143 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
144 },
145 [IRQ_LPC32XX_KEY] = {
146 .event_group = &lpc32xx_event_int_regs,
147 .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
148 },
149 [IRQ_LPC32XX_USB_OTG_ATX] = {
150 .event_group = &lpc32xx_event_int_regs,
151 .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
152 },
153 [IRQ_LPC32XX_USB_HOST] = {
154 .event_group = &lpc32xx_event_int_regs,
155 .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
156 },
157 [IRQ_LPC32XX_RTC] = {
158 .event_group = &lpc32xx_event_int_regs,
159 .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
160 },
161 [IRQ_LPC32XX_MSTIMER] = {
162 .event_group = &lpc32xx_event_int_regs,
163 .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
164 },
165 [IRQ_LPC32XX_TS_AUX] = {
166 .event_group = &lpc32xx_event_int_regs,
167 .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
168 },
169 [IRQ_LPC32XX_TS_P] = {
170 .event_group = &lpc32xx_event_int_regs,
171 .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
172 },
173 [IRQ_LPC32XX_TS_IRQ] = {
174 .event_group = &lpc32xx_event_int_regs,
175 .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
176 },
177};
178
179static void get_controller(unsigned int irq, unsigned int *base,
180 unsigned int *irqbit)
181{
182 if (irq < 32) {
183 *base = LPC32XX_MIC_BASE;
184 *irqbit = 1 << irq;
185 } else if (irq < 64) {
186 *base = LPC32XX_SIC1_BASE;
187 *irqbit = 1 << (irq - 32);
188 } else {
189 *base = LPC32XX_SIC2_BASE;
190 *irqbit = 1 << (irq - 64);
191 }
192}
193
194static void lpc32xx_mask_irq(unsigned int irq)
195{
196 unsigned int reg, ctrl, mask;
197
198 get_controller(irq, &ctrl, &mask);
199
200 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
201 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
202}
203
204static void lpc32xx_unmask_irq(unsigned int irq)
205{
206 unsigned int reg, ctrl, mask;
207
208 get_controller(irq, &ctrl, &mask);
209
210 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
211 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
212}
213
214static void lpc32xx_ack_irq(unsigned int irq)
215{
216 unsigned int ctrl, mask;
217
218 get_controller(irq, &ctrl, &mask);
219
220 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
221
222 /* Also need to clear pending wake event */
223 if (lpc32xx_events[irq].mask != 0)
224 __raw_writel(lpc32xx_events[irq].mask,
225 lpc32xx_events[irq].event_group->rawstat_reg);
226}
227
228static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
229 int use_edge)
230{
231 unsigned int reg, ctrl, mask;
232
233 get_controller(irq, &ctrl, &mask);
234
235 /* Activation level, high or low */
236 reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl));
237 if (use_high_level)
238 reg |= mask;
239 else
240 reg &= ~mask;
241 __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));
242
243 /* Activation type, edge or level */
244 reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl));
245 if (use_edge)
246 reg |= mask;
247 else
248 reg &= ~mask;
249 __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
250
251 /* Use same polarity for the wake events */
252 if (lpc32xx_events[irq].mask != 0) {
253 reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg);
254
255 if (use_high_level)
256 reg |= lpc32xx_events[irq].mask;
257 else
258 reg &= ~lpc32xx_events[irq].mask;
259
260 __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);
261 }
262}
263
264static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
265{
266 switch (type) {
267 case IRQ_TYPE_EDGE_RISING:
268 /* Rising edge sensitive */
269 __lpc32xx_set_irq_type(irq, 1, 1);
270 break;
271
272 case IRQ_TYPE_EDGE_FALLING:
273 /* Falling edge sensitive */
274 __lpc32xx_set_irq_type(irq, 0, 1);
275 break;
276
277 case IRQ_TYPE_LEVEL_LOW:
278 /* Low level sensitive */
279 __lpc32xx_set_irq_type(irq, 0, 0);
280 break;
281
282 case IRQ_TYPE_LEVEL_HIGH:
283 /* High level sensitive */
284 __lpc32xx_set_irq_type(irq, 1, 0);
285 break;
286
287 /* Other modes are not supported */
288 default:
289 return -EINVAL;
290 }
291
292 /* Ok to use the level handler for all types */
293 set_irq_handler(irq, handle_level_irq);
294
295 return 0;
296}
297
298static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state)
299{
300 unsigned long eventreg;
301
302 if (lpc32xx_events[irqno].mask != 0) {
303 eventreg = __raw_readl(lpc32xx_events[irqno].
304 event_group->enab_reg);
305
306 if (state)
307 eventreg |= lpc32xx_events[irqno].mask;
308 else
309 eventreg &= ~lpc32xx_events[irqno].mask;
310
311 __raw_writel(eventreg,
312 lpc32xx_events[irqno].event_group->enab_reg);
313
314 return 0;
315 }
316
317 /* Clear event */
318 __raw_writel(lpc32xx_events[irqno].mask,
319 lpc32xx_events[irqno].event_group->rawstat_reg);
320
321 return -ENODEV;
322}
323
324static void __init lpc32xx_set_default_mappings(unsigned int apr,
325 unsigned int atr, unsigned int offset)
326{
327 unsigned int i;
328
329 /* Set activation levels for each interrupt */
330 i = 0;
331 while (i < 32) {
332 __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1),
333 ((atr >> i) & 0x1));
334 i++;
335 }
336}
337
338static struct irq_chip lpc32xx_irq_chip = {
339 .ack = lpc32xx_ack_irq,
340 .mask = lpc32xx_mask_irq,
341 .unmask = lpc32xx_unmask_irq,
342 .set_type = lpc32xx_set_irq_type,
343 .set_wake = lpc32xx_irq_wake
344};
345
346static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
347{
348 unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
349
350 while (ints != 0) {
351 int irqno = fls(ints) - 1;
352
353 ints &= ~(1 << irqno);
354
355 generic_handle_irq(LPC32XX_SIC1_IRQ(irqno));
356 }
357}
358
359static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
360{
361 unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
362
363 while (ints != 0) {
364 int irqno = fls(ints) - 1;
365
366 ints &= ~(1 << irqno);
367
368 generic_handle_irq(LPC32XX_SIC2_IRQ(irqno));
369 }
370}
371
372void __init lpc32xx_init_irq(void)
373{
374 unsigned int i;
375
376 /* Setup MIC */
377 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
378 __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));
379 __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));
380
381 /* Setup SIC1 */
382 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
383 __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
384 __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
385
386 /* Setup SIC2 */
387 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
388 __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
389 __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
390
391 /* Configure supported IRQ's */
392 for (i = 0; i < NR_IRQS; i++) {
393 set_irq_chip(i, &lpc32xx_irq_chip);
394 set_irq_handler(i, handle_level_irq);
395 set_irq_flags(i, IRQF_VALID);
396 }
397
398 /* Set default mappings */
399 lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0);
400 lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
401 lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
402
403 /* mask all interrupts except SUBIRQ */
404 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
405 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
406 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
407
408 /* MIC SUBIRQx interrupts will route handling to the chain handlers */
409 set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
410 set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
411
412 /* Initially disable all wake events */
413 __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
414 __raw_writel(0, LPC32XX_CLKPWR_INT_ER);
415 __raw_writel(0, LPC32XX_CLKPWR_PIN_ER);
416
417 /*
418 * Default wake activation polarities, all pin sources are low edge
419 * triggered
420 */
421 __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |
422 LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT |
423 LPC32XX_CLKPWR_INTSRC_RTC_BIT,
424 LPC32XX_CLKPWR_INT_AP);
425 __raw_writel(0, LPC32XX_CLKPWR_PIN_AP);
426
427 /* Clear latched wake event states */
428 __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),
429 LPC32XX_CLKPWR_PIN_RS);
430 __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
431 LPC32XX_CLKPWR_INT_RS);
432}
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
new file mode 100644
index 000000000000..bc9a42da2145
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -0,0 +1,397 @@
1/*
2 * arch/arm/mach-lpc32xx/phy3250.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/sysdev.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/dma-mapping.h>
25#include <linux/device.h>
26#include <linux/spi/spi.h>
27#include <linux/spi/eeprom.h>
28#include <linux/leds.h>
29#include <linux/gpio.h>
30#include <linux/amba/bus.h>
31#include <linux/amba/clcd.h>
32#include <linux/amba/pl022.h>
33
34#include <asm/setup.h>
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37
38#include <mach/hardware.h>
39#include <mach/platform.h>
40#include "common.h"
41
42/*
43 * Mapped GPIOLIB GPIOs
44 */
45#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
46#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
47#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
48#define LED_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
49
50/*
51 * AMBA LCD controller
52 */
53static struct clcd_panel conn_lcd_panel = {
54 .mode = {
55 .name = "QVGA portrait",
56 .refresh = 60,
57 .xres = 240,
58 .yres = 320,
59 .pixclock = 191828,
60 .left_margin = 22,
61 .right_margin = 11,
62 .upper_margin = 2,
63 .lower_margin = 1,
64 .hsync_len = 5,
65 .vsync_len = 2,
66 .sync = 0,
67 .vmode = FB_VMODE_NONINTERLACED,
68 },
69 .width = -1,
70 .height = -1,
71 .tim2 = (TIM2_IVS | TIM2_IHS),
72 .cntl = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
73 CNTL_LCDBPP16_565),
74 .bpp = 16,
75};
76#define PANEL_SIZE (3 * SZ_64K)
77
78static int lpc32xx_clcd_setup(struct clcd_fb *fb)
79{
80 dma_addr_t dma;
81
82 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
83 PANEL_SIZE, &dma, GFP_KERNEL);
84 if (!fb->fb.screen_base) {
85 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
86 return -ENOMEM;
87 }
88
89 fb->fb.fix.smem_start = dma;
90 fb->fb.fix.smem_len = PANEL_SIZE;
91 fb->panel = &conn_lcd_panel;
92
93 if (gpio_request(LCD_POWER_GPIO, "LCD power"))
94 printk(KERN_ERR "Error requesting gpio %u",
95 LCD_POWER_GPIO);
96 else if (gpio_direction_output(LCD_POWER_GPIO, 1))
97 printk(KERN_ERR "Error setting gpio %u to output",
98 LCD_POWER_GPIO);
99
100 if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
101 printk(KERN_ERR "Error requesting gpio %u",
102 BKL_POWER_GPIO);
103 else if (gpio_direction_output(BKL_POWER_GPIO, 1))
104 printk(KERN_ERR "Error setting gpio %u to output",
105 BKL_POWER_GPIO);
106
107 return 0;
108}
109
110static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
111{
112 return dma_mmap_writecombine(&fb->dev->dev, vma,
113 fb->fb.screen_base, fb->fb.fix.smem_start,
114 fb->fb.fix.smem_len);
115}
116
117static void lpc32xx_clcd_remove(struct clcd_fb *fb)
118{
119 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
120 fb->fb.screen_base, fb->fb.fix.smem_start);
121}
122
123/*
124 * On some early LCD modules (1307.0), the backlight logic is inverted.
125 * For those board variants, swap the disable and enable states for
126 * BKL_POWER_GPIO.
127*/
128static void clcd_disable(struct clcd_fb *fb)
129{
130 gpio_set_value(BKL_POWER_GPIO, 0);
131 gpio_set_value(LCD_POWER_GPIO, 0);
132}
133
134static void clcd_enable(struct clcd_fb *fb)
135{
136 gpio_set_value(BKL_POWER_GPIO, 1);
137 gpio_set_value(LCD_POWER_GPIO, 1);
138}
139
140static struct clcd_board lpc32xx_clcd_data = {
141 .name = "Phytec LCD",
142 .check = clcdfb_check,
143 .decode = clcdfb_decode,
144 .disable = clcd_disable,
145 .enable = clcd_enable,
146 .setup = lpc32xx_clcd_setup,
147 .mmap = lpc32xx_clcd_mmap,
148 .remove = lpc32xx_clcd_remove,
149};
150
151static struct amba_device lpc32xx_clcd_device = {
152 .dev = {
153 .coherent_dma_mask = ~0,
154 .init_name = "dev:clcd",
155 .platform_data = &lpc32xx_clcd_data,
156 },
157 .res = {
158 .start = LPC32XX_LCD_BASE,
159 .end = (LPC32XX_LCD_BASE + SZ_4K - 1),
160 .flags = IORESOURCE_MEM,
161 },
162 .dma_mask = ~0,
163 .irq = {IRQ_LPC32XX_LCD, NO_IRQ},
164};
165
166/*
167 * AMBA SSP (SPI)
168 */
169static void phy3250_spi_cs_set(u32 control)
170{
171 gpio_set_value(SPI0_CS_GPIO, (int) control);
172}
173
174static struct pl022_config_chip spi0_chip_info = {
175 .lbm = LOOPBACK_DISABLED,
176 .com_mode = INTERRUPT_TRANSFER,
177 .iface = SSP_INTERFACE_MOTOROLA_SPI,
178 .hierarchy = SSP_MASTER,
179 .slave_tx_disable = 0,
180 .endian_tx = SSP_TX_LSB,
181 .endian_rx = SSP_RX_LSB,
182 .data_size = SSP_DATA_BITS_8,
183 .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
184 .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
185 .clk_phase = SSP_CLK_FIRST_EDGE,
186 .clk_pol = SSP_CLK_POL_IDLE_LOW,
187 .ctrl_len = SSP_BITS_8,
188 .wait_state = SSP_MWIRE_WAIT_ZERO,
189 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
190 .cs_control = phy3250_spi_cs_set,
191};
192
193static struct pl022_ssp_controller lpc32xx_ssp0_data = {
194 .bus_id = 0,
195 .num_chipselect = 1,
196 .enable_dma = 0,
197};
198
199static struct amba_device lpc32xx_ssp0_device = {
200 .dev = {
201 .coherent_dma_mask = ~0,
202 .init_name = "dev:ssp0",
203 .platform_data = &lpc32xx_ssp0_data,
204 },
205 .res = {
206 .start = LPC32XX_SSP0_BASE,
207 .end = (LPC32XX_SSP0_BASE + SZ_4K - 1),
208 .flags = IORESOURCE_MEM,
209 },
210 .dma_mask = ~0,
211 .irq = {IRQ_LPC32XX_SSP0, NO_IRQ},
212};
213
214/* AT25 driver registration */
215static int __init phy3250_spi_board_register(void)
216{
217#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
218 static struct spi_board_info info[] = {
219 {
220 .modalias = "spidev",
221 .max_speed_hz = 5000000,
222 .bus_num = 0,
223 .chip_select = 0,
224 .controller_data = &spi0_chip_info,
225 },
226 };
227
228#else
229 static struct spi_eeprom eeprom = {
230 .name = "at25256a",
231 .byte_len = 0x8000,
232 .page_size = 64,
233 .flags = EE_ADDR2,
234 };
235
236 static struct spi_board_info info[] = {
237 {
238 .modalias = "at25",
239 .max_speed_hz = 5000000,
240 .bus_num = 0,
241 .chip_select = 0,
242 .platform_data = &eeprom,
243 .controller_data = &spi0_chip_info,
244 },
245 };
246#endif
247 return spi_register_board_info(info, ARRAY_SIZE(info));
248}
249arch_initcall(phy3250_spi_board_register);
250
251static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
252 {
253 I2C_BOARD_INFO("pcf8563", 0x51),
254 },
255};
256
257static struct gpio_led phy_leds[] = {
258 {
259 .name = "led0",
260 .gpio = LED_GPIO,
261 .active_low = 1,
262 .default_trigger = "heartbeat",
263 },
264};
265
266static struct gpio_led_platform_data led_data = {
267 .leds = phy_leds,
268 .num_leds = ARRAY_SIZE(phy_leds),
269};
270
271static struct platform_device lpc32xx_gpio_led_device = {
272 .name = "leds-gpio",
273 .id = -1,
274 .dev.platform_data = &led_data,
275};
276
277static struct platform_device *phy3250_devs[] __initdata = {
278 &lpc32xx_i2c0_device,
279 &lpc32xx_i2c1_device,
280 &lpc32xx_i2c2_device,
281 &lpc32xx_watchdog_device,
282 &lpc32xx_gpio_led_device,
283};
284
285static struct amba_device *amba_devs[] __initdata = {
286 &lpc32xx_clcd_device,
287 &lpc32xx_ssp0_device,
288};
289
290/*
291 * Board specific functions
292 */
293static void __init phy3250_board_init(void)
294{
295 u32 tmp;
296 int i;
297
298 lpc32xx_gpio_init();
299
300 /* Register GPIOs used on this board */
301 if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
302 printk(KERN_ERR "Error requesting gpio %u",
303 SPI0_CS_GPIO);
304 else if (gpio_direction_output(SPI0_CS_GPIO, 1))
305 printk(KERN_ERR "Error setting gpio %u to output",
306 SPI0_CS_GPIO);
307
308 /* Setup network interface for RMII mode */
309 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
310 tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
311 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
312 __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
313
314 /* Setup SLC NAND controller muxing */
315 __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
316 LPC32XX_CLKPWR_NAND_CLK_CTRL);
317
318 /* Setup LCD muxing to RGB565 */
319 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
320 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
321 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
322 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
323 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
324
325 /* Set up I2C pull levels */
326 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
327 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
328 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
329 __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
330
331 /* Disable IrDA pulsing support on UART6 */
332 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
333 tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
334 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
335
336 /* Enable DMA for I2S1 channel */
337 tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
338 tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
339 __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
340
341 lpc32xx_serial_init();
342
343 /*
344 * AMBA peripheral clocks need to be enabled prior to AMBA device
345 * detection or a data fault will occur, so enable the clocks
346 * here. However, we don't want to enable them if the peripheral
347 * isn't included in the image
348 */
349#ifdef CONFIG_FB_ARMCLCD
350 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
351 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
352 LPC32XX_CLKPWR_LCDCLK_CTRL);
353#endif
354#ifdef CONFIG_SPI_PL022
355 tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
356 __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
357 LPC32XX_CLKPWR_SSP_CLK_CTRL);
358#endif
359
360 platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
361 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
362 struct amba_device *d = amba_devs[i];
363 amba_device_register(d, &iomem_resource);
364 }
365
366 /* Test clock needed for UDA1380 initial init */
367 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
368 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
369 LPC32XX_CLKPWR_TEST_CLK_SEL);
370
371 i2c_register_board_info(0, phy3250_i2c_board_info,
372 ARRAY_SIZE(phy3250_i2c_board_info));
373}
374
375static int __init lpc32xx_display_uid(void)
376{
377 u32 uid[4];
378
379 lpc32xx_get_uid(uid);
380
381 printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
382 uid[3], uid[2], uid[1], uid[0]);
383
384 return 1;
385}
386arch_initcall(lpc32xx_display_uid);
387
388MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
389 /* Maintainer: Kevin Wells, NXP Semiconductors */
390 .phys_io = LPC32XX_UART5_BASE,
391 .io_pg_offst = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
392 .boot_params = 0x80000100,
393 .map_io = lpc32xx_map_io,
394 .init_irq = lpc32xx_init_irq,
395 .timer = &lpc32xx_timer,
396 .init_machine = phy3250_board_init,
397MACHINE_END
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
new file mode 100644
index 000000000000..a6e2aed9a49f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -0,0 +1,146 @@
1/*
2 * arch/arm/mach-lpc32xx/pm.c
3 *
4 * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
5 * Modified by Kevin Wells <kevin.wells@nxp.com>
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/*
14 * LPC32XX CPU and system power management
15 *
16 * The LCP32XX has three CPU modes for controlling system power: run,
17 * direct-run, and halt modes. When switching between halt and run modes,
18 * the CPU transistions through direct-run mode. For Linux, direct-run
19 * mode is not used in normal operation. Halt mode is used when the
20 * system is fully suspended.
21 *
22 * Run mode:
23 * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
24 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
25 * the HCLK_PLL rate. Linux runs in this mode.
26 *
27 * Direct-run mode:
28 * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
29 * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
30 * source or the frequency of the main oscillator. In this mode, the
31 * HCLK_PLL can be safely enabled, changed, or disabled.
32 *
33 * Halt mode:
34 * SYSCLK is gated off and the CPU and system clocks are halted.
35 * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
36 * key scanner, etc.) still operate if enabled. In this state, an enabled
37 * system event (ie, GPIO state change, RTC match, key press, etc.) will
38 * wake the system up back into direct-run mode.
39 *
40 * DRAM refresh
41 * DRAM clocking and refresh are slightly different for systems with DDR
42 * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
43 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
44 * a transistion to direct-run mode will stop all DDR accesses (no clocks).
45 * Because of this, the code to switch power modes and the code to enter
46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
47 * section of IRAM is used instead for this.
48 *
49 * Suspend is handled with the following logic:
50 * Backup a small area of IRAM used for the suspend code
51 * Copy suspend code to IRAM
52 * Transfer control to code in IRAM
53 * Places DRAMs in self-refresh mode
54 * Enter direct-run mode
55 * Save state of HCLK_PLL PLL
56 * Disable HCLK_PLL PLL
57 * Enter halt mode - CPU and buses will stop
58 * System enters direct-run mode when an enabled event occurs
59 * HCLK PLL state is restored
60 * Run mode is entered
61 * DRAMS are placed back into normal mode
62 * Code execution returns from IRAM
63 * IRAM code are used for suspend is restored
64 * Suspend mode is exited
65 */
66
67#include <linux/suspend.h>
68#include <linux/io.h>
69#include <linux/slab.h>
70
71#include <asm/cacheflush.h>
72
73#include <mach/hardware.h>
74#include <mach/platform.h>
75#include "common.h"
76#include "clock.h"
77
78#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
79
80/*
81 * Both STANDBY and MEM suspend states are handled the same with no
82 * loss of CPU or memory state
83 */
84static int lpc32xx_pm_enter(suspend_state_t state)
85{
86 int (*lpc32xx_suspend_ptr) (void);
87 void *iram_swap_area;
88
89 /* Allocate some space for temporary IRAM storage */
90 iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL);
91 if (!iram_swap_area) {
92 printk(KERN_ERR
93 "PM Suspend: cannot allocate memory to save portion "
94 "of SRAM\n");
95 return -ENOMEM;
96 }
97
98 /* Backup a small area of IRAM used for the suspend code */
99 memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA,
100 lpc32xx_sys_suspend_sz);
101
102 /*
103 * Copy code to suspend system into IRAM. The suspend code
104 * needs to run from IRAM as DRAM may no longer be available
105 * when the PLL is stopped.
106 */
107 memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
108 lpc32xx_sys_suspend_sz);
109 flush_icache_range((unsigned long)TEMP_IRAM_AREA,
110 (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
111
112 /* Transfer to suspend code in IRAM */
113 lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
114 flush_cache_all();
115 (void) lpc32xx_suspend_ptr();
116
117 /* Restore original IRAM contents */
118 memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
119 lpc32xx_sys_suspend_sz);
120
121 kfree(iram_swap_area);
122
123 return 0;
124}
125
126static struct platform_suspend_ops lpc32xx_pm_ops = {
127 .valid = suspend_valid_only_mem,
128 .enter = lpc32xx_pm_enter,
129};
130
131#define EMC_DYN_MEM_CTRL_OFS 0x20
132#define EMC_SRMMC (1 << 3)
133#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
134static int __init lpc32xx_pm_init(void)
135{
136 /*
137 * Setup SDRAM self-refresh clock to automatically disable o
138 * start of self-refresh. This only needs to be done once.
139 */
140 __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
141
142 suspend_set_ops(&lpc32xx_pm_ops);
143
144 return 0;
145}
146arch_initcall(lpc32xx_pm_init);
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
new file mode 100644
index 000000000000..429cfdbb2b3d
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -0,0 +1,190 @@
1/*
2 * arch/arm/mach-lpc32xx/serial.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/serial.h>
22#include <linux/serial_core.h>
23#include <linux/serial_reg.h>
24#include <linux/serial_8250.h>
25#include <linux/clk.h>
26#include <linux/io.h>
27
28#include <mach/hardware.h>
29#include <mach/platform.h>
30#include "common.h"
31
32#define LPC32XX_SUART_FIFO_SIZE 64
33
34/* Standard 8250/16550 compatible serial ports */
35static struct plat_serial8250_port serial_std_platform_data[] = {
36#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
37 {
38 .membase = io_p2v(LPC32XX_UART5_BASE),
39 .mapbase = LPC32XX_UART5_BASE,
40 .irq = IRQ_LPC32XX_UART_IIR5,
41 .uartclk = LPC32XX_MAIN_OSC_FREQ,
42 .regshift = 2,
43 .iotype = UPIO_MEM32,
44 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
45 UPF_SKIP_TEST,
46 },
47#endif
48#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
49 {
50 .membase = io_p2v(LPC32XX_UART3_BASE),
51 .mapbase = LPC32XX_UART3_BASE,
52 .irq = IRQ_LPC32XX_UART_IIR3,
53 .uartclk = LPC32XX_MAIN_OSC_FREQ,
54 .regshift = 2,
55 .iotype = UPIO_MEM32,
56 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
57 UPF_SKIP_TEST,
58 },
59#endif
60#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
61 {
62 .membase = io_p2v(LPC32XX_UART4_BASE),
63 .mapbase = LPC32XX_UART4_BASE,
64 .irq = IRQ_LPC32XX_UART_IIR4,
65 .uartclk = LPC32XX_MAIN_OSC_FREQ,
66 .regshift = 2,
67 .iotype = UPIO_MEM32,
68 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
69 UPF_SKIP_TEST,
70 },
71#endif
72#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
73 {
74 .membase = io_p2v(LPC32XX_UART6_BASE),
75 .mapbase = LPC32XX_UART6_BASE,
76 .irq = IRQ_LPC32XX_UART_IIR6,
77 .uartclk = LPC32XX_MAIN_OSC_FREQ,
78 .regshift = 2,
79 .iotype = UPIO_MEM32,
80 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
81 UPF_SKIP_TEST,
82 },
83#endif
84 { },
85};
86
87struct uartinit {
88 char *uart_ck_name;
89 u32 ck_mode_mask;
90 void __iomem *pdiv_clk_reg;
91};
92
93static struct uartinit uartinit_data[] __initdata = {
94#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
95 {
96 .uart_ck_name = "uart5_ck",
97 .ck_mode_mask =
98 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
99 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
100 },
101#endif
102#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
103 {
104 .uart_ck_name = "uart3_ck",
105 .ck_mode_mask =
106 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
107 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
108 },
109#endif
110#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
111 {
112 .uart_ck_name = "uart4_ck",
113 .ck_mode_mask =
114 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
115 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
116 },
117#endif
118#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
119 {
120 .uart_ck_name = "uart6_ck",
121 .ck_mode_mask =
122 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
123 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
124 },
125#endif
126};
127
128static struct platform_device serial_std_platform_device = {
129 .name = "serial8250",
130 .id = 0,
131 .dev = {
132 .platform_data = serial_std_platform_data,
133 },
134};
135
136static struct platform_device *lpc32xx_serial_devs[] __initdata = {
137 &serial_std_platform_device,
138};
139
140void __init lpc32xx_serial_init(void)
141{
142 u32 tmp, clkmodes = 0;
143 struct clk *clk;
144 unsigned int puart;
145 int i, j;
146
147 /* UART clocks are off, let clock driver manage them */
148 __raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL);
149
150 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
151 clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
152 if (!IS_ERR(clk)) {
153 clk_enable(clk);
154 serial_std_platform_data[i].uartclk =
155 clk_get_rate(clk);
156 }
157
158 /* Fall back on main osc rate if clock rate return fails */
159 if (serial_std_platform_data[i].uartclk == 0)
160 serial_std_platform_data[i].uartclk =
161 LPC32XX_MAIN_OSC_FREQ;
162
163 /* Setup UART clock modes for all UARTs, disable autoclock */
164 clkmodes |= uartinit_data[i].ck_mode_mask;
165
166 /* pre-UART clock divider set to 1 */
167 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
168 }
169
170 /* This needs to be done after all UART clocks are setup */
171 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
172 for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
173 /* Force a flush of the RX FIFOs to work around a HW bug */
174 puart = serial_std_platform_data[i].mapbase;
175 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
176 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
177 j = LPC32XX_SUART_FIFO_SIZE;
178 while (j--)
179 tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
180 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
181 }
182
183 /* Disable UART5->USB transparent mode or USB won't work */
184 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
185 tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
186 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
187
188 platform_add_devices(lpc32xx_serial_devs,
189 ARRAY_SIZE(lpc32xx_serial_devs));
190}
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
new file mode 100644
index 000000000000..374f9f07fe48
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -0,0 +1,151 @@
1/*
2 * arch/arm/mach-lpc32xx/suspend.S
3 *
4 * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
5 * Modified by Kevin Wells <kevin.wells@nxp.com>
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14#include <mach/platform.h>
15#include <mach/hardware.h>
16
17/* Using named register defines makes the code easier to follow */
18#define WORK1_REG r0
19#define WORK2_REG r1
20#define SAVED_HCLK_DIV_REG r2
21#define SAVED_HCLK_PLL_REG r3
22#define SAVED_DRAM_CLKCTRL_REG r4
23#define SAVED_PWR_CTRL_REG r5
24#define CLKPWRBASE_REG r6
25#define EMCBASE_REG r7
26
27#define LPC32XX_EMC_STATUS_OFFS 0x04
28#define LPC32XX_EMC_STATUS_BUSY 0x1
29#define LPC32XX_EMC_STATUS_SELF_RFSH 0x4
30
31#define LPC32XX_CLKPWR_PWR_CTRL_OFFS 0x44
32#define LPC32XX_CLKPWR_HCLK_DIV_OFFS 0x40
33#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
34
35#define CLKPWR_PCLK_DIV_MASK 0xFFFFFE7F
36
37 .text
38
39ENTRY(lpc32xx_sys_suspend)
40 @ Save a copy of the used registers in IRAM, r0 is corrupted
41 adr r0, tmp_stack_end
42 stmfd r0!, {r3 - r7, sp, lr}
43
44 @ Load a few common register addresses
45 adr WORK1_REG, reg_bases
46 ldr CLKPWRBASE_REG, [WORK1_REG, #0]
47 ldr EMCBASE_REG, [WORK1_REG, #4]
48
49 ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
50 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
51 orr WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
52
53 @ Wait for SDRAM busy status to go busy and then idle
54 @ This guarantees a small windows where DRAM isn't busy
551:
56 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
57 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
58 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
59 bne 1b @ Branch while idle
602:
61 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
62 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
63 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
64 beq 2b @ Branch until idle
65
66 @ Setup self-refresh with support for manual exit of
67 @ self-refresh mode
68 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
69 orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
70 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
71 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
72
73 @ Wait for self-refresh acknowledge, clocks to the DRAM device
74 @ will automatically stop on start of self-refresh
753:
76 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
77 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
78 cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
79 bne 3b @ Branch until self-refresh mode starts
80
81 @ Enter direct-run mode from run mode
82 bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
83 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
84
85 @ Safe disable of DRAM clock in EMC block, prevents DDR sync
86 @ issues on restart
87 ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
88 #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
89 and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
90 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
91
92 @ Save HCLK PLL state and disable HCLK PLL
93 ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
94 #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
95 bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
96 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
97
98 @ Enter stop mode until an enabled event occurs
99 orr WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
100 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
101 .rept 9
102 nop
103 .endr
104
105 @ Clear stop status
106 bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
107
108 @ Restore original HCLK PLL value and wait for PLL lock
109 str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
110 #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
1114:
112 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
113 and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
114 bne 4b
115
116 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
117 @ update yet. DRAM is still in self-refresh
118 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
119 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
120
121 @ Restore original DRAM clock mode to restore DRAM clocks
122 str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
123 #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
124
125 @ Clear self-refresh mode
126 orr WORK1_REG, SAVED_PWR_CTRL_REG,\
127 #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
128 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
129 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
130 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
131
132 @ Wait for EMC to clear self-refresh mode
1335:
134 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
135 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
136 bne 5b @ Branch until self-refresh has exited
137
138 @ restore regs and return
139 adr r0, tmp_stack
140 ldmfd r0!, {r3 - r7, sp, pc}
141
142reg_bases:
143 .long IO_ADDRESS(LPC32XX_CLK_PM_BASE)
144 .long IO_ADDRESS(LPC32XX_EMC_BASE)
145
146tmp_stack:
147 .long 0, 0, 0, 0, 0, 0, 0
148tmp_stack_end:
149
150ENTRY(lpc32xx_sys_suspend_sz)
151 .word . - lpc32xx_sys_suspend
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
new file mode 100644
index 000000000000..630dd4a74b26
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -0,0 +1,182 @@
1/*
2 * arch/arm/mach-lpc32xx/timer.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2009 - 2010 NXP Semiconductors
7 * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
8 * Ed Schouten <e.schouten@fontys.nl>
9 * Laurens Timmermans <l.timmermans@fontys.nl>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/time.h>
25#include <linux/err.h>
26#include <linux/clockchips.h>
27
28#include <asm/mach/time.h>
29
30#include <mach/hardware.h>
31#include <mach/platform.h>
32#include "common.h"
33
34static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
35{
36 return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
37}
38
39static struct clocksource lpc32xx_clksrc = {
40 .name = "lpc32xx_clksrc",
41 .shift = 24,
42 .rating = 300,
43 .read = lpc32xx_clksrc_read,
44 .mask = CLOCKSOURCE_MASK(32),
45 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
46};
47
48static int lpc32xx_clkevt_next_event(unsigned long delta,
49 struct clock_event_device *dev)
50{
51 __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
52 LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
53 __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
54 __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
55 LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
56
57 return 0;
58}
59
60static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
61 struct clock_event_device *dev)
62{
63 switch (mode) {
64 case CLOCK_EVT_MODE_PERIODIC:
65 WARN_ON(1);
66 break;
67
68 case CLOCK_EVT_MODE_ONESHOT:
69 case CLOCK_EVT_MODE_SHUTDOWN:
70 /*
71 * Disable the timer. When using oneshot, we must also
72 * disable the timer to wait for the first call to
73 * set_next_event().
74 */
75 __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
76 break;
77
78 case CLOCK_EVT_MODE_UNUSED:
79 case CLOCK_EVT_MODE_RESUME:
80 break;
81 }
82}
83
84static struct clock_event_device lpc32xx_clkevt = {
85 .name = "lpc32xx_clkevt",
86 .features = CLOCK_EVT_FEAT_ONESHOT,
87 .shift = 32,
88 .rating = 300,
89 .set_next_event = lpc32xx_clkevt_next_event,
90 .set_mode = lpc32xx_clkevt_mode,
91};
92
93static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
94{
95 struct clock_event_device *evt = &lpc32xx_clkevt;
96
97 /* Clear match */
98 __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
99 LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
100
101 evt->event_handler(evt);
102
103 return IRQ_HANDLED;
104}
105
106static struct irqaction lpc32xx_timer_irq = {
107 .name = "LPC32XX Timer Tick",
108 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
109 .handler = lpc32xx_timer_interrupt,
110};
111
112/*
113 * The clock management driver isn't initialized at this point, so the
114 * clocks need to be enabled here manually and then tagged as used in
115 * the clock driver initialization
116 */
117static void __init lpc32xx_timer_init(void)
118{
119 u32 clkrate, pllreg;
120
121 /* Enable timer clock */
122 __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
123 LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
124 LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
125
126 /*
127 * The clock driver isn't initialized at this point. So determine if
128 * the SYSCLK is driven from the PLL397 or main oscillator and then use
129 * it to compute the PLL frequency and the PCLK divider to get the base
130 * timer rates. This rate is needed to compute the tick rate.
131 */
132 if (clk_is_sysclk_mainosc() != 0)
133 clkrate = LPC32XX_MAIN_OSC_FREQ;
134 else
135 clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
136
137 /* Get ARM HCLKPLL register and convert it into a frequency */
138 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
139 clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
140
141 /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
142 clkrate = clkrate / clk_get_pclk_div();
143
144 /* Initial timer setup */
145 __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
146 __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
147 LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
148 __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
149 __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
150 LCP32XX_TIMER_CNTR_MCR_STOP(0) |
151 LCP32XX_TIMER_CNTR_MCR_RESET(0),
152 LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
153
154 /* Setup tick interrupt */
155 setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
156
157 /* Setup the clockevent structure. */
158 lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
159 lpc32xx_clkevt.shift);
160 lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
161 &lpc32xx_clkevt);
162 lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
163 &lpc32xx_clkevt) + 1;
164 lpc32xx_clkevt.cpumask = cpumask_of(0);
165 clockevents_register_device(&lpc32xx_clkevt);
166
167 /* Use timer1 as clock source. */
168 __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
169 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
170 __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
171 __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
172 __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
173 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
174 lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate,
175 lpc32xx_clksrc.shift);
176 clocksource_register(&lpc32xx_clksrc);
177}
178
179struct sys_timer lpc32xx_timer = {
180 .init = &lpc32xx_timer_init,
181};
182
diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
index 0859336a8e6d..5c934bdb7158 100644
--- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
@@ -8,6 +8,7 @@
8 * the Free Software Foundation. 8 * the Free Software Foundation.
9 */ 9 */
10#include <mach/hardware.h> 10#include <mach/hardware.h>
11#include <asm/memory.h>
11 12
12#include <mach/regs-board-a9m9750dev.h> 13#include <mach/regs-board-a9m9750dev.h>
13 14
diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
index 1b12d324b087..770a68c46e81 100644
--- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h
+++ b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
@@ -20,50 +20,49 @@ static void putc_dummy(char c, void __iomem *base)
20 /* nothing */ 20 /* nothing */
21} 21}
22 22
23static int timeout;
24
23static void putc_ns9360(char c, void __iomem *base) 25static void putc_ns9360(char c, void __iomem *base)
24{ 26{
25 static int t = 0x10000;
26 do { 27 do {
27 if (t) 28 if (timeout)
28 --t; 29 --timeout;
29 30
30 if (__raw_readl(base + 8) & (1 << 3)) { 31 if (__raw_readl(base + 8) & (1 << 3)) {
31 __raw_writeb(c, base + 16); 32 __raw_writeb(c, base + 16);
32 t = 0x10000; 33 timeout = 0x10000;
33 break; 34 break;
34 } 35 }
35 } while (t); 36 } while (timeout);
36} 37}
37 38
38static void putc_a9m9750dev(char c, void __iomem *base) 39static void putc_a9m9750dev(char c, void __iomem *base)
39{ 40{
40 static int t = 0x10000;
41 do { 41 do {
42 if (t) 42 if (timeout)
43 --t; 43 --timeout;
44 44
45 if (__raw_readb(base + 5) & (1 << 5)) { 45 if (__raw_readb(base + 5) & (1 << 5)) {
46 __raw_writeb(c, base); 46 __raw_writeb(c, base);
47 t = 0x10000; 47 timeout = 0x10000;
48 break; 48 break;
49 } 49 }
50 } while (t); 50 } while (timeout);
51 51
52} 52}
53 53
54static void putc_ns921x(char c, void __iomem *base) 54static void putc_ns921x(char c, void __iomem *base)
55{ 55{
56 static int t = 0x10000;
57 do { 56 do {
58 if (t) 57 if (timeout)
59 --t; 58 --timeout;
60 59
61 if (!(__raw_readl(base) & (1 << 11))) { 60 if (!(__raw_readl(base) & (1 << 11))) {
62 __raw_writeb(c, base + 0x0028); 61 __raw_writeb(c, base + 0x0028);
63 t = 0x10000; 62 timeout = 0x10000;
64 break; 63 break;
65 } 64 }
66 } while (t); 65 } while (timeout);
67} 66}
68 67
69#define MSCS __REG(0xA0900184) 68#define MSCS __REG(0xA0900184)
@@ -89,6 +88,7 @@ static void putc_ns921x(char c, void __iomem *base)
89 88
90static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base) 89static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
91{ 90{
91 timeout = 0x10000;
92 if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) { 92 if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
93 /* ns9360 or ns9750 */ 93 /* ns9360 or ns9750 */
94 if (NS9360_UART_ENABLED(NS9360_UARTA)) { 94 if (NS9360_UART_ENABLED(NS9360_UARTA)) {
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index abdf321c2d41..03483920ed6e 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -175,6 +175,10 @@ static void __init rx51_add_gpio_keys(void)
175#endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */ 175#endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */
176 176
177static int board_keymap[] = { 177static int board_keymap[] = {
178 /*
179 * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row
180 * connected to the ground" matrix state.
181 */
178 KEY(0, 0, KEY_Q), 182 KEY(0, 0, KEY_Q),
179 KEY(0, 1, KEY_O), 183 KEY(0, 1, KEY_O),
180 KEY(0, 2, KEY_P), 184 KEY(0, 2, KEY_P),
@@ -182,6 +186,7 @@ static int board_keymap[] = {
182 KEY(0, 4, KEY_BACKSPACE), 186 KEY(0, 4, KEY_BACKSPACE),
183 KEY(0, 6, KEY_A), 187 KEY(0, 6, KEY_A),
184 KEY(0, 7, KEY_S), 188 KEY(0, 7, KEY_S),
189
185 KEY(1, 0, KEY_W), 190 KEY(1, 0, KEY_W),
186 KEY(1, 1, KEY_D), 191 KEY(1, 1, KEY_D),
187 KEY(1, 2, KEY_F), 192 KEY(1, 2, KEY_F),
@@ -190,6 +195,7 @@ static int board_keymap[] = {
190 KEY(1, 5, KEY_J), 195 KEY(1, 5, KEY_J),
191 KEY(1, 6, KEY_K), 196 KEY(1, 6, KEY_K),
192 KEY(1, 7, KEY_L), 197 KEY(1, 7, KEY_L),
198
193 KEY(2, 0, KEY_E), 199 KEY(2, 0, KEY_E),
194 KEY(2, 1, KEY_DOT), 200 KEY(2, 1, KEY_DOT),
195 KEY(2, 2, KEY_UP), 201 KEY(2, 2, KEY_UP),
@@ -197,6 +203,8 @@ static int board_keymap[] = {
197 KEY(2, 5, KEY_Z), 203 KEY(2, 5, KEY_Z),
198 KEY(2, 6, KEY_X), 204 KEY(2, 6, KEY_X),
199 KEY(2, 7, KEY_C), 205 KEY(2, 7, KEY_C),
206 KEY(2, 8, KEY_F9),
207
200 KEY(3, 0, KEY_R), 208 KEY(3, 0, KEY_R),
201 KEY(3, 1, KEY_V), 209 KEY(3, 1, KEY_V),
202 KEY(3, 2, KEY_B), 210 KEY(3, 2, KEY_B),
@@ -205,20 +213,23 @@ static int board_keymap[] = {
205 KEY(3, 5, KEY_SPACE), 213 KEY(3, 5, KEY_SPACE),
206 KEY(3, 6, KEY_SPACE), 214 KEY(3, 6, KEY_SPACE),
207 KEY(3, 7, KEY_LEFT), 215 KEY(3, 7, KEY_LEFT),
216
208 KEY(4, 0, KEY_T), 217 KEY(4, 0, KEY_T),
209 KEY(4, 1, KEY_DOWN), 218 KEY(4, 1, KEY_DOWN),
210 KEY(4, 2, KEY_RIGHT), 219 KEY(4, 2, KEY_RIGHT),
211 KEY(4, 4, KEY_LEFTCTRL), 220 KEY(4, 4, KEY_LEFTCTRL),
212 KEY(4, 5, KEY_RIGHTALT), 221 KEY(4, 5, KEY_RIGHTALT),
213 KEY(4, 6, KEY_LEFTSHIFT), 222 KEY(4, 6, KEY_LEFTSHIFT),
223 KEY(4, 8, KEY_F10),
224
214 KEY(5, 0, KEY_Y), 225 KEY(5, 0, KEY_Y),
226 KEY(5, 8, KEY_F11),
227
215 KEY(6, 0, KEY_U), 228 KEY(6, 0, KEY_U),
229
216 KEY(7, 0, KEY_I), 230 KEY(7, 0, KEY_I),
217 KEY(7, 1, KEY_F7), 231 KEY(7, 1, KEY_F7),
218 KEY(7, 2, KEY_F8), 232 KEY(7, 2, KEY_F8),
219 KEY(0xff, 2, KEY_F9),
220 KEY(0xff, 4, KEY_F10),
221 KEY(0xff, 5, KEY_F11),
222}; 233};
223 234
224static struct matrix_keymap_data board_map_data = { 235static struct matrix_keymap_data board_map_data = {
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index 45c23fd6df31..40b6ac2de876 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -26,6 +26,7 @@
26#include <mach/colibri.h> 26#include <mach/colibri.h>
27#include <mach/ohci.h> 27#include <mach/ohci.h>
28#include <mach/pxafb.h> 28#include <mach/pxafb.h>
29#include <mach/audio.h>
29 30
30#include "generic.h" 31#include "generic.h"
31#include "devices.h" 32#include "devices.h"
@@ -145,7 +146,7 @@ static void __init colibri_pxa300_init_lcd(void)
145static inline void colibri_pxa300_init_lcd(void) {} 146static inline void colibri_pxa300_init_lcd(void) {}
146#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */ 147#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
147 148
148#if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE) 149#if defined(CONFIG_SND_AC97_CODEC) || defined(CONFIG_SND_AC97_CODEC_MODULE)
149static mfp_cfg_t colibri_pxa310_ac97_pin_config[] __initdata = { 150static mfp_cfg_t colibri_pxa310_ac97_pin_config[] __initdata = {
150 GPIO24_AC97_SYSCLK, 151 GPIO24_AC97_SYSCLK,
151 GPIO23_AC97_nACRESET, 152 GPIO23_AC97_nACRESET,
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 3d1dcb9ac08f..51ffa6afb675 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -446,7 +446,7 @@ static struct platform_device corgiled_device = {
446static struct pxamci_platform_data corgi_mci_platform_data = { 446static struct pxamci_platform_data corgi_mci_platform_data = {
447 .detect_delay_ms = 250, 447 .detect_delay_ms = 250,
448 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, 448 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
449 .gpio_card_detect = -1, 449 .gpio_card_detect = CORGI_GPIO_nSD_DETECT,
450 .gpio_card_ro = CORGI_GPIO_nSD_WP, 450 .gpio_card_ro = CORGI_GPIO_nSD_WP,
451 .gpio_power = CORGI_GPIO_SD_PWR, 451 .gpio_power = CORGI_GPIO_SD_PWR,
452}; 452};
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 9e4d9816726a..268a9bc6be8a 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -256,13 +256,9 @@ static void init_sdram_rows(void)
256 256
257static u32 mdrefr_dri(unsigned int freq) 257static u32 mdrefr_dri(unsigned int freq)
258{ 258{
259 u32 dri = 0; 259 u32 interval = freq * SDRAM_TREF / sdram_rows;
260 260
261 if (cpu_is_pxa25x()) 261 return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
262 dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
263 if (cpu_is_pxa27x())
264 dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
265 return dri;
266} 262}
267 263
268/* find a valid frequency point */ 264/* find a valid frequency point */
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 0af36177ff08..c059dac02b61 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -41,10 +41,10 @@ void pxa27x_clear_otgph(void)
41EXPORT_SYMBOL(pxa27x_clear_otgph); 41EXPORT_SYMBOL(pxa27x_clear_otgph);
42 42
43static unsigned long ac97_reset_config[] = { 43static unsigned long ac97_reset_config[] = {
44 GPIO95_AC97_nRESET,
45 GPIO95_GPIO,
46 GPIO113_AC97_nRESET,
47 GPIO113_GPIO, 44 GPIO113_GPIO,
45 GPIO113_AC97_nRESET,
46 GPIO95_GPIO,
47 GPIO95_AC97_nRESET,
48}; 48};
49 49
50void pxa27x_assert_ac97reset(int reset_gpio, int on) 50void pxa27x_assert_ac97reset(int reset_gpio, int on)
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index 50f071c5bf4d..5ea24d4d1ba6 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -20,6 +20,9 @@
20 strb \rd, [\rx] 20 strb \rd, [\rx]
21 .endm 21 .endm
22 22
23 .macro waituart,rd,rx
24 .endm
25
23 .macro busyuart,rd,rx 26 .macro busyuart,rd,rx
24 mov \rd, #0 27 mov \rd, #0
251001: add \rd, \rd, #1 281001: add \rd, \rd, #1
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 642207e18198..83c56324a472 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -93,7 +93,7 @@ static struct clk_lookup nuc900_clkregs[] = {
93 DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL), 93 DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
94 DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL), 94 DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
95 DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL), 95 DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
96 DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL), 96 DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL),
97 DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL), 97 DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
98 DEF_CLKLOOK(&clk_ext, NULL, "ext"), 98 DEF_CLKLOOK(&clk_ext, NULL, "ext"),
99 DEF_CLKLOOK(&clk_timer0, NULL, "timer0"), 99 DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 1670734b7e51..37fa593884ee 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -17,8 +17,8 @@
17 .macro addruart, rx 17 .macro addruart, rx
18 mrc p15, 0, \rx, c1, c0 18 mrc p15, 0, \rx, c1, c0
19 tst \rx, #1 @ MMU enabled? 19 tst \rx, #1 @ MMU enabled?
20 moveq \rx, =SPEAR_DBG_UART_BASE @ Physical base 20 moveq \rx, #SPEAR_DBG_UART_BASE @ Physical base
21 movne \rx, =VA_SPEAR_DBG_UART_BASE @ Virtual base 21 movne \rx, #VA_SPEAR_DBG_UART_BASE @ Virtual base
22 .endm 22 .endm
23 23
24 .macro senduart, rd, rx 24 .macro senduart, rd, rx
diff --git a/arch/avr32/include/asm/ioctls.h b/arch/avr32/include/asm/ioctls.h
index 0cf2c0a4502b..e6ac0b661076 100644
--- a/arch/avr32/include/asm/ioctls.h
+++ b/arch/avr32/include/asm/ioctls.h
@@ -54,6 +54,9 @@
54#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ 54#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
55#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ 55#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
56 56
57#define TIOCGRS485 0x542E
58#define TIOCSRS485 0x542F
59
57#define FIONCLEX 0x5450 60#define FIONCLEX 0x5450
58#define FIOCLEX 0x5451 61#define FIOCLEX 0x5451
59#define FIOASYNC 0x5452 62#define FIOASYNC 0x5452
diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
index c7f25bb1d068..61740201b311 100644
--- a/arch/avr32/mach-at32ap/include/mach/board.h
+++ b/arch/avr32/mach-at32ap/include/mach/board.h
@@ -5,6 +5,7 @@
5#define __ASM_ARCH_BOARD_H 5#define __ASM_ARCH_BOARD_H
6 6
7#include <linux/types.h> 7#include <linux/types.h>
8#include <linux/serial.h>
8 9
9#define GPIO_PIN_NONE (-1) 10#define GPIO_PIN_NONE (-1)
10 11
@@ -35,6 +36,7 @@ struct atmel_uart_data {
35 short use_dma_tx; /* use transmit DMA? */ 36 short use_dma_tx; /* use transmit DMA? */
36 short use_dma_rx; /* use receive DMA? */ 37 short use_dma_rx; /* use receive DMA? */
37 void __iomem *regs; /* virtual base address, if any */ 38 void __iomem *regs; /* virtual base address, if any */
39 struct serial_rs485 rs485; /* rs485 settings */
38}; 40};
39void at32_map_usart(unsigned int hw_id, unsigned int line, int flags); 41void at32_map_usart(unsigned int hw_id, unsigned int line, int flags);
40struct platform_device *at32_add_device_usart(unsigned int id); 42struct platform_device *at32_add_device_usart(unsigned int id);
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 2580e77624d2..f9e5622ebc95 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -435,20 +435,21 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
435static int __init au1xxx_platform_init(void) 435static int __init au1xxx_platform_init(void)
436{ 436{
437 unsigned int uartclk = get_au1x00_uart_baud_base() * 16; 437 unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
438 int i; 438 int err, i;
439 439
440 /* Fill up uartclk. */ 440 /* Fill up uartclk. */
441 for (i = 0; au1x00_uart_data[i].flags; i++) 441 for (i = 0; au1x00_uart_data[i].flags; i++)
442 au1x00_uart_data[i].uartclk = uartclk; 442 au1x00_uart_data[i].uartclk = uartclk;
443 443
444 err = platform_add_devices(au1xxx_platform_devices,
445 ARRAY_SIZE(au1xxx_platform_devices));
444#ifndef CONFIG_SOC_AU1100 446#ifndef CONFIG_SOC_AU1100
445 /* Register second MAC if enabled in pinfunc */ 447 /* Register second MAC if enabled in pinfunc */
446 if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) 448 if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
447 platform_device_register(&au1xxx_eth1_device); 449 platform_device_register(&au1xxx_eth1_device);
448#endif 450#endif
449 451
450 return platform_add_devices(au1xxx_platform_devices, 452 return err;
451 ARRAY_SIZE(au1xxx_platform_devices));
452} 453}
453 454
454arch_initcall(au1xxx_platform_init); 455arch_initcall(au1xxx_platform_init);
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index a9f0336e1f1f..52d883d37dd7 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -67,8 +67,6 @@ static void mtx1_power_off(void)
67 67
68void __init board_setup(void) 68void __init board_setup(void)
69{ 69{
70 alchemy_gpio2_enable();
71
72#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 70#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
73 /* Enable USB power switch */ 71 /* Enable USB power switch */
74 alchemy_gpio_direction_output(204, 0); 72 alchemy_gpio_direction_output(204, 0);
@@ -117,11 +115,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
117 115
118 if (assert && devsel != 0) 116 if (assert && devsel != 0)
119 /* Suppress signal to Cardbus */ 117 /* Suppress signal to Cardbus */
120 gpio_set_value(1, 0); /* set EXT_IO3 OFF */ 118 alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
121 else 119 else
122 gpio_set_value(1, 1); /* set EXT_IO3 ON */ 120 alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
123 121
124 au_sync_udelay(1); 122 udelay(1);
125 return 1; 123 return 1;
126} 124}
127 125
diff --git a/arch/mips/bcm63xx/dev-enet.c b/arch/mips/bcm63xx/dev-enet.c
index 9f544badd0b4..39c23366c5c7 100644
--- a/arch/mips/bcm63xx/dev-enet.c
+++ b/arch/mips/bcm63xx/dev-enet.c
@@ -104,6 +104,9 @@ int __init bcm63xx_enet_register(int unit,
104 if (unit > 1) 104 if (unit > 1)
105 return -ENODEV; 105 return -ENODEV;
106 106
107 if (unit == 1 && BCMCPU_IS_6338())
108 return -ENODEV;
109
107 if (!shared_device_registered) { 110 if (!shared_device_registered) {
108 shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA); 111 shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
109 shared_res[0].end = shared_res[0].start; 112 shared_res[0].end = shared_res[0].start;
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 59dc0c7ef733..c63c56bfd184 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -434,7 +434,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
434 __asm__ __volatile__( 434 __asm__ __volatile__(
435 " .set mips3 \n" 435 " .set mips3 \n"
436 "1: lld %0, %1 # atomic64_add \n" 436 "1: lld %0, %1 # atomic64_add \n"
437 " addu %0, %2 \n" 437 " daddu %0, %2 \n"
438 " scd %0, %1 \n" 438 " scd %0, %1 \n"
439 " beqzl %0, 1b \n" 439 " beqzl %0, 1b \n"
440 " .set mips0 \n" 440 " .set mips0 \n"
@@ -446,7 +446,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
446 __asm__ __volatile__( 446 __asm__ __volatile__(
447 " .set mips3 \n" 447 " .set mips3 \n"
448 "1: lld %0, %1 # atomic64_add \n" 448 "1: lld %0, %1 # atomic64_add \n"
449 " addu %0, %2 \n" 449 " daddu %0, %2 \n"
450 " scd %0, %1 \n" 450 " scd %0, %1 \n"
451 " beqz %0, 2f \n" 451 " beqz %0, 2f \n"
452 " .subsection 2 \n" 452 " .subsection 2 \n"
@@ -479,7 +479,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
479 __asm__ __volatile__( 479 __asm__ __volatile__(
480 " .set mips3 \n" 480 " .set mips3 \n"
481 "1: lld %0, %1 # atomic64_sub \n" 481 "1: lld %0, %1 # atomic64_sub \n"
482 " subu %0, %2 \n" 482 " dsubu %0, %2 \n"
483 " scd %0, %1 \n" 483 " scd %0, %1 \n"
484 " beqzl %0, 1b \n" 484 " beqzl %0, 1b \n"
485 " .set mips0 \n" 485 " .set mips0 \n"
@@ -491,7 +491,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
491 __asm__ __volatile__( 491 __asm__ __volatile__(
492 " .set mips3 \n" 492 " .set mips3 \n"
493 "1: lld %0, %1 # atomic64_sub \n" 493 "1: lld %0, %1 # atomic64_sub \n"
494 " subu %0, %2 \n" 494 " dsubu %0, %2 \n"
495 " scd %0, %1 \n" 495 " scd %0, %1 \n"
496 " beqz %0, 2f \n" 496 " beqz %0, 2f \n"
497 " .subsection 2 \n" 497 " .subsection 2 \n"
@@ -524,10 +524,10 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
524 __asm__ __volatile__( 524 __asm__ __volatile__(
525 " .set mips3 \n" 525 " .set mips3 \n"
526 "1: lld %1, %2 # atomic64_add_return \n" 526 "1: lld %1, %2 # atomic64_add_return \n"
527 " addu %0, %1, %3 \n" 527 " daddu %0, %1, %3 \n"
528 " scd %0, %2 \n" 528 " scd %0, %2 \n"
529 " beqzl %0, 1b \n" 529 " beqzl %0, 1b \n"
530 " addu %0, %1, %3 \n" 530 " daddu %0, %1, %3 \n"
531 " .set mips0 \n" 531 " .set mips0 \n"
532 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 532 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
533 : "Ir" (i), "m" (v->counter) 533 : "Ir" (i), "m" (v->counter)
@@ -538,10 +538,10 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
538 __asm__ __volatile__( 538 __asm__ __volatile__(
539 " .set mips3 \n" 539 " .set mips3 \n"
540 "1: lld %1, %2 # atomic64_add_return \n" 540 "1: lld %1, %2 # atomic64_add_return \n"
541 " addu %0, %1, %3 \n" 541 " daddu %0, %1, %3 \n"
542 " scd %0, %2 \n" 542 " scd %0, %2 \n"
543 " beqz %0, 2f \n" 543 " beqz %0, 2f \n"
544 " addu %0, %1, %3 \n" 544 " daddu %0, %1, %3 \n"
545 " .subsection 2 \n" 545 " .subsection 2 \n"
546 "2: b 1b \n" 546 "2: b 1b \n"
547 " .previous \n" 547 " .previous \n"
@@ -576,10 +576,10 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
576 __asm__ __volatile__( 576 __asm__ __volatile__(
577 " .set mips3 \n" 577 " .set mips3 \n"
578 "1: lld %1, %2 # atomic64_sub_return \n" 578 "1: lld %1, %2 # atomic64_sub_return \n"
579 " subu %0, %1, %3 \n" 579 " dsubu %0, %1, %3 \n"
580 " scd %0, %2 \n" 580 " scd %0, %2 \n"
581 " beqzl %0, 1b \n" 581 " beqzl %0, 1b \n"
582 " subu %0, %1, %3 \n" 582 " dsubu %0, %1, %3 \n"
583 " .set mips0 \n" 583 " .set mips0 \n"
584 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 584 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
585 : "Ir" (i), "m" (v->counter) 585 : "Ir" (i), "m" (v->counter)
@@ -590,10 +590,10 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
590 __asm__ __volatile__( 590 __asm__ __volatile__(
591 " .set mips3 \n" 591 " .set mips3 \n"
592 "1: lld %1, %2 # atomic64_sub_return \n" 592 "1: lld %1, %2 # atomic64_sub_return \n"
593 " subu %0, %1, %3 \n" 593 " dsubu %0, %1, %3 \n"
594 " scd %0, %2 \n" 594 " scd %0, %2 \n"
595 " beqz %0, 2f \n" 595 " beqz %0, 2f \n"
596 " subu %0, %1, %3 \n" 596 " dsubu %0, %1, %3 \n"
597 " .subsection 2 \n" 597 " .subsection 2 \n"
598 "2: b 1b \n" 598 "2: b 1b \n"
599 " .previous \n" 599 " .previous \n"
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 1b5a6648eb86..baa318a59c97 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -984,16 +984,17 @@
984#define __NR_perf_event_open (__NR_Linux + 296) 984#define __NR_perf_event_open (__NR_Linux + 296)
985#define __NR_accept4 (__NR_Linux + 297) 985#define __NR_accept4 (__NR_Linux + 297)
986#define __NR_recvmmsg (__NR_Linux + 298) 986#define __NR_recvmmsg (__NR_Linux + 298)
987#define __NR_getdents64 (__NR_Linux + 299)
987 988
988/* 989/*
989 * Offset of the last N32 flavoured syscall 990 * Offset of the last N32 flavoured syscall
990 */ 991 */
991#define __NR_Linux_syscalls 298 992#define __NR_Linux_syscalls 299
992 993
993#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 994#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
994 995
995#define __NR_N32_Linux 6000 996#define __NR_N32_Linux 6000
996#define __NR_N32_Linux_syscalls 298 997#define __NR_N32_Linux_syscalls 299
997 998
998#ifdef __KERNEL__ 999#ifdef __KERNEL__
999 1000
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index a5297e2a353a..a4faceea9d88 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -419,4 +419,5 @@ EXPORT(sysn32_call_table)
419 PTR sys_perf_event_open 419 PTR sys_perf_event_open
420 PTR sys_accept4 420 PTR sys_accept4
421 PTR compat_sys_recvmmsg 421 PTR compat_sys_recvmmsg
422 PTR sys_getdents
422 .size sysn32_call_table,.-sysn32_call_table 423 .size sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c
index b773c1112b14..e5cdfd603f8f 100644
--- a/arch/mips/kernel/vdso.c
+++ b/arch/mips/kernel/vdso.c
@@ -61,11 +61,9 @@ static int __init init_vdso(void)
61 61
62 vunmap(vdso); 62 vunmap(vdso);
63 63
64 pr_notice("init_vdso successfull\n");
65
66 return 0; 64 return 0;
67} 65}
68device_initcall(init_vdso); 66subsys_initcall(init_vdso);
69 67
70static unsigned long vdso_addr(unsigned long start) 68static unsigned long vdso_addr(unsigned long start)
71{ 69{
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
index 2fbfa1a8c3a9..bf80921f2f56 100644
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/mti-malta/malta-pci.c
@@ -247,6 +247,8 @@ void __init mips_pcibios_init(void)
247 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ 247 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
248 ioport_resource.end = controller->io_resource->end; 248 ioport_resource.end = controller->io_resource->end;
249 249
250 controller->io_map_base = mips_io_port_base;
251
250 register_pci_controller(controller); 252 register_pci_controller(controller);
251} 253}
252 254
diff --git a/arch/mips/nxp/pnx8550/common/pci.c b/arch/mips/nxp/pnx8550/common/pci.c
index eee4f3dfc410..98e86ddb86cc 100644
--- a/arch/mips/nxp/pnx8550/common/pci.c
+++ b/arch/mips/nxp/pnx8550/common/pci.c
@@ -44,6 +44,7 @@ extern struct pci_ops pnx8550_pci_ops;
44 44
45static struct pci_controller pnx8550_controller = { 45static struct pci_controller pnx8550_controller = {
46 .pci_ops = &pnx8550_pci_ops, 46 .pci_ops = &pnx8550_pci_ops,
47 .io_map_base = PNX8550_PORT_BASE,
47 .io_resource = &pci_io_resource, 48 .io_resource = &pci_io_resource,
48 .mem_resource = &pci_mem_resource, 49 .mem_resource = &pci_mem_resource,
49}; 50};
diff --git a/arch/mips/nxp/pnx8550/common/setup.c b/arch/mips/nxp/pnx8550/common/setup.c
index 2aed50fef10f..64246c9c875c 100644
--- a/arch/mips/nxp/pnx8550/common/setup.c
+++ b/arch/mips/nxp/pnx8550/common/setup.c
@@ -113,7 +113,7 @@ void __init plat_mem_setup(void)
113 PNX8550_GLB2_ENAB_INTA_O = 0; 113 PNX8550_GLB2_ENAB_INTA_O = 0;
114 114
115 /* IO/MEM resources. */ 115 /* IO/MEM resources. */
116 set_io_port_base(KSEG1); 116 set_io_port_base(PNX8550_PORT_BASE);
117 ioport_resource.start = 0; 117 ioport_resource.start = 0;
118 ioport_resource.end = ~0; 118 ioport_resource.end = ~0;
119 iomem_resource.start = 0; 119 iomem_resource.start = 0;
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 04b31478a6d7..b7c03d80c88c 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -944,6 +944,7 @@ static struct pci_controller msp_pci_controller = {
944 .pci_ops = &msp_pci_ops, 944 .pci_ops = &msp_pci_ops,
945 .mem_resource = &pci_mem_resource, 945 .mem_resource = &pci_mem_resource,
946 .mem_offset = 0, 946 .mem_offset = 0,
947 .io_map_base = MSP_PCI_IOSPACE_BASE,
947 .io_resource = &pci_io_resource, 948 .io_resource = &pci_io_resource,
948 .io_offset = 0 949 .io_offset = 0
949}; 950};
diff --git a/arch/mips/pci/pci-yosemite.c b/arch/mips/pci/pci-yosemite.c
index 0357946f30e6..cf5e1a25cb7d 100644
--- a/arch/mips/pci/pci-yosemite.c
+++ b/arch/mips/pci/pci-yosemite.c
@@ -54,6 +54,7 @@ static int __init pmc_yosemite_setup(void)
54 panic(ioremap_failed); 54 panic(ioremap_failed);
55 55
56 set_io_port_base(io_v_base); 56 set_io_port_base(io_v_base);
57 py_controller.io_map_base = io_v_base;
57 TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1); 58 TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
58 59
59 ioport_resource.end = TITAN_IO_SIZE - 1; 60 ioport_resource.end = TITAN_IO_SIZE - 1;
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index 8ee77887306a..9ec523e4dd06 100644
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -472,6 +472,9 @@ void __init configure_platform(void)
472 * it*/ 472 * it*/
473 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; 473 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
474 474
475 /* Cronus and Cronus Lite have the same register map */
476 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
477
475 /* ASIC version will determine if this is a real CronusLite or 478 /* ASIC version will determine if this is a real CronusLite or
476 * Castrati(Cronus) */ 479 * Castrati(Cronus) */
477 chipversion = asic_read(chipver3) << 24; 480 chipversion = asic_read(chipver3) << 24;
@@ -484,8 +487,6 @@ void __init configure_platform(void)
484 else 487 else
485 asic = ASIC_CRONUSLITE; 488 asic = ASIC_CRONUSLITE;
486 489
487 /* Cronus and Cronus Lite have the same register map */
488 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
489 gp_resources = non_dvr_cronuslite_resources; 490 gp_resources = non_dvr_cronuslite_resources;
490 pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, " 491 pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
491 "chipversion=0x%08X\n", 492 "chipversion=0x%08X\n",
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index 2a9cd74a841e..076327f2eff7 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -8,9 +8,9 @@
8 * On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory 8 * On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory
9 * and therefore we can only deal with memory within this range 9 * and therefore we can only deal with memory within this range
10 */ 10 */
11#define KEXEC_SOURCE_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL) 11#define KEXEC_SOURCE_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL - 1)
12#define KEXEC_DESTINATION_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL) 12#define KEXEC_DESTINATION_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL - 1)
13#define KEXEC_CONTROL_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL) 13#define KEXEC_CONTROL_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL - 1)
14 14
15#else 15#else
16 16
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 2102b214a87c..0e398cfee2c8 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -250,7 +250,9 @@ extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
250int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, 250int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
251 pte_t *ptep, unsigned long trap, int local, int ssize, 251 pte_t *ptep, unsigned long trap, int local, int ssize,
252 unsigned int shift, unsigned int mmu_psize); 252 unsigned int shift, unsigned int mmu_psize);
253 253extern void hash_failure_debug(unsigned long ea, unsigned long access,
254 unsigned long vsid, unsigned long trap,
255 int ssize, int psize, unsigned long pte);
254extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, 256extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
255 unsigned long pstart, unsigned long prot, 257 unsigned long pstart, unsigned long prot,
256 int psize, int ssize); 258 int psize, int ssize);
diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c
index 369872f6cf78..babcceecd2ea 100644
--- a/arch/powerpc/kernel/perf_event_fsl_emb.c
+++ b/arch/powerpc/kernel/perf_event_fsl_emb.c
@@ -566,9 +566,9 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
566 * Finally record data if requested. 566 * Finally record data if requested.
567 */ 567 */
568 if (record) { 568 if (record) {
569 struct perf_sample_data data = { 569 struct perf_sample_data data;
570 .period = event->hw.last_period, 570
571 }; 571 perf_sample_data_init(&data, 0);
572 572
573 if (perf_event_overflow(event, nmi, &data, regs)) { 573 if (perf_event_overflow(event, nmi, &data, regs)) {
574 /* 574 /*
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 9d3953983fb7..fed9bf6187d1 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -414,7 +414,7 @@ static int __init early_init_dt_scan_drconf_memory(unsigned long node)
414 u64 base, size, memblock_size; 414 u64 base, size, memblock_size;
415 unsigned int is_kexec_kdump = 0, rngs; 415 unsigned int is_kexec_kdump = 0, rngs;
416 416
417 ls = of_get_flat_dt_prop(node, "ibm,memblock-size", &l); 417 ls = of_get_flat_dt_prop(node, "ibm,lmb-size", &l);
418 if (ls == NULL || l < dt_root_size_cells * sizeof(__be32)) 418 if (ls == NULL || l < dt_root_size_cells * sizeof(__be32))
419 return 0; 419 return 0;
420 memblock_size = dt_mem_next_cell(dt_root_size_cells, &ls); 420 memblock_size = dt_mem_next_cell(dt_root_size_cells, &ls);
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index a719f53921a5..3079f6b44cf5 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -68,9 +68,6 @@ _GLOBAL(__hash_page_4K)
68 std r8,STK_PARM(r8)(r1) 68 std r8,STK_PARM(r8)(r1)
69 std r9,STK_PARM(r9)(r1) 69 std r9,STK_PARM(r9)(r1)
70 70
71 /* Add _PAGE_PRESENT to access */
72 ori r4,r4,_PAGE_PRESENT
73
74 /* Save non-volatile registers. 71 /* Save non-volatile registers.
75 * r31 will hold "old PTE" 72 * r31 will hold "old PTE"
76 * r30 is "new PTE" 73 * r30 is "new PTE"
@@ -347,9 +344,6 @@ _GLOBAL(__hash_page_4K)
347 std r8,STK_PARM(r8)(r1) 344 std r8,STK_PARM(r8)(r1)
348 std r9,STK_PARM(r9)(r1) 345 std r9,STK_PARM(r9)(r1)
349 346
350 /* Add _PAGE_PRESENT to access */
351 ori r4,r4,_PAGE_PRESENT
352
353 /* Save non-volatile registers. 347 /* Save non-volatile registers.
354 * r31 will hold "old PTE" 348 * r31 will hold "old PTE"
355 * r30 is "new PTE" 349 * r30 is "new PTE"
@@ -687,9 +681,6 @@ _GLOBAL(__hash_page_64K)
687 std r8,STK_PARM(r8)(r1) 681 std r8,STK_PARM(r8)(r1)
688 std r9,STK_PARM(r9)(r1) 682 std r9,STK_PARM(r9)(r1)
689 683
690 /* Add _PAGE_PRESENT to access */
691 ori r4,r4,_PAGE_PRESENT
692
693 /* Save non-volatile registers. 684 /* Save non-volatile registers.
694 * r31 will hold "old PTE" 685 * r31 will hold "old PTE"
695 * r30 is "new PTE" 686 * r30 is "new PTE"
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 98f262de5585..09dffe6efa46 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -871,6 +871,18 @@ static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
871} 871}
872#endif 872#endif
873 873
874void hash_failure_debug(unsigned long ea, unsigned long access,
875 unsigned long vsid, unsigned long trap,
876 int ssize, int psize, unsigned long pte)
877{
878 if (!printk_ratelimit())
879 return;
880 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
881 ea, access, current->comm);
882 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
883 trap, vsid, ssize, psize, pte);
884}
885
874/* Result code is: 886/* Result code is:
875 * 0 - handled 887 * 0 - handled
876 * 1 - normal page fault 888 * 1 - normal page fault
@@ -955,6 +967,17 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
955 return 1; 967 return 1;
956 } 968 }
957 969
970 /* Add _PAGE_PRESENT to the required access perm */
971 access |= _PAGE_PRESENT;
972
973 /* Pre-check access permissions (will be re-checked atomically
974 * in __hash_page_XX but this pre-check is a fast path
975 */
976 if (access & ~pte_val(*ptep)) {
977 DBG_LOW(" no access !\n");
978 return 1;
979 }
980
958#ifdef CONFIG_HUGETLB_PAGE 981#ifdef CONFIG_HUGETLB_PAGE
959 if (hugeshift) 982 if (hugeshift)
960 return __hash_page_huge(ea, access, vsid, ptep, trap, local, 983 return __hash_page_huge(ea, access, vsid, ptep, trap, local,
@@ -967,14 +990,6 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
967 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), 990 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
968 pte_val(*(ptep + PTRS_PER_PTE))); 991 pte_val(*(ptep + PTRS_PER_PTE)));
969#endif 992#endif
970 /* Pre-check access permissions (will be re-checked atomically
971 * in __hash_page_XX but this pre-check is a fast path
972 */
973 if (access & ~pte_val(*ptep)) {
974 DBG_LOW(" no access !\n");
975 return 1;
976 }
977
978 /* Do actual hashing */ 993 /* Do actual hashing */
979#ifdef CONFIG_PPC_64K_PAGES 994#ifdef CONFIG_PPC_64K_PAGES
980 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */ 995 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
@@ -1033,6 +1048,12 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
1033 local, ssize, spp); 1048 local, ssize, spp);
1034 } 1049 }
1035 1050
1051 /* Dump some info in case of hash insertion failure, they should
1052 * never happen so it is really useful to know if/when they do
1053 */
1054 if (rc == -1)
1055 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1056 pte_val(*ptep));
1036#ifndef CONFIG_PPC_64K_PAGES 1057#ifndef CONFIG_PPC_64K_PAGES
1037 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); 1058 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1038#else 1059#else
@@ -1051,8 +1072,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
1051 void *pgdir; 1072 void *pgdir;
1052 pte_t *ptep; 1073 pte_t *ptep;
1053 unsigned long flags; 1074 unsigned long flags;
1054 int local = 0; 1075 int rc, ssize, local = 0;
1055 int ssize;
1056 1076
1057 BUG_ON(REGION_ID(ea) != USER_REGION_ID); 1077 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1058 1078
@@ -1098,11 +1118,18 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
1098 /* Hash it in */ 1118 /* Hash it in */
1099#ifdef CONFIG_PPC_HAS_HASH_64K 1119#ifdef CONFIG_PPC_HAS_HASH_64K
1100 if (mm->context.user_psize == MMU_PAGE_64K) 1120 if (mm->context.user_psize == MMU_PAGE_64K)
1101 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); 1121 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1102 else 1122 else
1103#endif /* CONFIG_PPC_HAS_HASH_64K */ 1123#endif /* CONFIG_PPC_HAS_HASH_64K */
1104 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize, 1124 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1105 subpage_protection(pgdir, ea)); 1125 subpage_protection(pgdir, ea));
1126
1127 /* Dump some info in case of hash insertion failure, they should
1128 * never happen so it is really useful to know if/when they do
1129 */
1130 if (rc == -1)
1131 hash_failure_debug(ea, access, vsid, trap, ssize,
1132 mm->context.user_psize, pte_val(*ptep));
1106 1133
1107 local_irq_restore(flags); 1134 local_irq_restore(flags);
1108} 1135}
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index 199539882f92..cc5c273086cf 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -21,21 +21,13 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
21 unsigned long old_pte, new_pte; 21 unsigned long old_pte, new_pte;
22 unsigned long va, rflags, pa, sz; 22 unsigned long va, rflags, pa, sz;
23 long slot; 23 long slot;
24 int err = 1;
25 24
26 BUG_ON(shift != mmu_psize_defs[mmu_psize].shift); 25 BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
27 26
28 /* Search the Linux page table for a match with va */ 27 /* Search the Linux page table for a match with va */
29 va = hpt_va(ea, vsid, ssize); 28 va = hpt_va(ea, vsid, ssize);
30 29
31 /* 30 /* At this point, we have a pte (old_pte) which can be used to build
32 * Check the user's access rights to the page. If access should be
33 * prevented then send the problem up to do_page_fault.
34 */
35 if (unlikely(access & ~pte_val(*ptep)))
36 goto out;
37 /*
38 * At this point, we have a pte (old_pte) which can be used to build
39 * or update an HPTE. There are 2 cases: 31 * or update an HPTE. There are 2 cases:
40 * 32 *
41 * 1. There is a valid (present) pte with no associated HPTE (this is 33 * 1. There is a valid (present) pte with no associated HPTE (this is
@@ -49,9 +41,17 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
49 41
50 do { 42 do {
51 old_pte = pte_val(*ptep); 43 old_pte = pte_val(*ptep);
52 if (old_pte & _PAGE_BUSY) 44 /* If PTE busy, retry the access */
53 goto out; 45 if (unlikely(old_pte & _PAGE_BUSY))
46 return 0;
47 /* If PTE permissions don't match, take page fault */
48 if (unlikely(access & ~old_pte))
49 return 1;
50 /* Try to lock the PTE, add ACCESSED and DIRTY if it was
51 * a write access */
54 new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED; 52 new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED;
53 if (access & _PAGE_RW)
54 new_pte |= _PAGE_DIRTY;
55 } while(old_pte != __cmpxchg_u64((unsigned long *)ptep, 55 } while(old_pte != __cmpxchg_u64((unsigned long *)ptep,
56 old_pte, new_pte)); 56 old_pte, new_pte));
57 57
@@ -121,8 +121,16 @@ repeat:
121 } 121 }
122 } 122 }
123 123
124 if (unlikely(slot == -2)) 124 /*
125 panic("hash_huge_page: pte_insert failed\n"); 125 * Hypervisor failure. Restore old pte and return -1
126 * similar to __hash_page_*
127 */
128 if (unlikely(slot == -2)) {
129 *ptep = __pte(old_pte);
130 hash_failure_debug(ea, access, vsid, trap, ssize,
131 mmu_psize, old_pte);
132 return -1;
133 }
126 134
127 new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX); 135 new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX);
128 } 136 }
@@ -131,9 +139,5 @@ repeat:
131 * No need to use ldarx/stdcx here 139 * No need to use ldarx/stdcx here
132 */ 140 */
133 *ptep = __pte(new_pte & ~_PAGE_BUSY); 141 *ptep = __pte(new_pte & ~_PAGE_BUSY);
134 142 return 0;
135 err = 0;
136
137 out:
138 return err;
139} 143}
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index f47364585ecd..aa731af720c0 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -398,15 +398,15 @@ static int of_get_drconf_memory(struct device_node *memory, const u32 **dm)
398} 398}
399 399
400/* 400/*
401 * Retreive and validate the ibm,memblock-size property for drconf memory 401 * Retreive and validate the ibm,lmb-size property for drconf memory
402 * from the device tree. 402 * from the device tree.
403 */ 403 */
404static u64 of_get_memblock_size(struct device_node *memory) 404static u64 of_get_lmb_size(struct device_node *memory)
405{ 405{
406 const u32 *prop; 406 const u32 *prop;
407 u32 len; 407 u32 len;
408 408
409 prop = of_get_property(memory, "ibm,memblock-size", &len); 409 prop = of_get_property(memory, "ibm,lmb-size", &len);
410 if (!prop || len < sizeof(unsigned int)) 410 if (!prop || len < sizeof(unsigned int))
411 return 0; 411 return 0;
412 412
@@ -562,7 +562,7 @@ static unsigned long __init numa_enforce_memory_limit(unsigned long start,
562static inline int __init read_usm_ranges(const u32 **usm) 562static inline int __init read_usm_ranges(const u32 **usm)
563{ 563{
564 /* 564 /*
565 * For each memblock in ibm,dynamic-memory a corresponding 565 * For each lmb in ibm,dynamic-memory a corresponding
566 * entry in linux,drconf-usable-memory property contains 566 * entry in linux,drconf-usable-memory property contains
567 * a counter followed by that many (base, size) duple. 567 * a counter followed by that many (base, size) duple.
568 * read the counter from linux,drconf-usable-memory 568 * read the counter from linux,drconf-usable-memory
@@ -578,7 +578,7 @@ static void __init parse_drconf_memory(struct device_node *memory)
578{ 578{
579 const u32 *dm, *usm; 579 const u32 *dm, *usm;
580 unsigned int n, rc, ranges, is_kexec_kdump = 0; 580 unsigned int n, rc, ranges, is_kexec_kdump = 0;
581 unsigned long memblock_size, base, size, sz; 581 unsigned long lmb_size, base, size, sz;
582 int nid; 582 int nid;
583 struct assoc_arrays aa; 583 struct assoc_arrays aa;
584 584
@@ -586,8 +586,8 @@ static void __init parse_drconf_memory(struct device_node *memory)
586 if (!n) 586 if (!n)
587 return; 587 return;
588 588
589 memblock_size = of_get_memblock_size(memory); 589 lmb_size = of_get_lmb_size(memory);
590 if (!memblock_size) 590 if (!lmb_size)
591 return; 591 return;
592 592
593 rc = of_get_assoc_arrays(memory, &aa); 593 rc = of_get_assoc_arrays(memory, &aa);
@@ -611,7 +611,7 @@ static void __init parse_drconf_memory(struct device_node *memory)
611 continue; 611 continue;
612 612
613 base = drmem.base_addr; 613 base = drmem.base_addr;
614 size = memblock_size; 614 size = lmb_size;
615 ranges = 1; 615 ranges = 1;
616 616
617 if (is_kexec_kdump) { 617 if (is_kexec_kdump) {
@@ -1072,7 +1072,7 @@ static int hot_add_drconf_scn_to_nid(struct device_node *memory,
1072{ 1072{
1073 const u32 *dm; 1073 const u32 *dm;
1074 unsigned int drconf_cell_cnt, rc; 1074 unsigned int drconf_cell_cnt, rc;
1075 unsigned long memblock_size; 1075 unsigned long lmb_size;
1076 struct assoc_arrays aa; 1076 struct assoc_arrays aa;
1077 int nid = -1; 1077 int nid = -1;
1078 1078
@@ -1080,8 +1080,8 @@ static int hot_add_drconf_scn_to_nid(struct device_node *memory,
1080 if (!drconf_cell_cnt) 1080 if (!drconf_cell_cnt)
1081 return -1; 1081 return -1;
1082 1082
1083 memblock_size = of_get_memblock_size(memory); 1083 lmb_size = of_get_lmb_size(memory);
1084 if (!memblock_size) 1084 if (!lmb_size)
1085 return -1; 1085 return -1;
1086 1086
1087 rc = of_get_assoc_arrays(memory, &aa); 1087 rc = of_get_assoc_arrays(memory, &aa);
@@ -1100,7 +1100,7 @@ static int hot_add_drconf_scn_to_nid(struct device_node *memory,
1100 continue; 1100 continue;
1101 1101
1102 if ((scn_addr < drmem.base_addr) 1102 if ((scn_addr < drmem.base_addr)
1103 || (scn_addr >= (drmem.base_addr + memblock_size))) 1103 || (scn_addr >= (drmem.base_addr + lmb_size)))
1104 continue; 1104 continue;
1105 1105
1106 nid = of_drconf_to_nid_single(&drmem, &aa); 1106 nid = of_drconf_to_nid_single(&drmem, &aa);
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index deab5f946090..bc8803664140 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -69,7 +69,7 @@ static int pseries_remove_memory(struct device_node *np)
69 const char *type; 69 const char *type;
70 const unsigned int *regs; 70 const unsigned int *regs;
71 unsigned long base; 71 unsigned long base;
72 unsigned int memblock_size; 72 unsigned int lmb_size;
73 int ret = -EINVAL; 73 int ret = -EINVAL;
74 74
75 /* 75 /*
@@ -87,9 +87,9 @@ static int pseries_remove_memory(struct device_node *np)
87 return ret; 87 return ret;
88 88
89 base = *(unsigned long *)regs; 89 base = *(unsigned long *)regs;
90 memblock_size = regs[3]; 90 lmb_size = regs[3];
91 91
92 ret = pseries_remove_memblock(base, memblock_size); 92 ret = pseries_remove_memblock(base, lmb_size);
93 return ret; 93 return ret;
94} 94}
95 95
@@ -98,7 +98,7 @@ static int pseries_add_memory(struct device_node *np)
98 const char *type; 98 const char *type;
99 const unsigned int *regs; 99 const unsigned int *regs;
100 unsigned long base; 100 unsigned long base;
101 unsigned int memblock_size; 101 unsigned int lmb_size;
102 int ret = -EINVAL; 102 int ret = -EINVAL;
103 103
104 /* 104 /*
@@ -116,36 +116,36 @@ static int pseries_add_memory(struct device_node *np)
116 return ret; 116 return ret;
117 117
118 base = *(unsigned long *)regs; 118 base = *(unsigned long *)regs;
119 memblock_size = regs[3]; 119 lmb_size = regs[3];
120 120
121 /* 121 /*
122 * Update memory region to represent the memory add 122 * Update memory region to represent the memory add
123 */ 123 */
124 ret = memblock_add(base, memblock_size); 124 ret = memblock_add(base, lmb_size);
125 return (ret < 0) ? -EINVAL : 0; 125 return (ret < 0) ? -EINVAL : 0;
126} 126}
127 127
128static int pseries_drconf_memory(unsigned long *base, unsigned int action) 128static int pseries_drconf_memory(unsigned long *base, unsigned int action)
129{ 129{
130 struct device_node *np; 130 struct device_node *np;
131 const unsigned long *memblock_size; 131 const unsigned long *lmb_size;
132 int rc; 132 int rc;
133 133
134 np = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory"); 134 np = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
135 if (!np) 135 if (!np)
136 return -EINVAL; 136 return -EINVAL;
137 137
138 memblock_size = of_get_property(np, "ibm,memblock-size", NULL); 138 lmb_size = of_get_property(np, "ibm,lmb-size", NULL);
139 if (!memblock_size) { 139 if (!lmb_size) {
140 of_node_put(np); 140 of_node_put(np);
141 return -EINVAL; 141 return -EINVAL;
142 } 142 }
143 143
144 if (action == PSERIES_DRCONF_MEM_ADD) { 144 if (action == PSERIES_DRCONF_MEM_ADD) {
145 rc = memblock_add(*base, *memblock_size); 145 rc = memblock_add(*base, *lmb_size);
146 rc = (rc < 0) ? -EINVAL : 0; 146 rc = (rc < 0) ? -EINVAL : 0;
147 } else if (action == PSERIES_DRCONF_MEM_REMOVE) { 147 } else if (action == PSERIES_DRCONF_MEM_REMOVE) {
148 rc = pseries_remove_memblock(*base, *memblock_size); 148 rc = pseries_remove_memblock(*base, *lmb_size);
149 } else { 149 } else {
150 rc = -EINVAL; 150 rc = -EINVAL;
151 } 151 }
diff --git a/arch/sparc/configs/sparc64_defconfig b/arch/sparc/configs/sparc64_defconfig
index 259e3fd50993..1dc07a0014c1 100644
--- a/arch/sparc/configs/sparc64_defconfig
+++ b/arch/sparc/configs/sparc64_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.34-rc3 3# Linux kernel version: 2.6.34
4# Sat Apr 3 15:49:56 2010 4# Wed May 26 21:14:01 2010
5# 5#
6CONFIG_64BIT=y 6CONFIG_64BIT=y
7CONFIG_SPARC=y 7CONFIG_SPARC=y
@@ -107,10 +107,9 @@ CONFIG_PERF_COUNTERS=y
107# CONFIG_DEBUG_PERF_USE_VMALLOC is not set 107# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
108CONFIG_VM_EVENT_COUNTERS=y 108CONFIG_VM_EVENT_COUNTERS=y
109CONFIG_PCI_QUIRKS=y 109CONFIG_PCI_QUIRKS=y
110CONFIG_SLUB_DEBUG=y
111# CONFIG_COMPAT_BRK is not set 110# CONFIG_COMPAT_BRK is not set
112# CONFIG_SLAB is not set 111CONFIG_SLAB=y
113CONFIG_SLUB=y 112# CONFIG_SLUB is not set
114# CONFIG_SLOB is not set 113# CONFIG_SLOB is not set
115CONFIG_PROFILING=y 114CONFIG_PROFILING=y
116CONFIG_TRACEPOINTS=y 115CONFIG_TRACEPOINTS=y
@@ -239,6 +238,7 @@ CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
239CONFIG_SPARSEMEM_VMEMMAP=y 238CONFIG_SPARSEMEM_VMEMMAP=y
240CONFIG_PAGEFLAGS_EXTENDED=y 239CONFIG_PAGEFLAGS_EXTENDED=y
241CONFIG_SPLIT_PTLOCK_CPUS=4 240CONFIG_SPLIT_PTLOCK_CPUS=4
241# CONFIG_COMPACTION is not set
242CONFIG_MIGRATION=y 242CONFIG_MIGRATION=y
243CONFIG_PHYS_ADDR_T_64BIT=y 243CONFIG_PHYS_ADDR_T_64BIT=y
244CONFIG_ZONE_DMA_FLAG=0 244CONFIG_ZONE_DMA_FLAG=0
@@ -351,6 +351,7 @@ CONFIG_IPV6_TUNNEL=m
351# CONFIG_RDS is not set 351# CONFIG_RDS is not set
352# CONFIG_TIPC is not set 352# CONFIG_TIPC is not set
353# CONFIG_ATM is not set 353# CONFIG_ATM is not set
354# CONFIG_L2TP is not set
354# CONFIG_BRIDGE is not set 355# CONFIG_BRIDGE is not set
355# CONFIG_NET_DSA is not set 356# CONFIG_NET_DSA is not set
356CONFIG_VLAN_8021Q=m 357CONFIG_VLAN_8021Q=m
@@ -367,6 +368,7 @@ CONFIG_VLAN_8021Q=m
367# CONFIG_IEEE802154 is not set 368# CONFIG_IEEE802154 is not set
368# CONFIG_NET_SCHED is not set 369# CONFIG_NET_SCHED is not set
369# CONFIG_DCB is not set 370# CONFIG_DCB is not set
371CONFIG_RPS=y
370 372
371# 373#
372# Network testing 374# Network testing
@@ -386,9 +388,14 @@ CONFIG_WIRELESS=y
386# 388#
387# CFG80211 needs to be enabled for MAC80211 389# CFG80211 needs to be enabled for MAC80211
388# 390#
391
392#
393# Some wireless drivers require a rate control algorithm
394#
389# CONFIG_WIMAX is not set 395# CONFIG_WIMAX is not set
390# CONFIG_RFKILL is not set 396# CONFIG_RFKILL is not set
391# CONFIG_NET_9P is not set 397# CONFIG_NET_9P is not set
398# CONFIG_CAIF is not set
392 399
393# 400#
394# Device Drivers 401# Device Drivers
@@ -658,6 +665,7 @@ CONFIG_PHYLIB=m
658# CONFIG_NATIONAL_PHY is not set 665# CONFIG_NATIONAL_PHY is not set
659# CONFIG_STE10XP is not set 666# CONFIG_STE10XP is not set
660# CONFIG_LSI_ET1011C_PHY is not set 667# CONFIG_LSI_ET1011C_PHY is not set
668# CONFIG_MICREL_PHY is not set
661# CONFIG_MDIO_BITBANG is not set 669# CONFIG_MDIO_BITBANG is not set
662CONFIG_NET_ETHERNET=y 670CONFIG_NET_ETHERNET=y
663CONFIG_MII=m 671CONFIG_MII=m
@@ -734,6 +742,8 @@ CONFIG_NETDEV_10000=y
734# CONFIG_CHELSIO_T1 is not set 742# CONFIG_CHELSIO_T1 is not set
735CONFIG_CHELSIO_T3_DEPENDS=y 743CONFIG_CHELSIO_T3_DEPENDS=y
736# CONFIG_CHELSIO_T3 is not set 744# CONFIG_CHELSIO_T3 is not set
745CONFIG_CHELSIO_T4_DEPENDS=y
746# CONFIG_CHELSIO_T4 is not set
737# CONFIG_ENIC is not set 747# CONFIG_ENIC is not set
738# CONFIG_IXGBE is not set 748# CONFIG_IXGBE is not set
739# CONFIG_IXGBEVF is not set 749# CONFIG_IXGBEVF is not set
@@ -766,6 +776,7 @@ CONFIG_NIU=m
766# CONFIG_USB_PEGASUS is not set 776# CONFIG_USB_PEGASUS is not set
767# CONFIG_USB_RTL8150 is not set 777# CONFIG_USB_RTL8150 is not set
768# CONFIG_USB_USBNET is not set 778# CONFIG_USB_USBNET is not set
779# CONFIG_USB_IPHETH is not set
769# CONFIG_WAN is not set 780# CONFIG_WAN is not set
770# CONFIG_FDDI is not set 781# CONFIG_FDDI is not set
771# CONFIG_HIPPI is not set 782# CONFIG_HIPPI is not set
@@ -778,7 +789,6 @@ CONFIG_PPP_DEFLATE=m
778CONFIG_PPP_BSDCOMP=m 789CONFIG_PPP_BSDCOMP=m
779CONFIG_PPP_MPPE=m 790CONFIG_PPP_MPPE=m
780CONFIG_PPPOE=m 791CONFIG_PPPOE=m
781# CONFIG_PPPOL2TP is not set
782# CONFIG_SLIP is not set 792# CONFIG_SLIP is not set
783CONFIG_SLHC=m 793CONFIG_SLHC=m
784# CONFIG_NET_FC is not set 794# CONFIG_NET_FC is not set
@@ -816,6 +826,7 @@ CONFIG_INPUT_KEYBOARD=y
816CONFIG_KEYBOARD_ATKBD=y 826CONFIG_KEYBOARD_ATKBD=y
817# CONFIG_QT2160 is not set 827# CONFIG_QT2160 is not set
818CONFIG_KEYBOARD_LKKBD=m 828CONFIG_KEYBOARD_LKKBD=m
829# CONFIG_KEYBOARD_TCA6416 is not set
819# CONFIG_KEYBOARD_MAX7359 is not set 830# CONFIG_KEYBOARD_MAX7359 is not set
820# CONFIG_KEYBOARD_NEWTON is not set 831# CONFIG_KEYBOARD_NEWTON is not set
821# CONFIG_KEYBOARD_OPENCORES is not set 832# CONFIG_KEYBOARD_OPENCORES is not set
@@ -840,6 +851,7 @@ CONFIG_MOUSE_SERIAL=y
840# CONFIG_INPUT_TABLET is not set 851# CONFIG_INPUT_TABLET is not set
841# CONFIG_INPUT_TOUCHSCREEN is not set 852# CONFIG_INPUT_TOUCHSCREEN is not set
842CONFIG_INPUT_MISC=y 853CONFIG_INPUT_MISC=y
854# CONFIG_INPUT_AD714X is not set
843CONFIG_INPUT_SPARCSPKR=y 855CONFIG_INPUT_SPARCSPKR=y
844# CONFIG_INPUT_ATI_REMOTE is not set 856# CONFIG_INPUT_ATI_REMOTE is not set
845# CONFIG_INPUT_ATI_REMOTE2 is not set 857# CONFIG_INPUT_ATI_REMOTE2 is not set
@@ -848,6 +860,7 @@ CONFIG_INPUT_SPARCSPKR=y
848# CONFIG_INPUT_YEALINK is not set 860# CONFIG_INPUT_YEALINK is not set
849# CONFIG_INPUT_CM109 is not set 861# CONFIG_INPUT_CM109 is not set
850# CONFIG_INPUT_UINPUT is not set 862# CONFIG_INPUT_UINPUT is not set
863# CONFIG_INPUT_PCF8574 is not set
851 864
852# 865#
853# Hardware I/O ports 866# Hardware I/O ports
@@ -871,6 +884,7 @@ CONFIG_HW_CONSOLE=y
871# CONFIG_VT_HW_CONSOLE_BINDING is not set 884# CONFIG_VT_HW_CONSOLE_BINDING is not set
872# CONFIG_DEVKMEM is not set 885# CONFIG_DEVKMEM is not set
873# CONFIG_SERIAL_NONSTANDARD is not set 886# CONFIG_SERIAL_NONSTANDARD is not set
887# CONFIG_N_GSM is not set
874# CONFIG_NOZOMI is not set 888# CONFIG_NOZOMI is not set
875 889
876# 890#
@@ -893,6 +907,8 @@ CONFIG_SERIAL_CORE_CONSOLE=y
893# CONFIG_SERIAL_JSM is not set 907# CONFIG_SERIAL_JSM is not set
894# CONFIG_SERIAL_TIMBERDALE is not set 908# CONFIG_SERIAL_TIMBERDALE is not set
895# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set 909# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
910# CONFIG_SERIAL_ALTERA_JTAGUART is not set
911# CONFIG_SERIAL_ALTERA_UART is not set
896CONFIG_UNIX98_PTYS=y 912CONFIG_UNIX98_PTYS=y
897# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 913# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
898# CONFIG_LEGACY_PTYS is not set 914# CONFIG_LEGACY_PTYS is not set
@@ -1306,11 +1322,14 @@ CONFIG_USB_HIDDEV=y
1306CONFIG_HID_A4TECH=y 1322CONFIG_HID_A4TECH=y
1307CONFIG_HID_APPLE=y 1323CONFIG_HID_APPLE=y
1308CONFIG_HID_BELKIN=y 1324CONFIG_HID_BELKIN=y
1325# CONFIG_HID_CANDO is not set
1309CONFIG_HID_CHERRY=y 1326CONFIG_HID_CHERRY=y
1310CONFIG_HID_CHICONY=y 1327CONFIG_HID_CHICONY=y
1328# CONFIG_HID_PRODIKEYS is not set
1311CONFIG_HID_CYPRESS=y 1329CONFIG_HID_CYPRESS=y
1312CONFIG_HID_DRAGONRISE=y 1330CONFIG_HID_DRAGONRISE=y
1313# CONFIG_DRAGONRISE_FF is not set 1331# CONFIG_DRAGONRISE_FF is not set
1332# CONFIG_HID_EGALAX is not set
1314CONFIG_HID_EZKEY=y 1333CONFIG_HID_EZKEY=y
1315CONFIG_HID_KYE=y 1334CONFIG_HID_KYE=y
1316CONFIG_HID_GYRATION=y 1335CONFIG_HID_GYRATION=y
@@ -1328,7 +1347,9 @@ CONFIG_HID_ORTEK=y
1328CONFIG_HID_PANTHERLORD=y 1347CONFIG_HID_PANTHERLORD=y
1329# CONFIG_PANTHERLORD_FF is not set 1348# CONFIG_PANTHERLORD_FF is not set
1330CONFIG_HID_PETALYNX=y 1349CONFIG_HID_PETALYNX=y
1350# CONFIG_HID_PICOLCD is not set
1331# CONFIG_HID_QUANTA is not set 1351# CONFIG_HID_QUANTA is not set
1352# CONFIG_HID_ROCCAT_KONE is not set
1332CONFIG_HID_SAMSUNG=y 1353CONFIG_HID_SAMSUNG=y
1333CONFIG_HID_SONY=y 1354CONFIG_HID_SONY=y
1334# CONFIG_HID_STANTUM is not set 1355# CONFIG_HID_STANTUM is not set
@@ -1342,6 +1363,7 @@ CONFIG_HID_THRUSTMASTER=y
1342# CONFIG_THRUSTMASTER_FF is not set 1363# CONFIG_THRUSTMASTER_FF is not set
1343CONFIG_HID_ZEROPLUS=y 1364CONFIG_HID_ZEROPLUS=y
1344# CONFIG_ZEROPLUS_FF is not set 1365# CONFIG_ZEROPLUS_FF is not set
1366# CONFIG_HID_ZYDACRON is not set
1345CONFIG_USB_SUPPORT=y 1367CONFIG_USB_SUPPORT=y
1346CONFIG_USB_ARCH_HAS_HCD=y 1368CONFIG_USB_ARCH_HAS_HCD=y
1347CONFIG_USB_ARCH_HAS_OHCI=y 1369CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1356,7 +1378,6 @@ CONFIG_USB=y
1356# CONFIG_USB_DEVICEFS is not set 1378# CONFIG_USB_DEVICEFS is not set
1357# CONFIG_USB_DEVICE_CLASS is not set 1379# CONFIG_USB_DEVICE_CLASS is not set
1358# CONFIG_USB_DYNAMIC_MINORS is not set 1380# CONFIG_USB_DYNAMIC_MINORS is not set
1359# CONFIG_USB_OTG is not set
1360# CONFIG_USB_MON is not set 1381# CONFIG_USB_MON is not set
1361# CONFIG_USB_WUSB is not set 1382# CONFIG_USB_WUSB is not set
1362# CONFIG_USB_WUSB_CBAF is not set 1383# CONFIG_USB_WUSB_CBAF is not set
@@ -1521,10 +1542,6 @@ CONFIG_RTC_DRV_STARFIRE=y
1521# CONFIG_DMADEVICES is not set 1542# CONFIG_DMADEVICES is not set
1522# CONFIG_AUXDISPLAY is not set 1543# CONFIG_AUXDISPLAY is not set
1523# CONFIG_UIO is not set 1544# CONFIG_UIO is not set
1524
1525#
1526# TI VLYNQ
1527#
1528# CONFIG_STAGING is not set 1545# CONFIG_STAGING is not set
1529 1546
1530# 1547#
@@ -1706,8 +1723,8 @@ CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1706CONFIG_SCHEDSTATS=y 1723CONFIG_SCHEDSTATS=y
1707# CONFIG_TIMER_STATS is not set 1724# CONFIG_TIMER_STATS is not set
1708# CONFIG_DEBUG_OBJECTS is not set 1725# CONFIG_DEBUG_OBJECTS is not set
1709# CONFIG_SLUB_DEBUG_ON is not set 1726# CONFIG_DEBUG_SLAB is not set
1710# CONFIG_SLUB_STATS is not set 1727# CONFIG_DEBUG_KMEMLEAK is not set
1711# CONFIG_DEBUG_RT_MUTEXES is not set 1728# CONFIG_DEBUG_RT_MUTEXES is not set
1712# CONFIG_RT_MUTEX_TESTER is not set 1729# CONFIG_RT_MUTEX_TESTER is not set
1713# CONFIG_DEBUG_SPINLOCK is not set 1730# CONFIG_DEBUG_SPINLOCK is not set
@@ -1742,6 +1759,9 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
1742# CONFIG_DEBUG_PAGEALLOC is not set 1759# CONFIG_DEBUG_PAGEALLOC is not set
1743CONFIG_NOP_TRACER=y 1760CONFIG_NOP_TRACER=y
1744CONFIG_HAVE_FUNCTION_TRACER=y 1761CONFIG_HAVE_FUNCTION_TRACER=y
1762CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1763CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y
1764CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1745CONFIG_HAVE_DYNAMIC_FTRACE=y 1765CONFIG_HAVE_DYNAMIC_FTRACE=y
1746CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1766CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1747CONFIG_HAVE_SYSCALL_TRACEPOINTS=y 1767CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
@@ -1769,12 +1789,12 @@ CONFIG_BLK_DEV_IO_TRACE=y
1769# CONFIG_RING_BUFFER_BENCHMARK is not set 1789# CONFIG_RING_BUFFER_BENCHMARK is not set
1770# CONFIG_DYNAMIC_DEBUG is not set 1790# CONFIG_DYNAMIC_DEBUG is not set
1771# CONFIG_DMA_API_DEBUG is not set 1791# CONFIG_DMA_API_DEBUG is not set
1792# CONFIG_ATOMIC64_SELFTEST is not set
1772# CONFIG_SAMPLES is not set 1793# CONFIG_SAMPLES is not set
1773CONFIG_HAVE_ARCH_KGDB=y 1794CONFIG_HAVE_ARCH_KGDB=y
1774# CONFIG_KGDB is not set 1795# CONFIG_KGDB is not set
1775# CONFIG_DEBUG_STACK_USAGE is not set 1796# CONFIG_DEBUG_STACK_USAGE is not set
1776# CONFIG_DEBUG_DCFLUSH is not set 1797# CONFIG_DEBUG_DCFLUSH is not set
1777# CONFIG_STACK_DEBUG is not set
1778# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set 1798# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
1779 1799
1780# 1800#
@@ -1895,6 +1915,7 @@ CONFIG_CRYPTO_DEFLATE=y
1895# 1915#
1896# CONFIG_CRYPTO_ANSI_CPRNG is not set 1916# CONFIG_CRYPTO_ANSI_CPRNG is not set
1897CONFIG_CRYPTO_HW=y 1917CONFIG_CRYPTO_HW=y
1918# CONFIG_CRYPTO_DEV_NIAGARA2 is not set
1898# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1919# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1899CONFIG_BINARY_PRINTF=y 1920CONFIG_BINARY_PRINTF=y
1900 1921
diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
index 0588b8c7faa2..69358b590c91 100644
--- a/arch/sparc/include/asm/cache.h
+++ b/arch/sparc/include/asm/cache.h
@@ -11,7 +11,6 @@
11 11
12#define L1_CACHE_SHIFT 5 12#define L1_CACHE_SHIFT 5
13#define L1_CACHE_BYTES 32 13#define L1_CACHE_BYTES 32
14#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
15 14
16#ifdef CONFIG_SPARC32 15#ifdef CONFIG_SPARC32
17#define SMP_CACHE_BYTES_SHIFT 5 16#define SMP_CACHE_BYTES_SHIFT 5
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h
index 77f906d8cc21..0ece77f47753 100644
--- a/arch/sparc/include/asm/pgtable_32.h
+++ b/arch/sparc/include/asm/pgtable_32.h
@@ -142,13 +142,12 @@ BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t)
142#define pmd_page(pmd) BTFIXUP_CALL(pmd_page)(pmd) 142#define pmd_page(pmd) BTFIXUP_CALL(pmd_page)(pmd)
143#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd) 143#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd)
144 144
145BTFIXUPDEF_SETHI(none_mask)
146BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t) 145BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t)
147BTFIXUPDEF_CALL(void, pte_clear, pte_t *) 146BTFIXUPDEF_CALL(void, pte_clear, pte_t *)
148 147
149static inline int pte_none(pte_t pte) 148static inline int pte_none(pte_t pte)
150{ 149{
151 return !(pte_val(pte) & ~BTFIXUP_SETHI(none_mask)); 150 return !pte_val(pte);
152} 151}
153 152
154#define pte_present(pte) BTFIXUP_CALL(pte_present)(pte) 153#define pte_present(pte) BTFIXUP_CALL(pte_present)(pte)
@@ -160,7 +159,7 @@ BTFIXUPDEF_CALL(void, pmd_clear, pmd_t *)
160 159
161static inline int pmd_none(pmd_t pmd) 160static inline int pmd_none(pmd_t pmd)
162{ 161{
163 return !(pmd_val(pmd) & ~BTFIXUP_SETHI(none_mask)); 162 return !pmd_val(pmd);
164} 163}
165 164
166#define pmd_bad(pmd) BTFIXUP_CALL(pmd_bad)(pmd) 165#define pmd_bad(pmd) BTFIXUP_CALL(pmd_bad)(pmd)
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 0ec92c8861dd..44faabc3c02c 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -657,6 +657,7 @@ static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
657 cpuc->current_idx[i] = idx; 657 cpuc->current_idx[i] = idx;
658 658
659 enc = perf_event_get_enc(cpuc->events[i]); 659 enc = perf_event_get_enc(cpuc->events[i]);
660 pcr &= ~mask_for_index(idx);
660 pcr |= event_encoding(enc, idx); 661 pcr |= event_encoding(enc, idx);
661 } 662 }
662out: 663out:
diff --git a/arch/sparc/kernel/sun4d_irq.c b/arch/sparc/kernel/sun4d_irq.c
index ab036a72de5a..e11b4612dabb 100644
--- a/arch/sparc/kernel/sun4d_irq.c
+++ b/arch/sparc/kernel/sun4d_irq.c
@@ -183,7 +183,7 @@ void sun4d_free_irq(unsigned int irq, void *dev_id)
183 goto out_unlock; 183 goto out_unlock;
184 } 184 }
185 185
186 if (action && tmp) 186 if (tmp)
187 tmp->next = action->next; 187 tmp->next = action->next;
188 else 188 else
189 *actionp = action->next; 189 *actionp = action->next;
diff --git a/arch/sparc/kernel/ttable.S b/arch/sparc/kernel/ttable.S
index 76d837fc47d3..c6dfdaa29e20 100644
--- a/arch/sparc/kernel/ttable.S
+++ b/arch/sparc/kernel/ttable.S
@@ -64,7 +64,7 @@ tl0_irq6: TRAP_IRQ(smp_call_function_single_client, 6)
64tl0_irq6: BTRAP(0x46) 64tl0_irq6: BTRAP(0x46)
65#endif 65#endif
66tl0_irq7: TRAP_IRQ(deferred_pcr_work_irq, 7) 66tl0_irq7: TRAP_IRQ(deferred_pcr_work_irq, 7)
67#ifdef CONFIG_KGDB 67#if defined(CONFIG_KGDB) && defined(CONFIG_SMP)
68tl0_irq8: TRAP_IRQ(smp_kgdb_capture_client, 8) 68tl0_irq8: TRAP_IRQ(smp_kgdb_capture_client, 8)
69#else 69#else
70tl0_irq8: BTRAP(0x48) 70tl0_irq8: BTRAP(0x48)
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index f5f75a58e0b3..b0b43aa5e45a 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -2215,8 +2215,6 @@ void __init ld_mmu_srmmu(void)
2215 BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM); 2215 BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
2216 BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM); 2216 BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
2217 2217
2218 BTFIXUPSET_SETHI(none_mask, 0xF0000000);
2219
2220 BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM); 2218 BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2221 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0); 2219 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
2222 2220
diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c
index cf38846753dd..4289f90f8697 100644
--- a/arch/sparc/mm/sun4c.c
+++ b/arch/sparc/mm/sun4c.c
@@ -2087,9 +2087,6 @@ void __init ld_mmu_sun4c(void)
2087 2087
2088 BTFIXUPSET_CALL(set_pte, sun4c_set_pte, BTFIXUPCALL_STO1O0); 2088 BTFIXUPSET_CALL(set_pte, sun4c_set_pte, BTFIXUPCALL_STO1O0);
2089 2089
2090 /* The 2.4.18 code does not set this on sun4c, how does it work? XXX */
2091 /* BTFIXUPSET_SETHI(none_mask, 0x00000000); */ /* Defaults to zero? */
2092
2093 BTFIXUPSET_CALL(pte_pfn, sun4c_pte_pfn, BTFIXUPCALL_NORM); 2090 BTFIXUPSET_CALL(pte_pfn, sun4c_pte_pfn, BTFIXUPCALL_NORM);
2094#if 0 /* PAGE_SHIFT <= 12 */ /* Eek. Investigate. XXX */ 2091#if 0 /* PAGE_SHIFT <= 12 */ /* Eek. Investigate. XXX */
2095 BTFIXUPSET_CALL(pmd_page, sun4c_pmd_page, BTFIXUPCALL_ANDNINT(PAGE_SIZE - 1)); 2092 BTFIXUPSET_CALL(pmd_page, sun4c_pmd_page, BTFIXUPCALL_ANDNINT(PAGE_SIZE - 1));
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 2e837f5080fe..fb7a5f052e2b 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -145,6 +145,15 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu,
145 percpu_entry->states[cx->index].eax = cx->address; 145 percpu_entry->states[cx->index].eax = cx->address;
146 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK; 146 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
147 } 147 }
148
149 /*
150 * For _CST FFH on Intel, if GAS.access_size bit 1 is cleared,
151 * then we should skip checking BM_STS for this C-state.
152 * ref: "Intel Processor Vendor-Specific ACPI Interface Specification"
153 */
154 if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2))
155 cx->bm_sts_skip = 1;
156
148 return retval; 157 return retval;
149} 158}
150EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe); 159EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 82e508677b91..fcc3c61fdecc 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -157,9 +157,14 @@ static int __init acpi_sleep_setup(char *str)
157#ifdef CONFIG_HIBERNATION 157#ifdef CONFIG_HIBERNATION
158 if (strncmp(str, "s4_nohwsig", 10) == 0) 158 if (strncmp(str, "s4_nohwsig", 10) == 0)
159 acpi_no_s4_hw_signature(); 159 acpi_no_s4_hw_signature();
160 if (strncmp(str, "s4_nonvs", 8) == 0) 160 if (strncmp(str, "s4_nonvs", 8) == 0) {
161 acpi_s4_no_nvs(); 161 pr_warning("ACPI: acpi_sleep=s4_nonvs is deprecated, "
162 "please use acpi_sleep=nonvs instead");
163 acpi_nvs_nosave();
164 }
162#endif 165#endif
166 if (strncmp(str, "nonvs", 5) == 0)
167 acpi_nvs_nosave();
163 if (strncmp(str, "old_ordering", 12) == 0) 168 if (strncmp(str, "old_ordering", 12) == 0)
164 acpi_old_suspend_ordering(); 169 acpi_old_suspend_ordering();
165 str = strchr(str, ','); 170 str = strchr(str, ',');
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index c02cc692985c..a96489ee6cab 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -921,7 +921,7 @@ void disable_local_APIC(void)
921 unsigned int value; 921 unsigned int value;
922 922
923 /* APIC hasn't been mapped yet */ 923 /* APIC hasn't been mapped yet */
924 if (!apic_phys) 924 if (!x2apic_mode && !apic_phys)
925 return; 925 return;
926 926
927 clear_local_APIC(); 927 clear_local_APIC();
diff --git a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
index ce7cde713e71..a36de5bbb622 100644
--- a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
@@ -368,22 +368,16 @@ static int __init pcc_cpufreq_do_osc(acpi_handle *handle)
368 return -ENODEV; 368 return -ENODEV;
369 369
370 out_obj = output.pointer; 370 out_obj = output.pointer;
371 if (out_obj->type != ACPI_TYPE_BUFFER) { 371 if (out_obj->type != ACPI_TYPE_BUFFER)
372 ret = -ENODEV; 372 return -ENODEV;
373 goto out_free;
374 }
375 373
376 errors = *((u32 *)out_obj->buffer.pointer) & ~(1 << 0); 374 errors = *((u32 *)out_obj->buffer.pointer) & ~(1 << 0);
377 if (errors) { 375 if (errors)
378 ret = -ENODEV; 376 return -ENODEV;
379 goto out_free;
380 }
381 377
382 supported = *((u32 *)(out_obj->buffer.pointer + 4)); 378 supported = *((u32 *)(out_obj->buffer.pointer + 4));
383 if (!(supported & 0x1)) { 379 if (!(supported & 0x1))
384 ret = -ENODEV; 380 return -ENODEV;
385 goto out_free;
386 }
387 381
388out_free: 382out_free:
389 kfree(output.pointer); 383 kfree(output.pointer);
@@ -397,13 +391,17 @@ static int __init pcc_cpufreq_probe(void)
397 struct pcc_memory_resource *mem_resource; 391 struct pcc_memory_resource *mem_resource;
398 struct pcc_register_resource *reg_resource; 392 struct pcc_register_resource *reg_resource;
399 union acpi_object *out_obj, *member; 393 union acpi_object *out_obj, *member;
400 acpi_handle handle, osc_handle; 394 acpi_handle handle, osc_handle, pcch_handle;
401 int ret = 0; 395 int ret = 0;
402 396
403 status = acpi_get_handle(NULL, "\\_SB", &handle); 397 status = acpi_get_handle(NULL, "\\_SB", &handle);
404 if (ACPI_FAILURE(status)) 398 if (ACPI_FAILURE(status))
405 return -ENODEV; 399 return -ENODEV;
406 400
401 status = acpi_get_handle(handle, "PCCH", &pcch_handle);
402 if (ACPI_FAILURE(status))
403 return -ENODEV;
404
407 status = acpi_get_handle(handle, "_OSC", &osc_handle); 405 status = acpi_get_handle(handle, "_OSC", &osc_handle);
408 if (ACPI_SUCCESS(status)) { 406 if (ACPI_SUCCESS(status)) {
409 ret = pcc_cpufreq_do_osc(&osc_handle); 407 ret = pcc_cpufreq_do_osc(&osc_handle);
@@ -543,13 +541,13 @@ static int pcc_cpufreq_cpu_init(struct cpufreq_policy *policy)
543 541
544 if (!pcch_virt_addr) { 542 if (!pcch_virt_addr) {
545 result = -1; 543 result = -1;
546 goto pcch_null; 544 goto out;
547 } 545 }
548 546
549 result = pcc_get_offset(cpu); 547 result = pcc_get_offset(cpu);
550 if (result) { 548 if (result) {
551 dprintk("init: PCCP evaluation failed\n"); 549 dprintk("init: PCCP evaluation failed\n");
552 goto free; 550 goto out;
553 } 551 }
554 552
555 policy->max = policy->cpuinfo.max_freq = 553 policy->max = policy->cpuinfo.max_freq =
@@ -558,14 +556,15 @@ static int pcc_cpufreq_cpu_init(struct cpufreq_policy *policy)
558 ioread32(&pcch_hdr->minimum_frequency) * 1000; 556 ioread32(&pcch_hdr->minimum_frequency) * 1000;
559 policy->cur = pcc_get_freq(cpu); 557 policy->cur = pcc_get_freq(cpu);
560 558
559 if (!policy->cur) {
560 dprintk("init: Unable to get current CPU frequency\n");
561 result = -EINVAL;
562 goto out;
563 }
564
561 dprintk("init: policy->max is %d, policy->min is %d\n", 565 dprintk("init: policy->max is %d, policy->min is %d\n",
562 policy->max, policy->min); 566 policy->max, policy->min);
563 567out:
564 return 0;
565free:
566 pcc_clear_mapping();
567 free_percpu(pcc_cpu_info);
568pcch_null:
569 return result; 568 return result;
570} 569}
571 570
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 7ec2123838e6..3e90cce3dc8b 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -1023,13 +1023,12 @@ static int get_transition_latency(struct powernow_k8_data *data)
1023 } 1023 }
1024 if (max_latency == 0) { 1024 if (max_latency == 0) {
1025 /* 1025 /*
1026 * Fam 11h always returns 0 as transition latency. 1026 * Fam 11h and later may return 0 as transition latency. This
1027 * This is intended and means "very fast". While cpufreq core 1027 * is intended and means "very fast". While cpufreq core and
1028 * and governors currently can handle that gracefully, better 1028 * governors currently can handle that gracefully, better set it
1029 * set it to 1 to avoid problems in the future. 1029 * to 1 to avoid problems in the future.
1030 * For all others it's a BIOS bug.
1031 */ 1030 */
1032 if (boot_cpu_data.x86 != 0x11) 1031 if (boot_cpu_data.x86 < 0x11)
1033 printk(KERN_ERR FW_WARN PFX "Invalid zero transition " 1032 printk(KERN_ERR FW_WARN PFX "Invalid zero transition "
1034 "latency\n"); 1033 "latency\n");
1035 max_latency = 1; 1034 max_latency = 1;
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index ebdb85cf2686..e5cc7e82e60d 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -18,6 +18,7 @@
18#include <asm/apic.h> 18#include <asm/apic.h>
19#include <asm/iommu.h> 19#include <asm/iommu.h>
20#include <asm/gart.h> 20#include <asm/gart.h>
21#include <asm/hpet.h>
21 22
22static void __init fix_hypertransport_config(int num, int slot, int func) 23static void __init fix_hypertransport_config(int num, int slot, int func)
23{ 24{
@@ -191,6 +192,21 @@ static void __init ati_bugs_contd(int num, int slot, int func)
191} 192}
192#endif 193#endif
193 194
195/*
196 * Force the read back of the CMP register in hpet_next_event()
197 * to work around the problem that the CMP register write seems to be
198 * delayed. See hpet_next_event() for details.
199 *
200 * We do this on all SMBUS incarnations for now until we have more
201 * information about the affected chipsets.
202 */
203static void __init ati_hpet_bugs(int num, int slot, int func)
204{
205#ifdef CONFIG_HPET_TIMER
206 hpet_readback_cmp = 1;
207#endif
208}
209
194#define QFLAG_APPLY_ONCE 0x1 210#define QFLAG_APPLY_ONCE 0x1
195#define QFLAG_APPLIED 0x2 211#define QFLAG_APPLIED 0x2
196#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED) 212#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
@@ -220,6 +236,8 @@ static struct chipset early_qrk[] __initdata = {
220 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs }, 236 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
222 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd }, 238 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
239 { PCI_VENDOR_ID_ATI, PCI_ANY_ID,
240 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_hpet_bugs },
223 {} 241 {}
224}; 242};
225 243
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 0697ff139837..4db7c4d12ffa 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -571,8 +571,8 @@ auditsys:
571 * masked off. 571 * masked off.
572 */ 572 */
573sysret_audit: 573sysret_audit:
574 movq %rax,%rsi /* second arg, syscall return value */ 574 movq RAX-ARGOFFSET(%rsp),%rsi /* second arg, syscall return value */
575 cmpq $0,%rax /* is it < 0? */ 575 cmpq $0,%rsi /* is it < 0? */
576 setl %al /* 1 if so, 0 if not */ 576 setl %al /* 1 if so, 0 if not */
577 movzbl %al,%edi /* zero-extend that into %edi */ 577 movzbl %al,%edi /* zero-extend that into %edi */
578 inc %edi /* first arg, 0->1(AUDITSC_SUCCESS), 1->2(AUDITSC_FAILURE) */ 578 inc %edi /* first arg, 0->1(AUDITSC_SUCCESS), 1->2(AUDITSC_FAILURE) */
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index a198b7c87a12..ba390d731175 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -964,7 +964,7 @@ fs_initcall(hpet_late_init);
964 964
965void hpet_disable(void) 965void hpet_disable(void)
966{ 966{
967 if (is_hpet_capable()) { 967 if (is_hpet_capable() && hpet_virt_address) {
968 unsigned int cfg = hpet_readl(HPET_CFG); 968 unsigned int cfg = hpet_readl(HPET_CFG);
969 969
970 if (hpet_legacy_int_enabled) { 970 if (hpet_legacy_int_enabled) {
diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c
index 7c9f02c130f3..cafa7c80ac95 100644
--- a/arch/x86/kernel/i8259.c
+++ b/arch/x86/kernel/i8259.c
@@ -276,16 +276,6 @@ static struct sys_device device_i8259A = {
276 .cls = &i8259_sysdev_class, 276 .cls = &i8259_sysdev_class,
277}; 277};
278 278
279static int __init i8259A_init_sysfs(void)
280{
281 int error = sysdev_class_register(&i8259_sysdev_class);
282 if (!error)
283 error = sysdev_register(&device_i8259A);
284 return error;
285}
286
287device_initcall(i8259A_init_sysfs);
288
289static void mask_8259A(void) 279static void mask_8259A(void)
290{ 280{
291 unsigned long flags; 281 unsigned long flags;
@@ -407,3 +397,18 @@ struct legacy_pic default_legacy_pic = {
407}; 397};
408 398
409struct legacy_pic *legacy_pic = &default_legacy_pic; 399struct legacy_pic *legacy_pic = &default_legacy_pic;
400
401static int __init i8259A_init_sysfs(void)
402{
403 int error;
404
405 if (legacy_pic != &default_legacy_pic)
406 return 0;
407
408 error = sysdev_class_register(&i8259_sysdev_class);
409 if (!error)
410 error = sysdev_register(&device_i8259A);
411 return error;
412}
413
414device_initcall(i8259A_init_sysfs);
diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c
index 345a4b1fe144..675879b65ce6 100644
--- a/arch/x86/kernel/kprobes.c
+++ b/arch/x86/kernel/kprobes.c
@@ -640,8 +640,8 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
640 /* Skip cs, ip, orig_ax and gs. */ \ 640 /* Skip cs, ip, orig_ax and gs. */ \
641 " subl $16, %esp\n" \ 641 " subl $16, %esp\n" \
642 " pushl %fs\n" \ 642 " pushl %fs\n" \
643 " pushl %ds\n" \
644 " pushl %es\n" \ 643 " pushl %es\n" \
644 " pushl %ds\n" \
645 " pushl %eax\n" \ 645 " pushl %eax\n" \
646 " pushl %ebp\n" \ 646 " pushl %ebp\n" \
647 " pushl %edi\n" \ 647 " pushl %edi\n" \
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index e72d3fc6547d..939b9e98245f 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -498,15 +498,10 @@ void force_hpet_resume(void)
498 * See erratum #27 (Misinterpreted MSI Requests May Result in 498 * See erratum #27 (Misinterpreted MSI Requests May Result in
499 * Corrupted LPC DMA Data) in AMD Publication #46837, 499 * Corrupted LPC DMA Data) in AMD Publication #46837,
500 * "SB700 Family Product Errata", Rev. 1.0, March 2010. 500 * "SB700 Family Product Errata", Rev. 1.0, March 2010.
501 *
502 * Also force the read back of the CMP register in hpet_next_event()
503 * to work around the problem that the CMP register write seems to be
504 * delayed. See hpet_next_event() for details.
505 */ 501 */
506static void force_disable_hpet_msi(struct pci_dev *unused) 502static void force_disable_hpet_msi(struct pci_dev *unused)
507{ 503{
508 hpet_msi_disable = 1; 504 hpet_msi_disable = 1;
509 hpet_readback_cmp = 1;
510} 505}
511 506
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index de3b63ae3da2..a60df9ae6454 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -238,6 +238,15 @@ void __init setup_per_cpu_areas(void)
238#ifdef CONFIG_NUMA 238#ifdef CONFIG_NUMA
239 per_cpu(x86_cpu_to_node_map, cpu) = 239 per_cpu(x86_cpu_to_node_map, cpu) =
240 early_per_cpu_map(x86_cpu_to_node_map, cpu); 240 early_per_cpu_map(x86_cpu_to_node_map, cpu);
241 /*
242 * Ensure that the boot cpu numa_node is correct when the boot
243 * cpu is on a node that doesn't have memory installed.
244 * Also cpu_up() will call cpu_to_node() for APs when
245 * MEMORY_HOTPLUG is defined, before per_cpu(numa_node) is set
246 * up later with c_init aka intel_init/amd_init.
247 * So set them all (boot cpu and all APs).
248 */
249 set_cpu_numa_node(cpu, early_cpu_to_node(cpu));
241#endif 250#endif
242#endif 251#endif
243 /* 252 /*
@@ -257,14 +266,6 @@ void __init setup_per_cpu_areas(void)
257 early_per_cpu_ptr(x86_cpu_to_node_map) = NULL; 266 early_per_cpu_ptr(x86_cpu_to_node_map) = NULL;
258#endif 267#endif
259 268
260#if defined(CONFIG_X86_64) && defined(CONFIG_NUMA)
261 /*
262 * make sure boot cpu numa_node is right, when boot cpu is on the
263 * node that doesn't have mem installed
264 */
265 set_cpu_numa_node(boot_cpu_id, early_cpu_to_node(boot_cpu_id));
266#endif
267
268 /* Setup node to cpumask map */ 269 /* Setup node to cpumask map */
269 setup_node_to_cpumask_map(); 270 setup_node_to_cpumask_map();
270 271
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 3699613e8830..b1ed0a1a5913 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -2926,7 +2926,7 @@ static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm)
2926 return kvm_mmu_zap_page(kvm, page) + 1; 2926 return kvm_mmu_zap_page(kvm, page) + 1;
2927} 2927}
2928 2928
2929static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask) 2929static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
2930{ 2930{
2931 struct kvm *kvm; 2931 struct kvm *kvm;
2932 struct kvm *kvm_freed = NULL; 2932 struct kvm *kvm_freed = NULL;
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 89d66ca4d87c..2331bdc2b549 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -342,6 +342,7 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
342 /* advance table_gfn when emulating 1gb pages with 4k */ 342 /* advance table_gfn when emulating 1gb pages with 4k */
343 if (delta == 0) 343 if (delta == 0)
344 table_gfn += PT_INDEX(addr, level); 344 table_gfn += PT_INDEX(addr, level);
345 access &= gw->pte_access;
345 } else { 346 } else {
346 direct = 0; 347 direct = 0;
347 table_gfn = gw->table_gfn[level - 2]; 348 table_gfn = gw->table_gfn[level - 2];
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 05d571f6f196..7fa89c39c64f 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1562,7 +1562,7 @@ static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1562 1562
1563 r = -ENOMEM; 1563 r = -ENOMEM;
1564 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 1564 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1565 entries = vmalloc(size); 1565 entries = kmalloc(size, GFP_KERNEL);
1566 if (!entries) 1566 if (!entries)
1567 goto out; 1567 goto out;
1568 1568
@@ -1581,7 +1581,7 @@ static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1581 r = n; 1581 r = n;
1582 1582
1583out_free: 1583out_free:
1584 vfree(entries); 1584 kfree(entries);
1585out: 1585out:
1586 return r; 1586 return r;
1587} 1587}
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 6fdb3ec30c31..55253095be84 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -184,6 +184,7 @@ static void __init pcibios_allocate_resources(int pass)
184 idx, r, disabled, pass); 184 idx, r, disabled, pass);
185 if (pci_claim_resource(dev, idx) < 0) { 185 if (pci_claim_resource(dev, idx) < 0) {
186 /* We'll assign a new address later */ 186 /* We'll assign a new address later */
187 dev->fw_addr[idx] = r->start;
187 r->end -= r->start; 188 r->end -= r->start;
188 r->start = 0; 189 r->start = 0;
189 } 190 }
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index 7ef3a2735df3..cb29191cee58 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -66,8 +66,9 @@ static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
66 devfn, pos, 4, &pcie_cap)) 66 devfn, pos, 4, &pcie_cap))
67 return 0; 67 return 0;
68 68
69 if (pcie_cap == 0xffffffff) 69 if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
70 return 0; 70 PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
71 break;
71 72
72 if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) { 73 if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
73 raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, 74 raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
@@ -76,7 +77,7 @@ static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
76 return pos; 77 return pos;
77 } 78 }
78 79
79 pos = pcie_cap >> 20; 80 pos = PCI_EXT_CAP_NEXT(pcie_cap);
80 } 81 }
81 82
82 return 0; 83 return 0;