diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-12-18 15:34:29 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-12-18 15:34:29 -0500 |
commit | 6842d98de7bb726dfddc719cb9ae022b26a0f2b8 (patch) | |
tree | 73c42dbbd09dc6697c601f23a9be3ccdbc54664b /arch/x86 | |
parent | 758338e960ebe8ac3bef7ae11ff830bc2f9c655c (diff) | |
parent | 55f1f545f709a6023371848028a3029118855576 (diff) |
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux
Pull powertool update from Len Brown:
"This updates the tree w/ the latest version of turbostat, which
reports temperature and - on SNB and later - Watts."
Fix up semantic merge conflict as per Len.
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux:
tools: Allow tools to be installed in a user specified location
tools/power: turbostat: make Makefile a bit more capable
tools/power x86_energy_perf_policy: close /proc/stat in for_every_cpu()
tools/power turbostat: v3.0: monitor Watts and Temperature
tools/power turbostat: fix output buffering issue
tools/power turbostat: prevent infinite loop on migration error path
x86 power: define RAPL MSRs
tools/power/x86/turbostat: share kernel MSR #defines
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index 6e930b218724..433a59fb1a74 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h | |||
@@ -35,11 +35,14 @@ | |||
35 | #define MSR_IA32_PERFCTR0 0x000000c1 | 35 | #define MSR_IA32_PERFCTR0 0x000000c1 |
36 | #define MSR_IA32_PERFCTR1 0x000000c2 | 36 | #define MSR_IA32_PERFCTR1 0x000000c2 |
37 | #define MSR_FSB_FREQ 0x000000cd | 37 | #define MSR_FSB_FREQ 0x000000cd |
38 | #define MSR_NHM_PLATFORM_INFO 0x000000ce | ||
38 | 39 | ||
39 | #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 | 40 | #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 |
40 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) | 41 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) |
41 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) | 42 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) |
42 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) | 43 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
44 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) | ||
45 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) | ||
43 | 46 | ||
44 | #define MSR_MTRRcap 0x000000fe | 47 | #define MSR_MTRRcap 0x000000fe |
45 | #define MSR_IA32_BBL_CR_CTL 0x00000119 | 48 | #define MSR_IA32_BBL_CR_CTL 0x00000119 |
@@ -55,6 +58,8 @@ | |||
55 | 58 | ||
56 | #define MSR_OFFCORE_RSP_0 0x000001a6 | 59 | #define MSR_OFFCORE_RSP_0 0x000001a6 |
57 | #define MSR_OFFCORE_RSP_1 0x000001a7 | 60 | #define MSR_OFFCORE_RSP_1 0x000001a7 |
61 | #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad | ||
62 | #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae | ||
58 | 63 | ||
59 | #define MSR_LBR_SELECT 0x000001c8 | 64 | #define MSR_LBR_SELECT 0x000001c8 |
60 | #define MSR_LBR_TOS 0x000001c9 | 65 | #define MSR_LBR_TOS 0x000001c9 |
@@ -103,6 +108,38 @@ | |||
103 | #define MSR_IA32_MC0_ADDR 0x00000402 | 108 | #define MSR_IA32_MC0_ADDR 0x00000402 |
104 | #define MSR_IA32_MC0_MISC 0x00000403 | 109 | #define MSR_IA32_MC0_MISC 0x00000403 |
105 | 110 | ||
111 | /* C-state Residency Counters */ | ||
112 | #define MSR_PKG_C3_RESIDENCY 0x000003f8 | ||
113 | #define MSR_PKG_C6_RESIDENCY 0x000003f9 | ||
114 | #define MSR_PKG_C7_RESIDENCY 0x000003fa | ||
115 | #define MSR_CORE_C3_RESIDENCY 0x000003fc | ||
116 | #define MSR_CORE_C6_RESIDENCY 0x000003fd | ||
117 | #define MSR_CORE_C7_RESIDENCY 0x000003fe | ||
118 | #define MSR_PKG_C2_RESIDENCY 0x0000060d | ||
119 | |||
120 | /* Run Time Average Power Limiting (RAPL) Interface */ | ||
121 | |||
122 | #define MSR_RAPL_POWER_UNIT 0x00000606 | ||
123 | |||
124 | #define MSR_PKG_POWER_LIMIT 0x00000610 | ||
125 | #define MSR_PKG_ENERGY_STATUS 0x00000611 | ||
126 | #define MSR_PKG_PERF_STATUS 0x00000613 | ||
127 | #define MSR_PKG_POWER_INFO 0x00000614 | ||
128 | |||
129 | #define MSR_DRAM_POWER_LIMIT 0x00000618 | ||
130 | #define MSR_DRAM_ENERGY_STATUS 0x00000619 | ||
131 | #define MSR_DRAM_PERF_STATUS 0x0000061b | ||
132 | #define MSR_DRAM_POWER_INFO 0x0000061c | ||
133 | |||
134 | #define MSR_PP0_POWER_LIMIT 0x00000638 | ||
135 | #define MSR_PP0_ENERGY_STATUS 0x00000639 | ||
136 | #define MSR_PP0_POLICY 0x0000063a | ||
137 | #define MSR_PP0_PERF_STATUS 0x0000063b | ||
138 | |||
139 | #define MSR_PP1_POWER_LIMIT 0x00000640 | ||
140 | #define MSR_PP1_ENERGY_STATUS 0x00000641 | ||
141 | #define MSR_PP1_POLICY 0x00000642 | ||
142 | |||
106 | #define MSR_AMD64_MC0_MASK 0xc0010044 | 143 | #define MSR_AMD64_MC0_MASK 0xc0010044 |
107 | 144 | ||
108 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) | 145 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |