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authorGary Hade <garyhade@us.ibm.com>2007-10-03 18:56:51 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2007-10-12 18:03:18 -0400
commit62f420f828249f686aaae949ac3439d1304a759a (patch)
tree0cc534ad4971b9155a23b46c43597d5b5dd9d548 /arch/x86/pci/pci.h
parentfd64cb4606cbdd592b7119e82341d4ae5b56f2cc (diff)
PCI: use _CRS for PCI resource allocation
Use _CRS for PCI resource allocation This patch resolves an issue where incorrect PCI memory and i/o ranges are being assigned to hotplugged PCI devices on some IBM systems. The resource mis-allocation not only makes the PCI device unuseable but often makes the entire system unuseable due to resulting machine checks. The hotplug capable PCI slots on the affected systems are not located under a standard P2P bridge but are instead located under PCI root bridges or subtractive decode P2P bridges. For example, the IBM x3850 contains 2 hotplug capable PCI-X slots and 4 hotplug capable PCIe slots with the PCI-X slots each located under a PCI root bridge and the PCIe slots each located under a subtractive decode P2P bridge. The current i386/x86_64 PCI resource allocation code does not use _CRS returned resource information. No other resource information source is available for slots that are not below a standard P2P bridge so incorrect ranges are being allocated from e820 hole causing the bad result. This patch causes the kernel to use _CRS returned resource info. It is roughly based on a change provided by Matthew Wilcox for the ia64 kernel in 2005. Due to possible buggy BIOS factor and possible yet to be discovered kernel issues the function is disabled by default and can be enabled with pci=use_crs. Signed-off-by: Gary Hade <gary.hade@us.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch/x86/pci/pci.h')
-rw-r--r--arch/x86/pci/pci.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/pci/pci.h b/arch/x86/pci/pci.h
index 057f335fa3f6..ac56d3916c50 100644
--- a/arch/x86/pci/pci.h
+++ b/arch/x86/pci/pci.h
@@ -27,6 +27,7 @@
27#define PCI_BIOS_IRQ_SCAN 0x2000 27#define PCI_BIOS_IRQ_SCAN 0x2000
28#define PCI_ASSIGN_ALL_BUSSES 0x4000 28#define PCI_ASSIGN_ALL_BUSSES 0x4000
29#define PCI_CAN_SKIP_ISA_ALIGN 0x8000 29#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
30#define PCI_USE__CRS 0x10000
30 31
31extern unsigned int pci_probe; 32extern unsigned int pci_probe;
32extern unsigned long pirq_table_addr; 33extern unsigned long pirq_table_addr;