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authorDavidlohr Bueso <dave@gnu.org>2012-03-05 10:53:06 -0500
committerAvi Kivity <avi@redhat.com>2012-03-08 07:13:54 -0500
commit4d6931c380a976753f7566a96b58690010ef1413 (patch)
treed50e46205a6aa1b2a72a2e33f6e5363faec40e3b /arch/x86/kvm/mmu.c
parent62079d8a431287a4da81db64e002c71f0e06ca83 (diff)
KVM: MMU: make use of ->root_level in reset_rsvds_bits_mask
The reset_rsvds_bits_mask() function can use the guest walker's root level number instead of using a separate 'level' variable. Signed-off-by: Davidlohr Bueso <dave@gnu.org> Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'arch/x86/kvm/mmu.c')
-rw-r--r--arch/x86/kvm/mmu.c31
1 files changed, 15 insertions, 16 deletions
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index ff053ca32303..4cb164268846 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -3185,15 +3185,14 @@ static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3185#undef PTTYPE 3185#undef PTTYPE
3186 3186
3187static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, 3187static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3188 struct kvm_mmu *context, 3188 struct kvm_mmu *context)
3189 int level)
3190{ 3189{
3191 int maxphyaddr = cpuid_maxphyaddr(vcpu); 3190 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3192 u64 exb_bit_rsvd = 0; 3191 u64 exb_bit_rsvd = 0;
3193 3192
3194 if (!context->nx) 3193 if (!context->nx)
3195 exb_bit_rsvd = rsvd_bits(63, 63); 3194 exb_bit_rsvd = rsvd_bits(63, 63);
3196 switch (level) { 3195 switch (context->root_level) {
3197 case PT32_ROOT_LEVEL: 3196 case PT32_ROOT_LEVEL:
3198 /* no rsvd bits for 2 level 4K page table entries */ 3197 /* no rsvd bits for 2 level 4K page table entries */
3199 context->rsvd_bits_mask[0][1] = 0; 3198 context->rsvd_bits_mask[0][1] = 0;
@@ -3251,8 +3250,9 @@ static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3251 int level) 3250 int level)
3252{ 3251{
3253 context->nx = is_nx(vcpu); 3252 context->nx = is_nx(vcpu);
3253 context->root_level = level;
3254 3254
3255 reset_rsvds_bits_mask(vcpu, context, level); 3255 reset_rsvds_bits_mask(vcpu, context);
3256 3256
3257 ASSERT(is_pae(vcpu)); 3257 ASSERT(is_pae(vcpu));
3258 context->new_cr3 = paging_new_cr3; 3258 context->new_cr3 = paging_new_cr3;
@@ -3262,7 +3262,6 @@ static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3262 context->invlpg = paging64_invlpg; 3262 context->invlpg = paging64_invlpg;
3263 context->update_pte = paging64_update_pte; 3263 context->update_pte = paging64_update_pte;
3264 context->free = paging_free; 3264 context->free = paging_free;
3265 context->root_level = level;
3266 context->shadow_root_level = level; 3265 context->shadow_root_level = level;
3267 context->root_hpa = INVALID_PAGE; 3266 context->root_hpa = INVALID_PAGE;
3268 context->direct_map = false; 3267 context->direct_map = false;
@@ -3279,8 +3278,9 @@ static int paging32_init_context(struct kvm_vcpu *vcpu,
3279 struct kvm_mmu *context) 3278 struct kvm_mmu *context)
3280{ 3279{
3281 context->nx = false; 3280 context->nx = false;
3281 context->root_level = PT32_ROOT_LEVEL;
3282 3282
3283 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); 3283 reset_rsvds_bits_mask(vcpu, context);
3284 3284
3285 context->new_cr3 = paging_new_cr3; 3285 context->new_cr3 = paging_new_cr3;
3286 context->page_fault = paging32_page_fault; 3286 context->page_fault = paging32_page_fault;
@@ -3289,7 +3289,6 @@ static int paging32_init_context(struct kvm_vcpu *vcpu,
3289 context->sync_page = paging32_sync_page; 3289 context->sync_page = paging32_sync_page;
3290 context->invlpg = paging32_invlpg; 3290 context->invlpg = paging32_invlpg;
3291 context->update_pte = paging32_update_pte; 3291 context->update_pte = paging32_update_pte;
3292 context->root_level = PT32_ROOT_LEVEL;
3293 context->shadow_root_level = PT32E_ROOT_LEVEL; 3292 context->shadow_root_level = PT32E_ROOT_LEVEL;
3294 context->root_hpa = INVALID_PAGE; 3293 context->root_hpa = INVALID_PAGE;
3295 context->direct_map = false; 3294 context->direct_map = false;
@@ -3327,19 +3326,19 @@ static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3327 context->root_level = 0; 3326 context->root_level = 0;
3328 } else if (is_long_mode(vcpu)) { 3327 } else if (is_long_mode(vcpu)) {
3329 context->nx = is_nx(vcpu); 3328 context->nx = is_nx(vcpu);
3330 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
3331 context->gva_to_gpa = paging64_gva_to_gpa;
3332 context->root_level = PT64_ROOT_LEVEL; 3329 context->root_level = PT64_ROOT_LEVEL;
3330 reset_rsvds_bits_mask(vcpu, context);
3331 context->gva_to_gpa = paging64_gva_to_gpa;
3333 } else if (is_pae(vcpu)) { 3332 } else if (is_pae(vcpu)) {
3334 context->nx = is_nx(vcpu); 3333 context->nx = is_nx(vcpu);
3335 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
3336 context->gva_to_gpa = paging64_gva_to_gpa;
3337 context->root_level = PT32E_ROOT_LEVEL; 3334 context->root_level = PT32E_ROOT_LEVEL;
3335 reset_rsvds_bits_mask(vcpu, context);
3336 context->gva_to_gpa = paging64_gva_to_gpa;
3338 } else { 3337 } else {
3339 context->nx = false; 3338 context->nx = false;
3340 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3341 context->gva_to_gpa = paging32_gva_to_gpa;
3342 context->root_level = PT32_ROOT_LEVEL; 3339 context->root_level = PT32_ROOT_LEVEL;
3340 reset_rsvds_bits_mask(vcpu, context);
3341 context->gva_to_gpa = paging32_gva_to_gpa;
3343 } 3342 }
3344 3343
3345 return 0; 3344 return 0;
@@ -3402,18 +3401,18 @@ static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3402 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; 3401 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3403 } else if (is_long_mode(vcpu)) { 3402 } else if (is_long_mode(vcpu)) {
3404 g_context->nx = is_nx(vcpu); 3403 g_context->nx = is_nx(vcpu);
3405 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3406 g_context->root_level = PT64_ROOT_LEVEL; 3404 g_context->root_level = PT64_ROOT_LEVEL;
3405 reset_rsvds_bits_mask(vcpu, g_context);
3407 g_context->gva_to_gpa = paging64_gva_to_gpa_nested; 3406 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3408 } else if (is_pae(vcpu)) { 3407 } else if (is_pae(vcpu)) {
3409 g_context->nx = is_nx(vcpu); 3408 g_context->nx = is_nx(vcpu);
3410 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3411 g_context->root_level = PT32E_ROOT_LEVEL; 3409 g_context->root_level = PT32E_ROOT_LEVEL;
3410 reset_rsvds_bits_mask(vcpu, g_context);
3412 g_context->gva_to_gpa = paging64_gva_to_gpa_nested; 3411 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3413 } else { 3412 } else {
3414 g_context->nx = false; 3413 g_context->nx = false;
3415 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3416 g_context->root_level = PT32_ROOT_LEVEL; 3414 g_context->root_level = PT32_ROOT_LEVEL;
3415 reset_rsvds_bits_mask(vcpu, g_context);
3417 g_context->gva_to_gpa = paging32_gva_to_gpa_nested; 3416 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3418 } 3417 }
3419 3418