Merge tag 'v3.6-rc6' into x86/mce

Merge Linux v3.6-rc6, to refresh this tree.

Signed-off-by: Ingo Molnar <mingo@kernel.org>

2 files changed, 40 insertions, 10 deletions

diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index 413c2ced887c..13017626f9a8 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -55,13 +55,6 @@ static struct severity {
 #define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
 #define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
 #define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV)
-#define MCACOD 0xffff
-/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
-#define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
-#define MCACOD_SCRUBMSK 0xfff0
-#define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
-#define MCACOD_DATA     0x0134  /* Data Load */
-#define MCACOD_INSTR    0x0150  /* Instruction Fetch */
 
         MCESEV(
                 NO, "Invalid",
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 8c1beea6cabf..c311122ea838 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -103,6 +103,8 @@ DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
 
 static DEFINE_PER_CPU(struct work_struct, mce_work);
 
+static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
+
 /*
  * CPU/chipset specific EDAC code can register a notifier call here to print
  * MCE errors in a human-readable form.
@@ -650,14 +652,18 @@ EXPORT_SYMBOL_GPL(machine_check_poll);
  * Do a quick check if any of the events requires a panic.
  * This decides if we keep the events around or clear them.
  */
-static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp)
+static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
+                          struct pt_regs *regs)
 {
         int i, ret = 0;
 
         for (i = 0; i < banks; i++) {
                 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
-                if (m->status & MCI_STATUS_VAL)
+                if (m->status & MCI_STATUS_VAL) {
                         __set_bit(i, validp);
+                        if (quirk_no_way_out)
+                                quirk_no_way_out(i, m, regs);
+                }
                 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
                         ret = 1;
         }
@@ -1040,7 +1046,7 @@ void do_machine_check(struct pt_regs *regs, long error_code)
         *final = m;
 
         memset(valid_banks, 0, sizeof(valid_banks));
-        no_way_out = mce_no_way_out(&m, &msg, valid_banks);
+        no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
 
         barrier();
 
@@ -1451,6 +1457,34 @@ static void __mcheck_cpu_init_generic(void)
         }
 }
 
+/*
+ * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
+ * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
+ * Vol 3B Table 15-20). But this confuses both the code that determines
+ * whether the machine check occurred in kernel or user mode, and also
+ * the severity assessment code. Pretend that EIPV was set, and take the
+ * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
+ */
+static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
+{
+        if (bank != 0)
+                return;
+        if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
+                return;
+        if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
+                          MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
+                          MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
+                          MCACOD)) !=
+                         (MCI_STATUS_UC|MCI_STATUS_EN|
+                          MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
+                          MCI_STATUS_AR|MCACOD_INSTR))
+                return;
+
+        m->mcgstatus |= MCG_STATUS_EIPV;
+        m->ip = regs->ip;
+        m->cs = regs->cs;
+}
+
 /* Add per CPU specific workarounds here */
 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
 {
@@ -1548,6 +1582,9 @@ static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
                  */
                 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
                         mce_bootlog = 0;
+
+                if (c->x86 == 6 && c->x86_model == 45)
+                        quirk_no_way_out = quirk_sandybridge_ifu;
         }
         if (monarch_timeout < 0)
                 monarch_timeout = 0;