[SPARC64]: Elminate all usage of hard-coded trap globals.

UltraSPARC has special sets of global registers which are switched to
for certain trap types.  There is one set for MMU related traps, one
set of Interrupt Vector processing, and another set (called the
Alternate globals) for all other trap types.

For what seems like forever we've hard coded the values in some of
these trap registers.  Some examples include:

1) Interrupt Vector global %g6 holds current processors interrupt
   work struct where received interrupts are managed for IRQ handler
   dispatch.

2) MMU global %g7 holds the base of the page tables of the currently
   active address space.

3) Alternate global %g6 held the current_thread_info() value.

Such hardcoding has resulted in some serious issues in many areas.
There are some code sequences where having another register available
would help clean up the implementation.  Taking traps such as
cross-calls from the OBP firmware requires some trick code sequences
wherein we have to save away and restore all of the special sets of
global registers when we enter/exit OBP.

We were also using the IMMU TSB register on SMP to hold the per-cpu
area base address, which doesn't work any longer now that we actually
use the TSB facility of the cpu.

The implementation is pretty straight forward.  One tricky bit is
getting the current processor ID as that is different on different cpu
variants.  We use a stub with a fancy calling convention which we
patch at boot time.  The calling convention is that the stub is
branched to and the (PC - 4) to return to is in register %g1.  The cpu
number is left in %g6.  This stub can be invoked by using the
__GET_CPUID macro.

We use an array of per-cpu trap state to store the current thread and
physical address of the current address space's page tables.  The
TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this
table, it uses __GET_CPUID and also clobbers %g1.

TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load
the current processor's IRQ software state into %g6.  It also uses
__GET_CPUID and clobbers %g1.

Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the
current address space's page tables into %g7, it clobbers %g1 and uses
__GET_CPUID.

Many refinements are possible, as well as some tuning, with this stuff
in place.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 20 insertions, 6 deletions

diff --git a/arch/sparc64/kernel/tsb.S b/arch/sparc64/kernel/tsb.S
index 44b9e6fed09f..50752c518773 100644
--- a/arch/sparc64/kernel/tsb.S
+++ b/arch/sparc64/kernel/tsb.S
@@ -36,6 +36,15 @@ tsb_miss_itlb:
          nop
 
 tsb_miss_page_table_walk:
+        /* This clobbers %g1 and %g6, preserve them... */
+        mov             %g1, %g5
+        mov             %g6, %g2
+
+        TRAP_LOAD_PGD_PHYS
+
+        mov             %g2, %g6
+        mov             %g5, %g1
+
         USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
 
 tsb_reload:
@@ -112,15 +121,20 @@ winfix_trampoline:
          * %o0: page table physical address
          * %o1: TSB address
          */
+        .align  32
         .globl  tsb_context_switch
 tsb_context_switch:
-        wrpr    %g0, PSTATE_MG | PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV, %pstate
+        rdpr    %pstate, %o5
+        wrpr    %o5, PSTATE_IE, %pstate
 
-        /* Set page table base alternate global.  */
-        mov     %o0, %g7
+        ldub    [%g6 + TI_CPU], %o3
+        sethi   %hi(trap_block), %o4
+        sllx    %o3, TRAP_BLOCK_SZ_SHIFT, %o3
+        or      %o4, %lo(trap_block), %o4
+        add     %o4, %o3, %o4
+        stx     %o0, [%o4 + TRAP_PER_CPU_PGD_PADDR]
 
-        /* XXX can this happen?  */
-        brz,pn  %o1, 9f
+        brgez   %o1, 9f
          nop
 
         /* Lock TSB into D-TLB.  */
@@ -163,7 +177,7 @@ tsb_context_switch:
         membar          #Sync
 
 9:
-        wrpr    %g0, PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE, %pstate
+        wrpr    %o5, %pstate
 
         retl
          mov    %o2, %o0