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authorPaul Mundt <lethal@linux-sh.org>2011-01-13 01:06:28 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-01-13 01:06:28 -0500
commitf43dc23d5ea91fca257be02138a255f02d98e806 (patch)
treeb29722f6e965316e90ac97abf79923ced250dc21 /arch/sh/kernel/cpu/sh4a/setup-sh7343.c
parentf8e53553f452dcbf67cb89c8cba63a1cd6eb4cc0 (diff)
parent4162cf64973df51fc885825bc9ca4d055891c49f (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into common/serial-rework
Conflicts: arch/sh/kernel/cpu/sh2/setup-sh7619.c arch/sh/kernel/cpu/sh2a/setup-mxg.c arch/sh/kernel/cpu/sh2a/setup-sh7201.c arch/sh/kernel/cpu/sh2a/setup-sh7203.c arch/sh/kernel/cpu/sh2a/setup-sh7206.c arch/sh/kernel/cpu/sh3/setup-sh7705.c arch/sh/kernel/cpu/sh3/setup-sh770x.c arch/sh/kernel/cpu/sh3/setup-sh7710.c arch/sh/kernel/cpu/sh3/setup-sh7720.c arch/sh/kernel/cpu/sh4/setup-sh4-202.c arch/sh/kernel/cpu/sh4/setup-sh7750.c arch/sh/kernel/cpu/sh4/setup-sh7760.c arch/sh/kernel/cpu/sh4a/setup-sh7343.c arch/sh/kernel/cpu/sh4a/setup-sh7366.c arch/sh/kernel/cpu/sh4a/setup-sh7722.c arch/sh/kernel/cpu/sh4a/setup-sh7723.c arch/sh/kernel/cpu/sh4a/setup-sh7724.c arch/sh/kernel/cpu/sh4a/setup-sh7763.c arch/sh/kernel/cpu/sh4a/setup-sh7770.c arch/sh/kernel/cpu/sh4a/setup-sh7780.c arch/sh/kernel/cpu/sh4a/setup-sh7785.c arch/sh/kernel/cpu/sh4a/setup-sh7786.c arch/sh/kernel/cpu/sh4a/setup-shx3.c arch/sh/kernel/cpu/sh5/setup-sh5.c drivers/serial/sh-sci.c drivers/serial/sh-sci.h include/linux/serial_sci.h
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7343.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c138
1 files changed, 78 insertions, 60 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index fbae06b1c98d..0d1be5d1fb86 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -15,6 +15,75 @@
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <asm/clock.h> 16#include <asm/clock.h>
17 17
18/* Serial */
19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe00000,
21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF,
25 .irqs = { 80, 80, 80, 80 },
26};
27
28static struct platform_device scif0_device = {
29 .name = "sh-sci",
30 .id = 0,
31 .dev = {
32 .platform_data = &scif0_platform_data,
33 },
34};
35
36static struct plat_sci_port scif1_platform_data = {
37 .mapbase = 0xffe10000,
38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
40 .scbrr_algo_id = SCBRR_ALGO_2,
41 .type = PORT_SCIF,
42 .irqs = { 81, 81, 81, 81 },
43};
44
45static struct platform_device scif1_device = {
46 .name = "sh-sci",
47 .id = 1,
48 .dev = {
49 .platform_data = &scif1_platform_data,
50 },
51};
52
53static struct plat_sci_port scif2_platform_data = {
54 .mapbase = 0xffe20000,
55 .flags = UPF_BOOT_AUTOCONF,
56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
57 .scbrr_algo_id = SCBRR_ALGO_2,
58 .type = PORT_SCIF,
59 .irqs = { 82, 82, 82, 82 },
60};
61
62static struct platform_device scif2_device = {
63 .name = "sh-sci",
64 .id = 2,
65 .dev = {
66 .platform_data = &scif2_platform_data,
67 },
68};
69
70static struct plat_sci_port scif3_platform_data = {
71 .mapbase = 0xffe30000,
72 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
74 .scbrr_algo_id = SCBRR_ALGO_2,
75 .type = PORT_SCIF,
76 .irqs = { 83, 83, 83, 83 },
77};
78
79static struct platform_device scif3_device = {
80 .name = "sh-sci",
81 .id = 3,
82 .dev = {
83 .platform_data = &scif3_platform_data,
84 },
85};
86
18static struct resource iic0_resources[] = { 87static struct resource iic0_resources[] = {
19 [0] = { 88 [0] = {
20 .name = "IIC0", 89 .name = "IIC0",
@@ -142,17 +211,14 @@ static struct platform_device jpu_device = {
142}; 211};
143 212
144static struct sh_timer_config cmt_platform_data = { 213static struct sh_timer_config cmt_platform_data = {
145 .name = "CMT",
146 .channel_offset = 0x60, 214 .channel_offset = 0x60,
147 .timer_bit = 5, 215 .timer_bit = 5,
148 .clk = "cmt0",
149 .clockevent_rating = 125, 216 .clockevent_rating = 125,
150 .clocksource_rating = 200, 217 .clocksource_rating = 200,
151}; 218};
152 219
153static struct resource cmt_resources[] = { 220static struct resource cmt_resources[] = {
154 [0] = { 221 [0] = {
155 .name = "CMT",
156 .start = 0x044a0060, 222 .start = 0x044a0060,
157 .end = 0x044a006b, 223 .end = 0x044a006b,
158 .flags = IORESOURCE_MEM, 224 .flags = IORESOURCE_MEM,
@@ -174,16 +240,13 @@ static struct platform_device cmt_device = {
174}; 240};
175 241
176static struct sh_timer_config tmu0_platform_data = { 242static struct sh_timer_config tmu0_platform_data = {
177 .name = "TMU0",
178 .channel_offset = 0x04, 243 .channel_offset = 0x04,
179 .timer_bit = 0, 244 .timer_bit = 0,
180 .clk = "tmu0",
181 .clockevent_rating = 200, 245 .clockevent_rating = 200,
182}; 246};
183 247
184static struct resource tmu0_resources[] = { 248static struct resource tmu0_resources[] = {
185 [0] = { 249 [0] = {
186 .name = "TMU0",
187 .start = 0xffd80008, 250 .start = 0xffd80008,
188 .end = 0xffd80013, 251 .end = 0xffd80013,
189 .flags = IORESOURCE_MEM, 252 .flags = IORESOURCE_MEM,
@@ -205,16 +268,13 @@ static struct platform_device tmu0_device = {
205}; 268};
206 269
207static struct sh_timer_config tmu1_platform_data = { 270static struct sh_timer_config tmu1_platform_data = {
208 .name = "TMU1",
209 .channel_offset = 0x10, 271 .channel_offset = 0x10,
210 .timer_bit = 1, 272 .timer_bit = 1,
211 .clk = "tmu0",
212 .clocksource_rating = 200, 273 .clocksource_rating = 200,
213}; 274};
214 275
215static struct resource tmu1_resources[] = { 276static struct resource tmu1_resources[] = {
216 [0] = { 277 [0] = {
217 .name = "TMU1",
218 .start = 0xffd80014, 278 .start = 0xffd80014,
219 .end = 0xffd8001f, 279 .end = 0xffd8001f,
220 .flags = IORESOURCE_MEM, 280 .flags = IORESOURCE_MEM,
@@ -236,15 +296,12 @@ static struct platform_device tmu1_device = {
236}; 296};
237 297
238static struct sh_timer_config tmu2_platform_data = { 298static struct sh_timer_config tmu2_platform_data = {
239 .name = "TMU2",
240 .channel_offset = 0x1c, 299 .channel_offset = 0x1c,
241 .timer_bit = 2, 300 .timer_bit = 2,
242 .clk = "tmu0",
243}; 301};
244 302
245static struct resource tmu2_resources[] = { 303static struct resource tmu2_resources[] = {
246 [0] = { 304 [0] = {
247 .name = "TMU2",
248 .start = 0xffd80020, 305 .start = 0xffd80020,
249 .end = 0xffd8002b, 306 .end = 0xffd8002b,
250 .flags = IORESOURCE_MEM, 307 .flags = IORESOURCE_MEM,
@@ -265,60 +322,17 @@ static struct platform_device tmu2_device = {
265 .num_resources = ARRAY_SIZE(tmu2_resources), 322 .num_resources = ARRAY_SIZE(tmu2_resources),
266}; 323};
267 324
268static struct plat_sci_port sci_platform_data[] = {
269 {
270 .mapbase = 0xffe00000,
271 .flags = UPF_BOOT_AUTOCONF,
272 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
273 .scbrr_algo_id = SCBRR_ALGO_2,
274 .type = PORT_SCIF,
275 .irqs = { 80, 80, 80, 80 },
276 .clk = "scif0",
277 }, {
278 .mapbase = 0xffe10000,
279 .flags = UPF_BOOT_AUTOCONF,
280 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
281 .scbrr_algo_id = SCBRR_ALGO_2,
282 .type = PORT_SCIF,
283 .irqs = { 81, 81, 81, 81 },
284 .clk = "scif1",
285 }, {
286 .mapbase = 0xffe20000,
287 .flags = UPF_BOOT_AUTOCONF,
288 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
289 .scbrr_algo_id = SCBRR_ALGO_2,
290 .type = PORT_SCIF,
291 .irqs = { 82, 82, 82, 82 },
292 .clk = "scif2",
293 }, {
294 .mapbase = 0xffe30000,
295 .flags = UPF_BOOT_AUTOCONF,
296 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
297 .scbrr_algo_id = SCBRR_ALGO_2,
298 .type = PORT_SCIF,
299 .irqs = { 83, 83, 83, 83 },
300 .clk = "scif3",
301 }, {
302 .flags = 0,
303 }
304};
305
306static struct platform_device sci_device = {
307 .name = "sh-sci",
308 .id = -1,
309 .dev = {
310 .platform_data = sci_platform_data,
311 },
312};
313
314static struct platform_device *sh7343_devices[] __initdata = { 325static struct platform_device *sh7343_devices[] __initdata = {
326 &scif0_device,
327 &scif1_device,
328 &scif2_device,
329 &scif3_device,
315 &cmt_device, 330 &cmt_device,
316 &tmu0_device, 331 &tmu0_device,
317 &tmu1_device, 332 &tmu1_device,
318 &tmu2_device, 333 &tmu2_device,
319 &iic0_device, 334 &iic0_device,
320 &iic1_device, 335 &iic1_device,
321 &sci_device,
322 &vpu_device, 336 &vpu_device,
323 &veu_device, 337 &veu_device,
324 &jpu_device, 338 &jpu_device,
@@ -333,9 +347,13 @@ static int __init sh7343_devices_setup(void)
333 return platform_add_devices(sh7343_devices, 347 return platform_add_devices(sh7343_devices,
334 ARRAY_SIZE(sh7343_devices)); 348 ARRAY_SIZE(sh7343_devices));
335} 349}
336__initcall(sh7343_devices_setup); 350arch_initcall(sh7343_devices_setup);
337 351
338static struct platform_device *sh7343_early_devices[] __initdata = { 352static struct platform_device *sh7343_early_devices[] __initdata = {
353 &scif0_device,
354 &scif1_device,
355 &scif2_device,
356 &scif3_device,
339 &cmt_device, 357 &cmt_device,
340 &tmu0_device, 358 &tmu0_device,
341 &tmu1_device, 359 &tmu1_device,
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-15 18:25:05 -0400