[S390] add support for compressed kernels

Add the "bzImage" compile target and the necessary code  to generate
compressed kernel images. The old style uncompressed "image" target
is preserved, a simple make will build them both.

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>

5 files changed, 78 insertions, 40 deletions

diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile
index 20f861256774..64230bc392fa 100644
--- a/arch/s390/kernel/Makefile
+++ b/arch/s390/kernel/Makefile
@@ -29,6 +29,7 @@ obj-y	+= $(if $(CONFIG_64BIT),entry64.o,entry.o)
 obj-y   += $(if $(CONFIG_64BIT),reipl64.o,reipl.o)
 
 extra-y                         += head.o init_task.o vmlinux.lds
+extra-y                         += $(if $(CONFIG_64BIT),head64.o,head31.o)
 
 obj-$(CONFIG_MODULES)           += s390_ksyms.o module.o
 obj-$(CONFIG_SMP)               += smp.o topology.o
diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S
index 1fb59055c7ca..ca4a62bd862f 100644
--- a/arch/s390/kernel/head.S
+++ b/arch/s390/kernel/head.S
@@ -1,5 +1,5 @@
 /*
- * Copyright IBM Corp. 1999,2009
+ * Copyright IBM Corp. 1999,2010
  *
  *    Author(s): Hartmut Penner <hp@de.ibm.com>
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>
@@ -22,11 +22,9 @@
  */
 
 #include <linux/init.h>
-#include <asm/setup.h>
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
 #include <asm/page.h>
-#include <asm/cpu.h>
 
 #ifdef CONFIG_64BIT
 #define ARCH_OFFSET     4
@@ -450,16 +448,15 @@ start:
 # or linload or SALIPL
 #
         .org    0x10000
-startup:basr    %r13,0                  # get base
+        .globl  startup
+startup:
+        basr    %r13,0                  # get base
 .LPG0:
         xc      0x200(256),0x200        # partially clear lowcore
         xc      0x300(256),0x300
-        l       %r1,5f-.LPG0(%r13)
-        stck    0(%r1)
-        spt     6f-.LPG0(%r13)
-        mvc     __LC_LAST_UPDATE_CLOCK(8),0(%r1)
-        mvc     __LC_LAST_UPDATE_TIMER(8),6f-.LPG0(%r13)
-        mvc     __LC_EXIT_TIMER(8),5f-.LPG0(%r13)
+        stck    __LC_LAST_UPDATE_CLOCK
+        spt     5f-.LPG0(%r13)
+        mvc     __LC_LAST_UPDATE_TIMER(8),5f-.LPG0(%r13)
 #ifndef CONFIG_MARCH_G5
         # check capabilities against MARCH_{G5,Z900,Z990,Z9_109,Z10}
         xc      __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST
@@ -477,7 +474,6 @@ startup:basr	%r13,0			# get base
         cl      %r0,2f+12-.LPG0(%r13)
         je      3f
 1:      l       %r15,.Lstack-.LPG0(%r13)
-        ahi     %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union+THREAD_SIZE
         ahi     %r15,-96
         la      %r2,.Lals_string-.LPG0(%r13)
         l       %r3,.Lsclp_print-.LPG0(%r13)
@@ -488,7 +484,7 @@ startup:basr	%r13,0			# get base
 .Lsclp_print:
         .long   _sclp_print_early
 .Lstack:
-        .long   init_thread_union
+        .long   0x8000 + (1<<(PAGE_SHIFT+THREAD_ORDER))
         .align 16
 2:      .long   0x000a0000,0x8badcccc
 #if defined(CONFIG_64BIT)
@@ -515,13 +511,22 @@ startup:basr	%r13,0			# get base
 3:
 #endif
 
+#ifdef CONFIG_64BIT
+        mvi     __LC_AR_MODE_ID,1       # set esame flag
+        slr     %r0,%r0                 # set cpuid to zero
+        lhi     %r1,2                   # mode 2 = esame (dump)
+        sigp    %r1,%r0,0x12            # switch to esame mode
+        sam64                           # switch to 64 bit mode
+        jg      startup_continue
+#else
+        mvi     __LC_AR_MODE_ID,0       # set ESA flag (mode 0)
         l       %r13,4f-.LPG0(%r13)
         b       0(%r13)
-        .align  4
+        .align  8
 4:      .long   startup_continue
-5:      .long   sched_clock_base_cc
+#endif
         .align  8
-6:      .long   0x7fffffff,0xffffffff
+5:      .long   0x7fffffff,0xffffffff
 
 #
 # params at 10400 (setup.h)
@@ -535,8 +540,4 @@ startup:basr	%r13,0			# get base
         .byte   "root=/dev/ram0 ro"
         .byte   0
 
-#ifdef CONFIG_64BIT
-#include "head64.S"
-#else
-#include "head31.S"
-#endif
+        .org    0x11000
diff --git a/arch/s390/kernel/head31.S b/arch/s390/kernel/head31.S
index 602b508cd4c4..1bbcc499d455 100644
--- a/arch/s390/kernel/head31.S
+++ b/arch/s390/kernel/head31.S
@@ -1,7 +1,7 @@
 /*
  * arch/s390/kernel/head31.S
  *
- * Copyright (C) IBM Corp. 2005,2006
+ * Copyright (C) IBM Corp. 2005,2010
  *
  *   Author(s): Hartmut Penner <hp@de.ibm.com>
  *              Martin Schwidefsky <schwidefsky@de.ibm.com>
@@ -10,13 +10,19 @@
  *
  */
 
-        .org    0x11000
+#include <linux/init.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/page.h>
 
+__HEAD
+        .globl  startup_continue
 startup_continue:
         basr    %r13,0                  # get base
 .LPG1:
 
-        mvi     __LC_AR_MODE_ID,0       # set ESA flag (mode 0)
+        l       %r1,.Lbase_cc-.LPG1(%r13)
+        mvc     0(8,%r1),__LC_LAST_UPDATE_CLOCK
         lctl    %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
         l       %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
                                         # move IPL device to lowcore
@@ -69,10 +75,12 @@ startup_continue:
 .Lduald:.rept   8
         .long   0x80000000,0,0,0        # invalid access-list entries
         .endr
+.Lbase_cc:
+        .long   sched_clock_base_cc
 
-        .org    0x12000
         .globl  _ehead
 _ehead:
+
 #ifdef CONFIG_SHARED_KERNEL
         .org    0x100000
 #endif
diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index 5419aabf8a66..39580e768658 100644
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -1,7 +1,7 @@
 /*
  * arch/s390/kernel/head64.S
  *
- * Copyright (C) IBM Corp. 1999,2006
+ * Copyright (C) IBM Corp. 1999,2010
  *
  *   Author(s): Hartmut Penner <hp@de.ibm.com>
  *              Martin Schwidefsky <schwidefsky@de.ibm.com>
@@ -10,18 +10,17 @@
  *
  */
 
-        .org    0x11000
+#include <linux/init.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/page.h>
 
+__HEAD
+        .globl  startup_continue
 startup_continue:
-        basr    %r13,0                  # get base
-.LPG1:  sll     %r13,1                  # remove high order bit
-        srl     %r13,1
-        mvi     __LC_AR_MODE_ID,1       # set esame flag
-        slr     %r0,%r0                 # set cpuid to zero
-        lhi     %r1,2                   # mode 2 = esame (dump)
-        sigp    %r1,%r0,0x12            # switch to esame mode
-        sam64                           # switch to 64 bit mode
-        llgfr   %r13,%r13               # clear high-order half of base reg
+        larl    %r1,sched_clock_base_cc
+        mvc     0(8,%r1),__LC_LAST_UPDATE_CLOCK
+        larl    %r13,.LPG1              # get base
         lmh     %r0,%r15,.Lzero64-.LPG1(%r13)   # clear high-order half
         lctlg   %c0,%c15,.Lctl-.LPG1(%r13)      # load control registers
         lg      %r12,.Lparmaddr-.LPG1(%r13)     # pointer to parameter area
@@ -46,6 +45,7 @@ startup_continue:
         lpswe   .Lentry-.LPG1(13)       # jump to _stext in primary-space,
                                         # virtual and never return ...
         .align  16
+.LPG1:
 .Lentry:.quad   0x0000000180000000,_stext
 .Lctl:  .quad   0x04350002              # cr0: various things
         .quad   0                       # cr1: primary space segment table
@@ -78,9 +78,9 @@ startup_continue:
         .long   0x80000000,0,0,0        # invalid access-list entries
         .endr
 
-        .org    0x12000
         .globl  _ehead
 _ehead:
+
 #ifdef CONFIG_SHARED_KERNEL
         .org    0x100000
 #endif
diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S
index e27ca63076d1..27af3bf3a009 100644
--- a/arch/s390/kernel/sclp.S
+++ b/arch/s390/kernel/sclp.S
@@ -9,8 +9,10 @@
  */
 
 LC_EXT_NEW_PSW          = 0x58                  # addr of ext int handler
+LC_EXT_NEW_PSW_64       = 0x1b0                 # addr of ext int handler 64 bit
 LC_EXT_INT_PARAM        = 0x80                  # addr of ext int parameter
 LC_EXT_INT_CODE         = 0x86                  # addr of ext int code
+LC_AR_MODE_ID           = 0xa3
 
 #
 # Subroutine which waits synchronously until either an external interruption
@@ -30,8 +32,16 @@ _sclp_wait_int:
 .LbaseS1:
         ahi     %r15,-96                        # create stack frame
         la      %r8,LC_EXT_NEW_PSW              # register int handler
-        mvc     .LoldpswS1-.LbaseS1(8,%r13),0(%r8)
-        mvc     0(8,%r8),.LextpswS1-.LbaseS1(%r13)
+        la      %r9,.LextpswS1-.LbaseS1(%r13)
+#ifdef CONFIG_64BIT
+        tm      LC_AR_MODE_ID,1
+        jno     .Lesa1
+        la      %r8,LC_EXT_NEW_PSW_64           # register int handler 64 bit
+        la      %r9,.LextpswS1_64-.LbaseS1(%r13)
+.Lesa1:
+#endif
+        mvc     .LoldpswS1-.LbaseS1(16,%r13),0(%r8)
+        mvc     0(16,%r8),0(%r9)
         lhi     %r6,0x0200                      # cr mask for ext int (cr0.54)
         ltr     %r2,%r2
         jz      .LsetctS1
@@ -64,15 +74,19 @@ _sclp_wait_int:
 .LtimeoutS1:
         lctl    %c0,%c0,.LctlS1-.LbaseS1(%r13)  # restore interrupt setting
         # restore old handler
-        mvc     0(8,%r8),.LoldpswS1-.LbaseS1(%r13)
+        mvc     0(16,%r8),.LoldpswS1-.LbaseS1(%r13)
         lm      %r6,%r15,120(%r15)              # restore registers
         br      %r14                            # return to caller
 
         .align  8
 .LoldpswS1:
-        .long   0, 0                            # old ext int PSW
+        .long   0, 0, 0, 0                      # old ext int PSW
 .LextpswS1:
         .long   0x00080000, 0x80000000+.LwaitS1 # PSW to handle ext int
+#ifdef CONFIG_64BIT
+.LextpswS1_64:
+        .quad   0x0000000180000000, .LwaitS1    # PSW to handle ext int, 64 bit
+#endif
 .LwaitpswS1:
         .long   0x010a0000, 0x00000000+.LloopS1 # PSW to wait for ext int
 .LtimeS1:
@@ -250,6 +264,13 @@ _sclp_print:
 _sclp_print_early:
         stm     %r6,%r15,24(%r15)               # save registers
         ahi     %r15,-96                        # create stack frame
+#ifdef CONFIG_64BIT
+        tm      LC_AR_MODE_ID,1
+        jno     .Lesa2
+        ahi     %r15,-80
+        stmh    %r6,%r15,96(%r15)               # store upper register halves
+.Lesa2:
+#endif
         lr      %r10,%r2                        # save string pointer
         lhi     %r2,0
         bras    %r14,_sclp_setup                # enable console
@@ -262,6 +283,13 @@ _sclp_print_early:
         lhi     %r2,1
         bras    %r14,_sclp_setup                # disable console
 .LendS5:
+#ifdef CONFIG_64BIT
+        tm      LC_AR_MODE_ID,1
+        jno     .Lesa3
+        lmh     %r6,%r15,96(%r15)               # store upper register halves
+        ahi     %r15,80
+.Lesa3:
+#endif
         lm      %r6,%r15,120(%r15)              # restore registers
         br      %r14