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authorBecky Bruce <beckyb@kernel.crashing.org>2011-10-10 06:50:41 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-12-07 00:26:22 -0500
commit27609a42ee5486b8d132ece24dde6f7524d67df3 (patch)
treeceb23d7bfbf72ce01f0c2836aa03256c4dd0492f /arch/powerpc
parent881fde1db591628db0494e77cd9002b0ba8b04b7 (diff)
powerpc: Whitespace/comment changes to tlb_low_64e.S
I happened to comment this code while I was digging through it; we might as well commit that. I also made some whitespace changes - the existing code had a lot of unnecessary newlines that I found annoying when I was working on my tiny laptop. No functional changes. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/mm/tlb_low_64e.S28
1 files changed, 11 insertions, 17 deletions
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index dc4a5f385e41..71d5d9a0b220 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -94,11 +94,11 @@
94 94
95 srdi r15,r16,60 /* get region */ 95 srdi r15,r16,60 /* get region */
96 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 96 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
97 bne- dtlb_miss_fault_bolted 97 bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */
98 98
99 rlwinm r10,r11,32-19,27,27 99 rlwinm r10,r11,32-19,27,27
100 rlwimi r10,r11,32-16,19,19 100 rlwimi r10,r11,32-16,19,19
101 cmpwi r15,0 101 cmpwi r15,0 /* user vs kernel check */
102 ori r10,r10,_PAGE_PRESENT 102 ori r10,r10,_PAGE_PRESENT
103 oris r11,r10,_PAGE_ACCESSED@h 103 oris r11,r10,_PAGE_ACCESSED@h
104 104
@@ -120,44 +120,38 @@ tlb_miss_common_bolted:
120 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3 120 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
121 cmpldi cr0,r14,0 121 cmpldi cr0,r14,0
122 clrrdi r15,r15,3 122 clrrdi r15,r15,3
123 beq tlb_miss_fault_bolted 123 beq tlb_miss_fault_bolted /* No PGDIR, bail */
124 124
125BEGIN_MMU_FTR_SECTION 125BEGIN_MMU_FTR_SECTION
126 /* Set the TLB reservation and search for existing entry. Then load 126 /* Set the TLB reservation and search for existing entry. Then load
127 * the entry. 127 * the entry.
128 */ 128 */
129 PPC_TLBSRX_DOT(0,r16) 129 PPC_TLBSRX_DOT(0,r16)
130 ldx r14,r14,r15 130 ldx r14,r14,r15 /* grab pgd entry */
131 beq normal_tlb_miss_done 131 beq normal_tlb_miss_done /* tlb exists already, bail */
132MMU_FTR_SECTION_ELSE 132MMU_FTR_SECTION_ELSE
133 ldx r14,r14,r15 133 ldx r14,r14,r15 /* grab pgd entry */
134ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) 134ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
135 135
136#ifndef CONFIG_PPC_64K_PAGES 136#ifndef CONFIG_PPC_64K_PAGES
137 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3 137 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
138 clrrdi r15,r15,3 138 clrrdi r15,r15,3
139 139 cmlpdi cr0,r14,0
140 cmpldi cr0,r14,0 140 beq tlb_miss_fault_bolted /* Bad pgd entry */
141 beq tlb_miss_fault_bolted 141 ldx r14,r14,r15 /* grab pud entry */
142
143 ldx r14,r14,r15
144#endif /* CONFIG_PPC_64K_PAGES */ 142#endif /* CONFIG_PPC_64K_PAGES */
145 143
146 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3 144 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
147 clrrdi r15,r15,3 145 clrrdi r15,r15,3
148
149 cmpldi cr0,r14,0 146 cmpldi cr0,r14,0
150 beq tlb_miss_fault_bolted 147 beq tlb_miss_fault_bolted
151 148 ldx r14,r14,r15 /* Grab pmd entry */
152 ldx r14,r14,r15
153 149
154 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3 150 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
155 clrrdi r15,r15,3 151 clrrdi r15,r15,3
156
157 cmpldi cr0,r14,0 152 cmpldi cr0,r14,0
158 beq tlb_miss_fault_bolted 153 beq tlb_miss_fault_bolted
159 154 ldx r14,r14,r15 /* Grab PTE */
160 ldx r14,r14,r15
161 155
162 /* Check if required permissions are met */ 156 /* Check if required permissions are met */
163 andc. r15,r11,r14 157 andc. r15,r11,r14