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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-11-01 15:38:34 -0400
committerJiri Kosina <jkosina@suse.cz>2010-11-01 15:38:34 -0400
commitb595076a180a56d1bb170e6eceda6eb9d76f4cd3 (patch)
treebc01ec7283808013e0b8ce7713fd6fc40f810429 /arch/powerpc/oprofile
parent6aaccece1c483f189f76f1282b3984ff4c7ecb0a (diff)
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address", "between", "initiali[zs]e", "instead", "function", "select", "already", "equal", "access", "management", "hierarchy", "registration", "interest", "relative", "memory", "offset", "already", Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'arch/powerpc/oprofile')
-rw-r--r--arch/powerpc/oprofile/op_model_cell.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c
index 7fd90d02d8c6..c4d2b7167568 100644
--- a/arch/powerpc/oprofile/op_model_cell.c
+++ b/arch/powerpc/oprofile/op_model_cell.c
@@ -1469,7 +1469,7 @@ static int cell_global_start(struct op_counter_config *ctr)
1469 * The pm_interval register is setup to write the SPU PC value into the 1469 * The pm_interval register is setup to write the SPU PC value into the
1470 * trace buffer at the maximum rate possible. The trace buffer is configured 1470 * trace buffer at the maximum rate possible. The trace buffer is configured
1471 * to store the PCs, wrapping when it is full. The performance counter is 1471 * to store the PCs, wrapping when it is full. The performance counter is
1472 * intialized to the max hardware count minus the number of events, N, between 1472 * initialized to the max hardware count minus the number of events, N, between
1473 * samples. Once the N events have occured, a HW counter overflow occurs 1473 * samples. Once the N events have occured, a HW counter overflow occurs
1474 * causing the generation of a HW counter interrupt which also stops the 1474 * causing the generation of a HW counter interrupt which also stops the
1475 * writing of the SPU PC values to the trace buffer. Hence the last PC 1475 * writing of the SPU PC values to the trace buffer. Hence the last PC