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authorAlexander Graf <agraf@suse.de>2012-05-09 21:54:58 -0400
committerAlexander Graf <agraf@suse.de>2012-05-16 09:02:10 -0400
commit7ef4e985d54bad2773f260da38530f858a9a8491 (patch)
treef3dfb2ae54bd024dbe00da864b8e791fac94210d /arch/powerpc/kvm/book3s_segment.S
parent568b44559d7ca269d367e694c74eb4436e7e3ccf (diff)
KVM: PPC: Book3S: PR: Handle EMUL_ASSIST
In addition to normal "priviledged instruction" traps, we can also receive "emulation assist" traps on newer hardware that has the HV bit set. Handle that one the same way as a privileged instruction, including the instruction fetching. That way we don't execute old instructions that we happen to still leave in that field when an emul assist trap comes. This fixes -M mac99 / -M g3beige on p7 bare metal for me. Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kvm/book3s_segment.S')
-rw-r--r--arch/powerpc/kvm/book3s_segment.S6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S
index 0676ae249b9f..012fc9281213 100644
--- a/arch/powerpc/kvm/book3s_segment.S
+++ b/arch/powerpc/kvm/book3s_segment.S
@@ -250,6 +250,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
250 beq ld_last_prev_inst 250 beq ld_last_prev_inst
251 cmpwi r12, BOOK3S_INTERRUPT_ALIGNMENT 251 cmpwi r12, BOOK3S_INTERRUPT_ALIGNMENT
252 beq- ld_last_inst 252 beq- ld_last_inst
253#ifdef CONFIG_PPC64
254BEGIN_FTR_SECTION
255 cmpwi r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST
256 beq- ld_last_inst
257END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
258#endif
253 259
254 b no_ld_last_inst 260 b no_ld_last_inst
255 261