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authorPaul Mackerras <paulus@samba.org>2005-09-26 02:04:21 -0400
committerPaul Mackerras <paulus@samba.org>2005-09-26 02:04:21 -0400
commit14cf11af6cf608eb8c23e989ddb17a715ddce109 (patch)
tree271a97ce73e265f39c569cb159c195c5b4bb3f8c /arch/powerpc/kernel/head.S
parente5baa396af7560382d2cf3f0871d616b61fc284c (diff)
powerpc: Merge enough to start building in arch/powerpc.
This creates the directory structure under arch/powerpc and a bunch of Kconfig files. It does a first-cut merge of arch/powerpc/mm, arch/powerpc/lib and arch/powerpc/platforms/powermac. This is enough to build a 32-bit powermac kernel with ARCH=powerpc. For now we are getting some unmerged files from arch/ppc/kernel and arch/ppc/syslib, or arch/ppc64/kernel. This makes some minor changes to files in those directories and files outside arch/powerpc. The boot directory is still not merged. That's going to be interesting. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/kernel/head.S')
-rw-r--r--arch/powerpc/kernel/head.S1545
1 files changed, 1545 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/head.S b/arch/powerpc/kernel/head.S
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+++ b/arch/powerpc/kernel/head.S
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1/*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
13 *
14 * This file contains the low-level support and setup for the
15 * PowerPC platform, including trap and interrupt dispatch.
16 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 *
23 */
24
25#include <linux/config.h>
26#include <asm/processor.h>
27#include <asm/page.h>
28#include <asm/mmu.h>
29#include <asm/pgtable.h>
30#include <asm/cputable.h>
31#include <asm/cache.h>
32#include <asm/thread_info.h>
33#include <asm/ppc_asm.h>
34#include <asm/asm-offsets.h>
35
36#ifdef CONFIG_APUS
37#include <asm/amigappc.h>
38#endif
39
40#ifdef CONFIG_PPC64BRIDGE
41#define LOAD_BAT(n, reg, RA, RB) \
42 ld RA,(n*32)+0(reg); \
43 ld RB,(n*32)+8(reg); \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_IBAT##n##L,RB; \
46 ld RA,(n*32)+16(reg); \
47 ld RB,(n*32)+24(reg); \
48 mtspr SPRN_DBAT##n##U,RA; \
49 mtspr SPRN_DBAT##n##L,RB; \
50
51#else /* CONFIG_PPC64BRIDGE */
52
53/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
54#define LOAD_BAT(n, reg, RA, RB) \
55 /* see the comment for clear_bats() -- Cort */ \
56 li RA,0; \
57 mtspr SPRN_IBAT##n##U,RA; \
58 mtspr SPRN_DBAT##n##U,RA; \
59 lwz RA,(n*16)+0(reg); \
60 lwz RB,(n*16)+4(reg); \
61 mtspr SPRN_IBAT##n##U,RA; \
62 mtspr SPRN_IBAT##n##L,RB; \
63 beq 1f; \
64 lwz RA,(n*16)+8(reg); \
65 lwz RB,(n*16)+12(reg); \
66 mtspr SPRN_DBAT##n##U,RA; \
67 mtspr SPRN_DBAT##n##L,RB; \
681:
69#endif /* CONFIG_PPC64BRIDGE */
70
71 .text
72 .stabs "arch/ppc/kernel/",N_SO,0,0,0f
73 .stabs "head.S",N_SO,0,0,0f
740:
75 .globl _stext
76_stext:
77
78/*
79 * _start is defined this way because the XCOFF loader in the OpenFirmware
80 * on the powermac expects the entry point to be a procedure descriptor.
81 */
82 .text
83 .globl _start
84_start:
85 /*
86 * These are here for legacy reasons, the kernel used to
87 * need to look like a coff function entry for the pmac
88 * but we're always started by some kind of bootloader now.
89 * -- Cort
90 */
91 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
92 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
93 nop
94
95/* PMAC
96 * Enter here with the kernel text, data and bss loaded starting at
97 * 0, running with virtual == physical mapping.
98 * r5 points to the prom entry point (the client interface handler
99 * address). Address translation is turned on, with the prom
100 * managing the hash table. Interrupts are disabled. The stack
101 * pointer (r1) points to just below the end of the half-meg region
102 * from 0x380000 - 0x400000, which is mapped in already.
103 *
104 * If we are booted from MacOS via BootX, we enter with the kernel
105 * image loaded somewhere, and the following values in registers:
106 * r3: 'BooX' (0x426f6f58)
107 * r4: virtual address of boot_infos_t
108 * r5: 0
109 *
110 * APUS
111 * r3: 'APUS'
112 * r4: physical address of memory base
113 * Linux/m68k style BootInfo structure at &_end.
114 *
115 * PREP
116 * This is jumped to on prep systems right after the kernel is relocated
117 * to its proper place in memory by the boot loader. The expected layout
118 * of the regs is:
119 * r3: ptr to residual data
120 * r4: initrd_start or if no initrd then 0
121 * r5: initrd_end - unused if r4 is 0
122 * r6: Start of command line string
123 * r7: End of command line string
124 *
125 * This just gets a minimal mmu environment setup so we can call
126 * start_here() to do the real work.
127 * -- Cort
128 */
129
130 .globl __start
131__start:
132/*
133 * We have to do any OF calls before we map ourselves to KERNELBASE,
134 * because OF may have I/O devices mapped into that area
135 * (particularly on CHRP).
136 */
137 mr r31,r3 /* save parameters */
138 mr r30,r4
139 mr r29,r5
140 mr r28,r6
141 mr r27,r7
142 li r24,0 /* cpu # */
143
144/*
145 * early_init() does the early machine identification and does
146 * the necessary low-level setup and clears the BSS
147 * -- Cort <cort@fsmlabs.com>
148 */
149 bl early_init
150
151/*
152 * On POWER4, we first need to tweak some CPU configuration registers
153 * like real mode cache inhibit or exception base
154 */
155#ifdef CONFIG_POWER4
156 bl __970_cpu_preinit
157#endif /* CONFIG_POWER4 */
158
159#ifdef CONFIG_APUS
160/* On APUS the __va/__pa constants need to be set to the correct
161 * values before continuing.
162 */
163 mr r4,r30
164 bl fix_mem_constants
165#endif /* CONFIG_APUS */
166
167/* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
168 * the physical address we are running at, returned by early_init()
169 */
170 bl mmu_off
171__after_mmu_off:
172#ifndef CONFIG_POWER4
173 bl clear_bats
174 bl flush_tlbs
175
176 bl initial_bats
177#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
178 bl setup_disp_bat
179#endif
180#else /* CONFIG_POWER4 */
181 bl reloc_offset
182 bl initial_mm_power4
183#endif /* CONFIG_POWER4 */
184
185/*
186 * Call setup_cpu for CPU 0 and initialize 6xx Idle
187 */
188 bl reloc_offset
189 li r24,0 /* cpu# */
190 bl call_setup_cpu /* Call setup_cpu for this CPU */
191#ifdef CONFIG_6xx
192 bl reloc_offset
193 bl init_idle_6xx
194#endif /* CONFIG_6xx */
195#ifdef CONFIG_POWER4
196 bl reloc_offset
197 bl init_idle_power4
198#endif /* CONFIG_POWER4 */
199
200
201#ifndef CONFIG_APUS
202/*
203 * We need to run with _start at physical address 0.
204 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
205 * the exception vectors at 0 (and therefore this copy
206 * overwrites OF's exception vectors with our own).
207 * If the MMU is already turned on, we copy stuff to KERNELBASE,
208 * otherwise we copy it to 0.
209 */
210 bl reloc_offset
211 mr r26,r3
212 addis r4,r3,KERNELBASE@h /* current address of _start */
213 cmpwi 0,r4,0 /* are we already running at 0? */
214 bne relocate_kernel
215#endif /* CONFIG_APUS */
216/*
217 * we now have the 1st 16M of ram mapped with the bats.
218 * prep needs the mmu to be turned on here, but pmac already has it on.
219 * this shouldn't bother the pmac since it just gets turned on again
220 * as we jump to our code at KERNELBASE. -- Cort
221 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
222 * off, and in other cases, we now turn it off before changing BATs above.
223 */
224turn_on_mmu:
225 mfmsr r0
226 ori r0,r0,MSR_DR|MSR_IR
227 mtspr SPRN_SRR1,r0
228 lis r0,start_here@h
229 ori r0,r0,start_here@l
230 mtspr SPRN_SRR0,r0
231 SYNC
232 RFI /* enables MMU */
233
234/*
235 * We need __secondary_hold as a place to hold the other cpus on
236 * an SMP machine, even when we are running a UP kernel.
237 */
238 . = 0xc0 /* for prep bootloader */
239 li r3,1 /* MTX only has 1 cpu */
240 .globl __secondary_hold
241__secondary_hold:
242 /* tell the master we're here */
243 stw r3,4(0)
244#ifdef CONFIG_SMP
245100: lwz r4,0(0)
246 /* wait until we're told to start */
247 cmpw 0,r4,r3
248 bne 100b
249 /* our cpu # was at addr 0 - go */
250 mr r24,r3 /* cpu # */
251 b __secondary_start
252#else
253 b .
254#endif /* CONFIG_SMP */
255
256/*
257 * Exception entry code. This code runs with address translation
258 * turned off, i.e. using physical addresses.
259 * We assume sprg3 has the physical address of the current
260 * task's thread_struct.
261 */
262#define EXCEPTION_PROLOG \
263 mtspr SPRN_SPRG0,r10; \
264 mtspr SPRN_SPRG1,r11; \
265 mfcr r10; \
266 EXCEPTION_PROLOG_1; \
267 EXCEPTION_PROLOG_2
268
269#define EXCEPTION_PROLOG_1 \
270 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
271 andi. r11,r11,MSR_PR; \
272 tophys(r11,r1); /* use tophys(r1) if kernel */ \
273 beq 1f; \
274 mfspr r11,SPRN_SPRG3; \
275 lwz r11,THREAD_INFO-THREAD(r11); \
276 addi r11,r11,THREAD_SIZE; \
277 tophys(r11,r11); \
2781: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
279
280
281#define EXCEPTION_PROLOG_2 \
282 CLR_TOP32(r11); \
283 stw r10,_CCR(r11); /* save registers */ \
284 stw r12,GPR12(r11); \
285 stw r9,GPR9(r11); \
286 mfspr r10,SPRN_SPRG0; \
287 stw r10,GPR10(r11); \
288 mfspr r12,SPRN_SPRG1; \
289 stw r12,GPR11(r11); \
290 mflr r10; \
291 stw r10,_LINK(r11); \
292 mfspr r12,SPRN_SRR0; \
293 mfspr r9,SPRN_SRR1; \
294 stw r1,GPR1(r11); \
295 stw r1,0(r11); \
296 tovirt(r1,r11); /* set new kernel sp */ \
297 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
298 MTMSRD(r10); /* (except for mach check in rtas) */ \
299 stw r0,GPR0(r11); \
300 SAVE_4GPRS(3, r11); \
301 SAVE_2GPRS(7, r11)
302
303/*
304 * Note: code which follows this uses cr0.eq (set if from kernel),
305 * r11, r12 (SRR0), and r9 (SRR1).
306 *
307 * Note2: once we have set r1 we are in a position to take exceptions
308 * again, and we could thus set MSR:RI at that point.
309 */
310
311/*
312 * Exception vectors.
313 */
314#define EXCEPTION(n, label, hdlr, xfer) \
315 . = n; \
316label: \
317 EXCEPTION_PROLOG; \
318 addi r3,r1,STACK_FRAME_OVERHEAD; \
319 xfer(n, hdlr)
320
321#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
322 li r10,trap; \
323 stw r10,TRAP(r11); \
324 li r10,MSR_KERNEL; \
325 copyee(r10, r9); \
326 bl tfer; \
327i##n: \
328 .long hdlr; \
329 .long ret
330
331#define COPY_EE(d, s) rlwimi d,s,0,16,16
332#define NOCOPY(d, s)
333
334#define EXC_XFER_STD(n, hdlr) \
335 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
336 ret_from_except_full)
337
338#define EXC_XFER_LITE(n, hdlr) \
339 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
340 ret_from_except)
341
342#define EXC_XFER_EE(n, hdlr) \
343 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
344 ret_from_except_full)
345
346#define EXC_XFER_EE_LITE(n, hdlr) \
347 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
348 ret_from_except)
349
350/* System reset */
351/* core99 pmac starts the seconary here by changing the vector, and
352 putting it back to what it was (UnknownException) when done. */
353#if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
354 . = 0x100
355 b __secondary_start_gemini
356#else
357 EXCEPTION(0x100, Reset, UnknownException, EXC_XFER_STD)
358#endif
359
360/* Machine check */
361/*
362 * On CHRP, this is complicated by the fact that we could get a
363 * machine check inside RTAS, and we have no guarantee that certain
364 * critical registers will have the values we expect. The set of
365 * registers that might have bad values includes all the GPRs
366 * and all the BATs. We indicate that we are in RTAS by putting
367 * a non-zero value, the address of the exception frame to use,
368 * in SPRG2. The machine check handler checks SPRG2 and uses its
369 * value if it is non-zero. If we ever needed to free up SPRG2,
370 * we could use a field in the thread_info or thread_struct instead.
371 * (Other exception handlers assume that r1 is a valid kernel stack
372 * pointer when we take an exception from supervisor mode.)
373 * -- paulus.
374 */
375 . = 0x200
376 mtspr SPRN_SPRG0,r10
377 mtspr SPRN_SPRG1,r11
378 mfcr r10
379#ifdef CONFIG_PPC_CHRP
380 mfspr r11,SPRN_SPRG2
381 cmpwi 0,r11,0
382 bne 7f
383#endif /* CONFIG_PPC_CHRP */
384 EXCEPTION_PROLOG_1
3857: EXCEPTION_PROLOG_2
386 addi r3,r1,STACK_FRAME_OVERHEAD
387#ifdef CONFIG_PPC_CHRP
388 mfspr r4,SPRN_SPRG2
389 cmpwi cr1,r4,0
390 bne cr1,1f
391#endif
392 EXC_XFER_STD(0x200, MachineCheckException)
393#ifdef CONFIG_PPC_CHRP
3941: b machine_check_in_rtas
395#endif
396
397/* Data access exception. */
398 . = 0x300
399#ifdef CONFIG_PPC64BRIDGE
400 b DataAccess
401DataAccessCont:
402#else
403DataAccess:
404 EXCEPTION_PROLOG
405#endif /* CONFIG_PPC64BRIDGE */
406 mfspr r10,SPRN_DSISR
407 andis. r0,r10,0xa470 /* weird error? */
408 bne 1f /* if not, try to put a PTE */
409 mfspr r4,SPRN_DAR /* into the hash table */
410 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
411 bl hash_page
4121: stw r10,_DSISR(r11)
413 mr r5,r10
414 mfspr r4,SPRN_DAR
415 EXC_XFER_EE_LITE(0x300, handle_page_fault)
416
417#ifdef CONFIG_PPC64BRIDGE
418/* SLB fault on data access. */
419 . = 0x380
420 b DataSegment
421#endif /* CONFIG_PPC64BRIDGE */
422
423/* Instruction access exception. */
424 . = 0x400
425#ifdef CONFIG_PPC64BRIDGE
426 b InstructionAccess
427InstructionAccessCont:
428#else
429InstructionAccess:
430 EXCEPTION_PROLOG
431#endif /* CONFIG_PPC64BRIDGE */
432 andis. r0,r9,0x4000 /* no pte found? */
433 beq 1f /* if so, try to put a PTE */
434 li r3,0 /* into the hash table */
435 mr r4,r12 /* SRR0 is fault address */
436 bl hash_page
4371: mr r4,r12
438 mr r5,r9
439 EXC_XFER_EE_LITE(0x400, handle_page_fault)
440
441#ifdef CONFIG_PPC64BRIDGE
442/* SLB fault on instruction access. */
443 . = 0x480
444 b InstructionSegment
445#endif /* CONFIG_PPC64BRIDGE */
446
447/* External interrupt */
448 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
449
450/* Alignment exception */
451 . = 0x600
452Alignment:
453 EXCEPTION_PROLOG
454 mfspr r4,SPRN_DAR
455 stw r4,_DAR(r11)
456 mfspr r5,SPRN_DSISR
457 stw r5,_DSISR(r11)
458 addi r3,r1,STACK_FRAME_OVERHEAD
459 EXC_XFER_EE(0x600, AlignmentException)
460
461/* Program check exception */
462 EXCEPTION(0x700, ProgramCheck, ProgramCheckException, EXC_XFER_STD)
463
464/* Floating-point unavailable */
465 . = 0x800
466FPUnavailable:
467 EXCEPTION_PROLOG
468 bne load_up_fpu /* if from user, just load it up */
469 addi r3,r1,STACK_FRAME_OVERHEAD
470 EXC_XFER_EE_LITE(0x800, KernelFP)
471
472/* Decrementer */
473 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
474
475 EXCEPTION(0xa00, Trap_0a, UnknownException, EXC_XFER_EE)
476 EXCEPTION(0xb00, Trap_0b, UnknownException, EXC_XFER_EE)
477
478/* System call */
479 . = 0xc00
480SystemCall:
481 EXCEPTION_PROLOG
482 EXC_XFER_EE_LITE(0xc00, DoSyscall)
483
484/* Single step - not used on 601 */
485 EXCEPTION(0xd00, SingleStep, SingleStepException, EXC_XFER_STD)
486 EXCEPTION(0xe00, Trap_0e, UnknownException, EXC_XFER_EE)
487
488/*
489 * The Altivec unavailable trap is at 0x0f20. Foo.
490 * We effectively remap it to 0x3000.
491 * We include an altivec unavailable exception vector even if
492 * not configured for Altivec, so that you can't panic a
493 * non-altivec kernel running on a machine with altivec just
494 * by executing an altivec instruction.
495 */
496 . = 0xf00
497 b Trap_0f
498
499 . = 0xf20
500 b AltiVecUnavailable
501
502Trap_0f:
503 EXCEPTION_PROLOG
504 addi r3,r1,STACK_FRAME_OVERHEAD
505 EXC_XFER_EE(0xf00, UnknownException)
506
507/*
508 * Handle TLB miss for instruction on 603/603e.
509 * Note: we get an alternate set of r0 - r3 to use automatically.
510 */
511 . = 0x1000
512InstructionTLBMiss:
513/*
514 * r0: stored ctr
515 * r1: linux style pte ( later becomes ppc hardware pte )
516 * r2: ptr to linux-style pte
517 * r3: scratch
518 */
519 mfctr r0
520 /* Get PTE (linux-style) and check access */
521 mfspr r3,SPRN_IMISS
522 lis r1,KERNELBASE@h /* check if kernel address */
523 cmplw 0,r3,r1
524 mfspr r2,SPRN_SPRG3
525 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
526 lwz r2,PGDIR(r2)
527 blt+ 112f
528 lis r2,swapper_pg_dir@ha /* if kernel address, use */
529 addi r2,r2,swapper_pg_dir@l /* kernel page table */
530 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
531 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
532112: tophys(r2,r2)
533 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
534 lwz r2,0(r2) /* get pmd entry */
535 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
536 beq- InstructionAddressInvalid /* return if no mapping */
537 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
538 lwz r3,0(r2) /* get linux-style pte */
539 andc. r1,r1,r3 /* check access & ~permission */
540 bne- InstructionAddressInvalid /* return if access not permitted */
541 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
542 /*
543 * NOTE! We are assuming this is not an SMP system, otherwise
544 * we would need to update the pte atomically with lwarx/stwcx.
545 */
546 stw r3,0(r2) /* update PTE (accessed bit) */
547 /* Convert linux-style PTE to low word of PPC-style PTE */
548 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
549 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
550 and r1,r1,r2 /* writable if _RW and _DIRTY */
551 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
552 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
553 ori r1,r1,0xe14 /* clear out reserved bits and M */
554 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
555 mtspr SPRN_RPA,r1
556 mfspr r3,SPRN_IMISS
557 tlbli r3
558 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
559 mtcrf 0x80,r3
560 rfi
561InstructionAddressInvalid:
562 mfspr r3,SPRN_SRR1
563 rlwinm r1,r3,9,6,6 /* Get load/store bit */
564
565 addis r1,r1,0x2000
566 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
567 mtctr r0 /* Restore CTR */
568 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
569 or r2,r2,r1
570 mtspr SPRN_SRR1,r2
571 mfspr r1,SPRN_IMISS /* Get failing address */
572 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
573 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
574 xor r1,r1,r2
575 mtspr SPRN_DAR,r1 /* Set fault address */
576 mfmsr r0 /* Restore "normal" registers */
577 xoris r0,r0,MSR_TGPR>>16
578 mtcrf 0x80,r3 /* Restore CR0 */
579 mtmsr r0
580 b InstructionAccess
581
582/*
583 * Handle TLB miss for DATA Load operation on 603/603e
584 */
585 . = 0x1100
586DataLoadTLBMiss:
587/*
588 * r0: stored ctr
589 * r1: linux style pte ( later becomes ppc hardware pte )
590 * r2: ptr to linux-style pte
591 * r3: scratch
592 */
593 mfctr r0
594 /* Get PTE (linux-style) and check access */
595 mfspr r3,SPRN_DMISS
596 lis r1,KERNELBASE@h /* check if kernel address */
597 cmplw 0,r3,r1
598 mfspr r2,SPRN_SPRG3
599 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
600 lwz r2,PGDIR(r2)
601 blt+ 112f
602 lis r2,swapper_pg_dir@ha /* if kernel address, use */
603 addi r2,r2,swapper_pg_dir@l /* kernel page table */
604 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
605 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
606112: tophys(r2,r2)
607 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
608 lwz r2,0(r2) /* get pmd entry */
609 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
610 beq- DataAddressInvalid /* return if no mapping */
611 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
612 lwz r3,0(r2) /* get linux-style pte */
613 andc. r1,r1,r3 /* check access & ~permission */
614 bne- DataAddressInvalid /* return if access not permitted */
615 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
616 /*
617 * NOTE! We are assuming this is not an SMP system, otherwise
618 * we would need to update the pte atomically with lwarx/stwcx.
619 */
620 stw r3,0(r2) /* update PTE (accessed bit) */
621 /* Convert linux-style PTE to low word of PPC-style PTE */
622 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
623 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
624 and r1,r1,r2 /* writable if _RW and _DIRTY */
625 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
626 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
627 ori r1,r1,0xe14 /* clear out reserved bits and M */
628 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
629 mtspr SPRN_RPA,r1
630 mfspr r3,SPRN_DMISS
631 tlbld r3
632 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
633 mtcrf 0x80,r3
634 rfi
635DataAddressInvalid:
636 mfspr r3,SPRN_SRR1
637 rlwinm r1,r3,9,6,6 /* Get load/store bit */
638 addis r1,r1,0x2000
639 mtspr SPRN_DSISR,r1
640 mtctr r0 /* Restore CTR */
641 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
642 mtspr SPRN_SRR1,r2
643 mfspr r1,SPRN_DMISS /* Get failing address */
644 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
645 beq 20f /* Jump if big endian */
646 xori r1,r1,3
64720: mtspr SPRN_DAR,r1 /* Set fault address */
648 mfmsr r0 /* Restore "normal" registers */
649 xoris r0,r0,MSR_TGPR>>16
650 mtcrf 0x80,r3 /* Restore CR0 */
651 mtmsr r0
652 b DataAccess
653
654/*
655 * Handle TLB miss for DATA Store on 603/603e
656 */
657 . = 0x1200
658DataStoreTLBMiss:
659/*
660 * r0: stored ctr
661 * r1: linux style pte ( later becomes ppc hardware pte )
662 * r2: ptr to linux-style pte
663 * r3: scratch
664 */
665 mfctr r0
666 /* Get PTE (linux-style) and check access */
667 mfspr r3,SPRN_DMISS
668 lis r1,KERNELBASE@h /* check if kernel address */
669 cmplw 0,r3,r1
670 mfspr r2,SPRN_SPRG3
671 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
672 lwz r2,PGDIR(r2)
673 blt+ 112f
674 lis r2,swapper_pg_dir@ha /* if kernel address, use */
675 addi r2,r2,swapper_pg_dir@l /* kernel page table */
676 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
677 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
678112: tophys(r2,r2)
679 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
680 lwz r2,0(r2) /* get pmd entry */
681 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
682 beq- DataAddressInvalid /* return if no mapping */
683 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
684 lwz r3,0(r2) /* get linux-style pte */
685 andc. r1,r1,r3 /* check access & ~permission */
686 bne- DataAddressInvalid /* return if access not permitted */
687 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
688 /*
689 * NOTE! We are assuming this is not an SMP system, otherwise
690 * we would need to update the pte atomically with lwarx/stwcx.
691 */
692 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
693 /* Convert linux-style PTE to low word of PPC-style PTE */
694 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
695 li r1,0xe15 /* clear out reserved bits and M */
696 andc r1,r3,r1 /* PP = user? 2: 0 */
697 mtspr SPRN_RPA,r1
698 mfspr r3,SPRN_DMISS
699 tlbld r3
700 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
701 mtcrf 0x80,r3
702 rfi
703
704#ifndef CONFIG_ALTIVEC
705#define AltivecAssistException UnknownException
706#endif
707
708 EXCEPTION(0x1300, Trap_13, InstructionBreakpoint, EXC_XFER_EE)
709 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
710 EXCEPTION(0x1500, Trap_15, UnknownException, EXC_XFER_EE)
711#ifdef CONFIG_POWER4
712 EXCEPTION(0x1600, Trap_16, UnknownException, EXC_XFER_EE)
713 EXCEPTION(0x1700, Trap_17, AltivecAssistException, EXC_XFER_EE)
714 EXCEPTION(0x1800, Trap_18, TAUException, EXC_XFER_STD)
715#else /* !CONFIG_POWER4 */
716 EXCEPTION(0x1600, Trap_16, AltivecAssistException, EXC_XFER_EE)
717 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
718 EXCEPTION(0x1800, Trap_18, UnknownException, EXC_XFER_EE)
719#endif /* CONFIG_POWER4 */
720 EXCEPTION(0x1900, Trap_19, UnknownException, EXC_XFER_EE)
721 EXCEPTION(0x1a00, Trap_1a, UnknownException, EXC_XFER_EE)
722 EXCEPTION(0x1b00, Trap_1b, UnknownException, EXC_XFER_EE)
723 EXCEPTION(0x1c00, Trap_1c, UnknownException, EXC_XFER_EE)
724 EXCEPTION(0x1d00, Trap_1d, UnknownException, EXC_XFER_EE)
725 EXCEPTION(0x1e00, Trap_1e, UnknownException, EXC_XFER_EE)
726 EXCEPTION(0x1f00, Trap_1f, UnknownException, EXC_XFER_EE)
727 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
728 EXCEPTION(0x2100, Trap_21, UnknownException, EXC_XFER_EE)
729 EXCEPTION(0x2200, Trap_22, UnknownException, EXC_XFER_EE)
730 EXCEPTION(0x2300, Trap_23, UnknownException, EXC_XFER_EE)
731 EXCEPTION(0x2400, Trap_24, UnknownException, EXC_XFER_EE)
732 EXCEPTION(0x2500, Trap_25, UnknownException, EXC_XFER_EE)
733 EXCEPTION(0x2600, Trap_26, UnknownException, EXC_XFER_EE)
734 EXCEPTION(0x2700, Trap_27, UnknownException, EXC_XFER_EE)
735 EXCEPTION(0x2800, Trap_28, UnknownException, EXC_XFER_EE)
736 EXCEPTION(0x2900, Trap_29, UnknownException, EXC_XFER_EE)
737 EXCEPTION(0x2a00, Trap_2a, UnknownException, EXC_XFER_EE)
738 EXCEPTION(0x2b00, Trap_2b, UnknownException, EXC_XFER_EE)
739 EXCEPTION(0x2c00, Trap_2c, UnknownException, EXC_XFER_EE)
740 EXCEPTION(0x2d00, Trap_2d, UnknownException, EXC_XFER_EE)
741 EXCEPTION(0x2e00, Trap_2e, UnknownException, EXC_XFER_EE)
742 EXCEPTION(0x2f00, MOLTrampoline, UnknownException, EXC_XFER_EE_LITE)
743
744 .globl mol_trampoline
745 .set mol_trampoline, i0x2f00
746
747 . = 0x3000
748
749AltiVecUnavailable:
750 EXCEPTION_PROLOG
751#ifdef CONFIG_ALTIVEC
752 bne load_up_altivec /* if from user, just load it up */
753#endif /* CONFIG_ALTIVEC */
754 EXC_XFER_EE_LITE(0xf20, AltivecUnavailException)
755
756#ifdef CONFIG_PPC64BRIDGE
757DataAccess:
758 EXCEPTION_PROLOG
759 b DataAccessCont
760
761InstructionAccess:
762 EXCEPTION_PROLOG
763 b InstructionAccessCont
764
765DataSegment:
766 EXCEPTION_PROLOG
767 addi r3,r1,STACK_FRAME_OVERHEAD
768 mfspr r4,SPRN_DAR
769 stw r4,_DAR(r11)
770 EXC_XFER_STD(0x380, UnknownException)
771
772InstructionSegment:
773 EXCEPTION_PROLOG
774 addi r3,r1,STACK_FRAME_OVERHEAD
775 EXC_XFER_STD(0x480, UnknownException)
776#endif /* CONFIG_PPC64BRIDGE */
777
778#ifdef CONFIG_ALTIVEC
779/* Note that the AltiVec support is closely modeled after the FP
780 * support. Changes to one are likely to be applicable to the
781 * other! */
782load_up_altivec:
783/*
784 * Disable AltiVec for the task which had AltiVec previously,
785 * and save its AltiVec registers in its thread_struct.
786 * Enables AltiVec for use in the kernel on return.
787 * On SMP we know the AltiVec units are free, since we give it up every
788 * switch. -- Kumar
789 */
790 mfmsr r5
791 oris r5,r5,MSR_VEC@h
792 MTMSRD(r5) /* enable use of AltiVec now */
793 isync
794/*
795 * For SMP, we don't do lazy AltiVec switching because it just gets too
796 * horrendously complex, especially when a task switches from one CPU
797 * to another. Instead we call giveup_altivec in switch_to.
798 */
799#ifndef CONFIG_SMP
800 tophys(r6,0)
801 addis r3,r6,last_task_used_altivec@ha
802 lwz r4,last_task_used_altivec@l(r3)
803 cmpwi 0,r4,0
804 beq 1f
805 add r4,r4,r6
806 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
807 SAVE_32VRS(0,r10,r4)
808 mfvscr vr0
809 li r10,THREAD_VSCR
810 stvx vr0,r10,r4
811 lwz r5,PT_REGS(r4)
812 add r5,r5,r6
813 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
814 lis r10,MSR_VEC@h
815 andc r4,r4,r10 /* disable altivec for previous task */
816 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
8171:
818#endif /* CONFIG_SMP */
819 /* enable use of AltiVec after return */
820 oris r9,r9,MSR_VEC@h
821 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
822 li r4,1
823 li r10,THREAD_VSCR
824 stw r4,THREAD_USED_VR(r5)
825 lvx vr0,r10,r5
826 mtvscr vr0
827 REST_32VRS(0,r10,r5)
828#ifndef CONFIG_SMP
829 subi r4,r5,THREAD
830 sub r4,r4,r6
831 stw r4,last_task_used_altivec@l(r3)
832#endif /* CONFIG_SMP */
833 /* restore registers and return */
834 /* we haven't used ctr or xer or lr */
835 b fast_exception_return
836
837/*
838 * AltiVec unavailable trap from kernel - print a message, but let
839 * the task use AltiVec in the kernel until it returns to user mode.
840 */
841KernelAltiVec:
842 lwz r3,_MSR(r1)
843 oris r3,r3,MSR_VEC@h
844 stw r3,_MSR(r1) /* enable use of AltiVec after return */
845 lis r3,87f@h
846 ori r3,r3,87f@l
847 mr r4,r2 /* current */
848 lwz r5,_NIP(r1)
849 bl printk
850 b ret_from_except
85187: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
852 .align 4,0
853
854/*
855 * giveup_altivec(tsk)
856 * Disable AltiVec for the task given as the argument,
857 * and save the AltiVec registers in its thread_struct.
858 * Enables AltiVec for use in the kernel on return.
859 */
860
861 .globl giveup_altivec
862giveup_altivec:
863 mfmsr r5
864 oris r5,r5,MSR_VEC@h
865 SYNC
866 MTMSRD(r5) /* enable use of AltiVec now */
867 isync
868 cmpwi 0,r3,0
869 beqlr- /* if no previous owner, done */
870 addi r3,r3,THREAD /* want THREAD of task */
871 lwz r5,PT_REGS(r3)
872 cmpwi 0,r5,0
873 SAVE_32VRS(0, r4, r3)
874 mfvscr vr0
875 li r4,THREAD_VSCR
876 stvx vr0,r4,r3
877 beq 1f
878 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
879 lis r3,MSR_VEC@h
880 andc r4,r4,r3 /* disable AltiVec for previous task */
881 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
8821:
883#ifndef CONFIG_SMP
884 li r5,0
885 lis r4,last_task_used_altivec@ha
886 stw r5,last_task_used_altivec@l(r4)
887#endif /* CONFIG_SMP */
888 blr
889#endif /* CONFIG_ALTIVEC */
890
891/*
892 * This code is jumped to from the startup code to copy
893 * the kernel image to physical address 0.
894 */
895relocate_kernel:
896 addis r9,r26,klimit@ha /* fetch klimit */
897 lwz r25,klimit@l(r9)
898 addis r25,r25,-KERNELBASE@h
899 li r3,0 /* Destination base address */
900 li r6,0 /* Destination offset */
901 li r5,0x4000 /* # bytes of memory to copy */
902 bl copy_and_flush /* copy the first 0x4000 bytes */
903 addi r0,r3,4f@l /* jump to the address of 4f */
904 mtctr r0 /* in copy and do the rest. */
905 bctr /* jump to the copy */
9064: mr r5,r25
907 bl copy_and_flush /* copy the rest */
908 b turn_on_mmu
909
910/*
911 * Copy routine used to copy the kernel to start at physical address 0
912 * and flush and invalidate the caches as needed.
913 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
914 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
915 */
916copy_and_flush:
917 addi r5,r5,-4
918 addi r6,r6,-4
9194: li r0,L1_CACHE_LINE_SIZE/4
920 mtctr r0
9213: addi r6,r6,4 /* copy a cache line */
922 lwzx r0,r6,r4
923 stwx r0,r6,r3
924 bdnz 3b
925 dcbst r6,r3 /* write it to memory */
926 sync
927 icbi r6,r3 /* flush the icache line */
928 cmplw 0,r6,r5
929 blt 4b
930 sync /* additional sync needed on g4 */
931 isync
932 addi r5,r5,4
933 addi r6,r6,4
934 blr
935
936#ifdef CONFIG_APUS
937/*
938 * On APUS the physical base address of the kernel is not known at compile
939 * time, which means the __pa/__va constants used are incorrect. In the
940 * __init section is recorded the virtual addresses of instructions using
941 * these constants, so all that has to be done is fix these before
942 * continuing the kernel boot.
943 *
944 * r4 = The physical address of the kernel base.
945 */
946fix_mem_constants:
947 mr r10,r4
948 addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */
949 neg r11,r10 /* phys_to_virt constant */
950
951 lis r12,__vtop_table_begin@h
952 ori r12,r12,__vtop_table_begin@l
953 add r12,r12,r10 /* table begin phys address */
954 lis r13,__vtop_table_end@h
955 ori r13,r13,__vtop_table_end@l
956 add r13,r13,r10 /* table end phys address */
957 subi r12,r12,4
958 subi r13,r13,4
9591: lwzu r14,4(r12) /* virt address of instruction */
960 add r14,r14,r10 /* phys address of instruction */
961 lwz r15,0(r14) /* instruction, now insert top */
962 rlwimi r15,r10,16,16,31 /* half of vp const in low half */
963 stw r15,0(r14) /* of instruction and restore. */
964 dcbst r0,r14 /* write it to memory */
965 sync
966 icbi r0,r14 /* flush the icache line */
967 cmpw r12,r13
968 bne 1b
969 sync /* additional sync needed on g4 */
970 isync
971
972/*
973 * Map the memory where the exception handlers will
974 * be copied to when hash constants have been patched.
975 */
976#ifdef CONFIG_APUS_FAST_EXCEPT
977 lis r8,0xfff0
978#else
979 lis r8,0
980#endif
981 ori r8,r8,0x2 /* 128KB, supervisor */
982 mtspr SPRN_DBAT3U,r8
983 mtspr SPRN_DBAT3L,r8
984
985 lis r12,__ptov_table_begin@h
986 ori r12,r12,__ptov_table_begin@l
987 add r12,r12,r10 /* table begin phys address */
988 lis r13,__ptov_table_end@h
989 ori r13,r13,__ptov_table_end@l
990 add r13,r13,r10 /* table end phys address */
991 subi r12,r12,4
992 subi r13,r13,4
9931: lwzu r14,4(r12) /* virt address of instruction */
994 add r14,r14,r10 /* phys address of instruction */
995 lwz r15,0(r14) /* instruction, now insert top */
996 rlwimi r15,r11,16,16,31 /* half of pv const in low half*/
997 stw r15,0(r14) /* of instruction and restore. */
998 dcbst r0,r14 /* write it to memory */
999 sync
1000 icbi r0,r14 /* flush the icache line */
1001 cmpw r12,r13
1002 bne 1b
1003
1004 sync /* additional sync needed on g4 */
1005 isync /* No speculative loading until now */
1006 blr
1007
1008/***********************************************************************
1009 * Please note that on APUS the exception handlers are located at the
1010 * physical address 0xfff0000. For this reason, the exception handlers
1011 * cannot use relative branches to access the code below.
1012 ***********************************************************************/
1013#endif /* CONFIG_APUS */
1014
1015#ifdef CONFIG_SMP
1016#ifdef CONFIG_GEMINI
1017 .globl __secondary_start_gemini
1018__secondary_start_gemini:
1019 mfspr r4,SPRN_HID0
1020 ori r4,r4,HID0_ICFI
1021 li r3,0
1022 ori r3,r3,HID0_ICE
1023 andc r4,r4,r3
1024 mtspr SPRN_HID0,r4
1025 sync
1026 b __secondary_start
1027#endif /* CONFIG_GEMINI */
1028
1029 .globl __secondary_start_pmac_0
1030__secondary_start_pmac_0:
1031 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1032 li r24,0
1033 b 1f
1034 li r24,1
1035 b 1f
1036 li r24,2
1037 b 1f
1038 li r24,3
10391:
1040 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
1041 set to map the 0xf0000000 - 0xffffffff region */
1042 mfmsr r0
1043 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
1044 SYNC
1045 mtmsr r0
1046 isync
1047
1048 .globl __secondary_start
1049__secondary_start:
1050#ifdef CONFIG_PPC64BRIDGE
1051 mfmsr r0
1052 clrldi r0,r0,1 /* make sure it's in 32-bit mode */
1053 SYNC
1054 MTMSRD(r0)
1055 isync
1056#endif
1057 /* Copy some CPU settings from CPU 0 */
1058 bl __restore_cpu_setup
1059
1060 lis r3,-KERNELBASE@h
1061 mr r4,r24
1062 bl identify_cpu
1063 bl call_setup_cpu /* Call setup_cpu for this CPU */
1064#ifdef CONFIG_6xx
1065 lis r3,-KERNELBASE@h
1066 bl init_idle_6xx
1067#endif /* CONFIG_6xx */
1068#ifdef CONFIG_POWER4
1069 lis r3,-KERNELBASE@h
1070 bl init_idle_power4
1071#endif /* CONFIG_POWER4 */
1072
1073 /* get current_thread_info and current */
1074 lis r1,secondary_ti@ha
1075 tophys(r1,r1)
1076 lwz r1,secondary_ti@l(r1)
1077 tophys(r2,r1)
1078 lwz r2,TI_TASK(r2)
1079
1080 /* stack */
1081 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1082 li r0,0
1083 tophys(r3,r1)
1084 stw r0,0(r3)
1085
1086 /* load up the MMU */
1087 bl load_up_mmu
1088
1089 /* ptr to phys current thread */
1090 tophys(r4,r2)
1091 addi r4,r4,THREAD /* phys address of our thread_struct */
1092 CLR_TOP32(r4)
1093 mtspr SPRN_SPRG3,r4
1094 li r3,0
1095 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1096
1097 /* enable MMU and jump to start_secondary */
1098 li r4,MSR_KERNEL
1099 FIX_SRR1(r4,r5)
1100 lis r3,start_secondary@h
1101 ori r3,r3,start_secondary@l
1102 mtspr SPRN_SRR0,r3
1103 mtspr SPRN_SRR1,r4
1104 SYNC
1105 RFI
1106#endif /* CONFIG_SMP */
1107
1108/*
1109 * Those generic dummy functions are kept for CPUs not
1110 * included in CONFIG_6xx
1111 */
1112_GLOBAL(__setup_cpu_power3)
1113 blr
1114_GLOBAL(__setup_cpu_generic)
1115 blr
1116
1117#if !defined(CONFIG_6xx) && !defined(CONFIG_POWER4)
1118_GLOBAL(__save_cpu_setup)
1119 blr
1120_GLOBAL(__restore_cpu_setup)
1121 blr
1122#endif /* !defined(CONFIG_6xx) && !defined(CONFIG_POWER4) */
1123
1124
1125/*
1126 * Load stuff into the MMU. Intended to be called with
1127 * IR=0 and DR=0.
1128 */
1129load_up_mmu:
1130 sync /* Force all PTE updates to finish */
1131 isync
1132 tlbia /* Clear all TLB entries */
1133 sync /* wait for tlbia/tlbie to finish */
1134 TLBSYNC /* ... on all CPUs */
1135 /* Load the SDR1 register (hash table base & size) */
1136 lis r6,_SDR1@ha
1137 tophys(r6,r6)
1138 lwz r6,_SDR1@l(r6)
1139 mtspr SPRN_SDR1,r6
1140#ifdef CONFIG_PPC64BRIDGE
1141 /* clear the ASR so we only use the pseudo-segment registers. */
1142 li r6,0
1143 mtasr r6
1144#endif /* CONFIG_PPC64BRIDGE */
1145 li r0,16 /* load up segment register values */
1146 mtctr r0 /* for context 0 */
1147 lis r3,0x2000 /* Ku = 1, VSID = 0 */
1148 li r4,0
11493: mtsrin r3,r4
1150 addi r3,r3,0x111 /* increment VSID */
1151 addis r4,r4,0x1000 /* address of next segment */
1152 bdnz 3b
1153#ifndef CONFIG_POWER4
1154/* Load the BAT registers with the values set up by MMU_init.
1155 MMU_init takes care of whether we're on a 601 or not. */
1156 mfpvr r3
1157 srwi r3,r3,16
1158 cmpwi r3,1
1159 lis r3,BATS@ha
1160 addi r3,r3,BATS@l
1161 tophys(r3,r3)
1162 LOAD_BAT(0,r3,r4,r5)
1163 LOAD_BAT(1,r3,r4,r5)
1164 LOAD_BAT(2,r3,r4,r5)
1165 LOAD_BAT(3,r3,r4,r5)
1166#endif /* CONFIG_POWER4 */
1167 blr
1168
1169/*
1170 * This is where the main kernel code starts.
1171 */
1172start_here:
1173 /* ptr to current */
1174 lis r2,init_task@h
1175 ori r2,r2,init_task@l
1176 /* Set up for using our exception vectors */
1177 /* ptr to phys current thread */
1178 tophys(r4,r2)
1179 addi r4,r4,THREAD /* init task's THREAD */
1180 CLR_TOP32(r4)
1181 mtspr SPRN_SPRG3,r4
1182 li r3,0
1183 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1184
1185 /* stack */
1186 lis r1,init_thread_union@ha
1187 addi r1,r1,init_thread_union@l
1188 li r0,0
1189 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1190/*
1191 * Do early bootinfo parsing, platform-specific initialization,
1192 * and set up the MMU.
1193 */
1194 mr r3,r31
1195 mr r4,r30
1196 mr r5,r29
1197 mr r6,r28
1198 mr r7,r27
1199 bl machine_init
1200 bl MMU_init
1201
1202#ifdef CONFIG_APUS
1203 /* Copy exception code to exception vector base on APUS. */
1204 lis r4,KERNELBASE@h
1205#ifdef CONFIG_APUS_FAST_EXCEPT
1206 lis r3,0xfff0 /* Copy to 0xfff00000 */
1207#else
1208 lis r3,0 /* Copy to 0x00000000 */
1209#endif
1210 li r5,0x4000 /* # bytes of memory to copy */
1211 li r6,0
1212 bl copy_and_flush /* copy the first 0x4000 bytes */
1213#endif /* CONFIG_APUS */
1214
1215/*
1216 * Go back to running unmapped so we can load up new values
1217 * for SDR1 (hash table pointer) and the segment registers
1218 * and change to using our exception vectors.
1219 */
1220 lis r4,2f@h
1221 ori r4,r4,2f@l
1222 tophys(r4,r4)
1223 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1224 FIX_SRR1(r3,r5)
1225 mtspr SPRN_SRR0,r4
1226 mtspr SPRN_SRR1,r3
1227 SYNC
1228 RFI
1229/* Load up the kernel context */
12302: bl load_up_mmu
1231
1232#ifdef CONFIG_BDI_SWITCH
1233 /* Add helper information for the Abatron bdiGDB debugger.
1234 * We do this here because we know the mmu is disabled, and
1235 * will be enabled for real in just a few instructions.
1236 */
1237 lis r5, abatron_pteptrs@h
1238 ori r5, r5, abatron_pteptrs@l
1239 stw r5, 0xf0(r0) /* This much match your Abatron config */
1240 lis r6, swapper_pg_dir@h
1241 ori r6, r6, swapper_pg_dir@l
1242 tophys(r5, r5)
1243 stw r6, 0(r5)
1244#endif /* CONFIG_BDI_SWITCH */
1245
1246/* Now turn on the MMU for real! */
1247 li r4,MSR_KERNEL
1248 FIX_SRR1(r4,r5)
1249 lis r3,start_kernel@h
1250 ori r3,r3,start_kernel@l
1251 mtspr SPRN_SRR0,r3
1252 mtspr SPRN_SRR1,r4
1253 SYNC
1254 RFI
1255
1256/*
1257 * Set up the segment registers for a new context.
1258 */
1259_GLOBAL(set_context)
1260 mulli r3,r3,897 /* multiply context by skew factor */
1261 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1262 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1263 li r0,NUM_USER_SEGMENTS
1264 mtctr r0
1265
1266#ifdef CONFIG_BDI_SWITCH
1267 /* Context switch the PTE pointer for the Abatron BDI2000.
1268 * The PGDIR is passed as second argument.
1269 */
1270 lis r5, KERNELBASE@h
1271 lwz r5, 0xf0(r5)
1272 stw r4, 0x4(r5)
1273#endif
1274 li r4,0
1275 isync
12763:
1277#ifdef CONFIG_PPC64BRIDGE
1278 slbie r4
1279#endif /* CONFIG_PPC64BRIDGE */
1280 mtsrin r3,r4
1281 addi r3,r3,0x111 /* next VSID */
1282 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1283 addis r4,r4,0x1000 /* address of next segment */
1284 bdnz 3b
1285 sync
1286 isync
1287 blr
1288
1289/*
1290 * An undocumented "feature" of 604e requires that the v bit
1291 * be cleared before changing BAT values.
1292 *
1293 * Also, newer IBM firmware does not clear bat3 and 4 so
1294 * this makes sure it's done.
1295 * -- Cort
1296 */
1297clear_bats:
1298 li r10,0
1299 mfspr r9,SPRN_PVR
1300 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1301 cmpwi r9, 1
1302 beq 1f
1303
1304 mtspr SPRN_DBAT0U,r10
1305 mtspr SPRN_DBAT0L,r10
1306 mtspr SPRN_DBAT1U,r10
1307 mtspr SPRN_DBAT1L,r10
1308 mtspr SPRN_DBAT2U,r10
1309 mtspr SPRN_DBAT2L,r10
1310 mtspr SPRN_DBAT3U,r10
1311 mtspr SPRN_DBAT3L,r10
13121:
1313 mtspr SPRN_IBAT0U,r10
1314 mtspr SPRN_IBAT0L,r10
1315 mtspr SPRN_IBAT1U,r10
1316 mtspr SPRN_IBAT1L,r10
1317 mtspr SPRN_IBAT2U,r10
1318 mtspr SPRN_IBAT2L,r10
1319 mtspr SPRN_IBAT3U,r10
1320 mtspr SPRN_IBAT3L,r10
1321BEGIN_FTR_SECTION
1322 /* Here's a tweak: at this point, CPU setup have
1323 * not been called yet, so HIGH_BAT_EN may not be
1324 * set in HID0 for the 745x processors. However, it
1325 * seems that doesn't affect our ability to actually
1326 * write to these SPRs.
1327 */
1328 mtspr SPRN_DBAT4U,r10
1329 mtspr SPRN_DBAT4L,r10
1330 mtspr SPRN_DBAT5U,r10
1331 mtspr SPRN_DBAT5L,r10
1332 mtspr SPRN_DBAT6U,r10
1333 mtspr SPRN_DBAT6L,r10
1334 mtspr SPRN_DBAT7U,r10
1335 mtspr SPRN_DBAT7L,r10
1336 mtspr SPRN_IBAT4U,r10
1337 mtspr SPRN_IBAT4L,r10
1338 mtspr SPRN_IBAT5U,r10
1339 mtspr SPRN_IBAT5L,r10
1340 mtspr SPRN_IBAT6U,r10
1341 mtspr SPRN_IBAT6L,r10
1342 mtspr SPRN_IBAT7U,r10
1343 mtspr SPRN_IBAT7L,r10
1344END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1345 blr
1346
1347flush_tlbs:
1348 lis r10, 0x40
13491: addic. r10, r10, -0x1000
1350 tlbie r10
1351 blt 1b
1352 sync
1353 blr
1354
1355mmu_off:
1356 addi r4, r3, __after_mmu_off - _start
1357 mfmsr r3
1358 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1359 beqlr
1360 andc r3,r3,r0
1361 mtspr SPRN_SRR0,r4
1362 mtspr SPRN_SRR1,r3
1363 sync
1364 RFI
1365
1366#ifndef CONFIG_POWER4
1367/*
1368 * Use the first pair of BAT registers to map the 1st 16MB
1369 * of RAM to KERNELBASE. From this point on we can't safely
1370 * call OF any more.
1371 */
1372initial_bats:
1373 lis r11,KERNELBASE@h
1374#ifndef CONFIG_PPC64BRIDGE
1375 mfspr r9,SPRN_PVR
1376 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1377 cmpwi 0,r9,1
1378 bne 4f
1379 ori r11,r11,4 /* set up BAT registers for 601 */
1380 li r8,0x7f /* valid, block length = 8MB */
1381 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1382 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1383 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1384 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1385 mtspr SPRN_IBAT1U,r9
1386 mtspr SPRN_IBAT1L,r10
1387 isync
1388 blr
1389#endif /* CONFIG_PPC64BRIDGE */
1390
13914: tophys(r8,r11)
1392#ifdef CONFIG_SMP
1393 ori r8,r8,0x12 /* R/W access, M=1 */
1394#else
1395 ori r8,r8,2 /* R/W access */
1396#endif /* CONFIG_SMP */
1397#ifdef CONFIG_APUS
1398 ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */
1399#else
1400 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1401#endif /* CONFIG_APUS */
1402
1403#ifdef CONFIG_PPC64BRIDGE
1404 /* clear out the high 32 bits in the BAT */
1405 clrldi r11,r11,32
1406 clrldi r8,r8,32
1407#endif /* CONFIG_PPC64BRIDGE */
1408 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1409 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1410 mtspr SPRN_IBAT0L,r8
1411 mtspr SPRN_IBAT0U,r11
1412 isync
1413 blr
1414
1415#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
1416setup_disp_bat:
1417 /*
1418 * setup the display bat prepared for us in prom.c
1419 */
1420 mflr r8
1421 bl reloc_offset
1422 mtlr r8
1423 addis r8,r3,disp_BAT@ha
1424 addi r8,r8,disp_BAT@l
1425 lwz r11,0(r8)
1426 lwz r8,4(r8)
1427 mfspr r9,SPRN_PVR
1428 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1429 cmpwi 0,r9,1
1430 beq 1f
1431 mtspr SPRN_DBAT3L,r8
1432 mtspr SPRN_DBAT3U,r11
1433 blr
14341: mtspr SPRN_IBAT3L,r8
1435 mtspr SPRN_IBAT3U,r11
1436 blr
1437
1438#endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */
1439
1440#else /* CONFIG_POWER4 */
1441/*
1442 * Load up the SDR1 and segment register values now
1443 * since we don't have the BATs.
1444 * Also make sure we are running in 32-bit mode.
1445 */
1446
1447initial_mm_power4:
1448 addis r14,r3,_SDR1@ha /* get the value from _SDR1 */
1449 lwz r14,_SDR1@l(r14) /* assume hash table below 4GB */
1450 mtspr SPRN_SDR1,r14
1451 slbia
1452 lis r4,0x2000 /* set pseudo-segment reg 12 */
1453 ori r5,r4,0x0ccc
1454 mtsr 12,r5
1455#if 0
1456 ori r5,r4,0x0888 /* set pseudo-segment reg 8 */
1457 mtsr 8,r5 /* (for access to serial port) */
1458#endif
1459#ifdef CONFIG_BOOTX_TEXT
1460 ori r5,r4,0x0999 /* set pseudo-segment reg 9 */
1461 mtsr 9,r5 /* (for access to screen) */
1462#endif
1463 mfmsr r0
1464 clrldi r0,r0,1
1465 sync
1466 mtmsr r0
1467 isync
1468 blr
1469
1470#endif /* CONFIG_POWER4 */
1471
1472#ifdef CONFIG_8260
1473/* Jump into the system reset for the rom.
1474 * We first disable the MMU, and then jump to the ROM reset address.
1475 *
1476 * r3 is the board info structure, r4 is the location for starting.
1477 * I use this for building a small kernel that can load other kernels,
1478 * rather than trying to write or rely on a rom monitor that can tftp load.
1479 */
1480 .globl m8260_gorom
1481m8260_gorom:
1482 mfmsr r0
1483 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1484 sync
1485 mtmsr r0
1486 sync
1487 mfspr r11, SPRN_HID0
1488 lis r10, 0
1489 ori r10,r10,HID0_ICE|HID0_DCE
1490 andc r11, r11, r10
1491 mtspr SPRN_HID0, r11
1492 isync
1493 li r5, MSR_ME|MSR_RI
1494 lis r6,2f@h
1495 addis r6,r6,-KERNELBASE@h
1496 ori r6,r6,2f@l
1497 mtspr SPRN_SRR0,r6
1498 mtspr SPRN_SRR1,r5
1499 isync
1500 sync
1501 rfi
15022:
1503 mtlr r4
1504 blr
1505#endif
1506
1507
1508/*
1509 * We put a few things here that have to be page-aligned.
1510 * This stuff goes at the beginning of the data segment,
1511 * which is page-aligned.
1512 */
1513 .data
1514 .globl sdata
1515sdata:
1516 .globl empty_zero_page
1517empty_zero_page:
1518 .space 4096
1519
1520 .globl swapper_pg_dir
1521swapper_pg_dir:
1522 .space 4096
1523
1524/*
1525 * This space gets a copy of optional info passed to us by the bootstrap
1526 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1527 */
1528 .globl cmd_line
1529cmd_line:
1530 .space 512
1531
1532 .globl intercept_table
1533intercept_table:
1534 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1535 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1536 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1537 .long 0, 0, 0, 0, 0, 0, 0, 0
1538 .long 0, 0, 0, 0, 0, 0, 0, 0
1539 .long 0, 0, 0, 0, 0, 0, 0, 0
1540
1541/* Room for two PTE pointers, usually the kernel and current user pointers
1542 * to their respective root page table.
1543 */
1544abatron_pteptrs:
1545 .space 8
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 21:03:42 -0500