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authorKumar Gala <galak@kernel.crashing.org>2011-11-02 11:15:30 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:38 -0500
commitffeb33d20c6217bb8f0ab46d3f1396021c00c24f (patch)
treecf814b306078ba3eebee9cfaf7497bd71b4c0d09 /arch/powerpc/boot/dts
parent3316a83c7c2335d92f924e080a2c7b9b144bc1ba (diff)
powerpc/85xx: Rework P1021MDS device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Added usb node for 2nd usb controller * Dropping "fsl,p1021-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-post.dtsi225
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi68
-rw-r--r--arch/powerpc/boot/dts/p1021mds.dts421
3 files changed, 314 insertions, 400 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
new file mode 100644
index 000000000000..38ba54d1e32e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -0,0 +1,225 @@
1/*
2 * P1021/P1012 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,mpc8548-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1021-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1021-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1021-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127
128/include/ "pq3-espi-0.dtsi"
129 spi@7000 {
130 fsl,espi-num-chipselects = <4>;
131 };
132
133/include/ "pq3-gpio-0.dtsi"
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,p1021-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x40000>; // L2,256K
140 interrupts = <16 2 0 0>;
141 };
142
143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi"
145
146/include/ "pq3-esdhc-0.dtsi"
147/include/ "pq3-sec3.3-0.dtsi"
148
149/include/ "pq3-mpic.dtsi"
150/include/ "pq3-mpic-timer-B.dtsi"
151
152/include/ "pq3-etsec2-0.dtsi"
153 enet0: enet0_grp2: ethernet@b0000 {
154 };
155
156/include/ "pq3-etsec2-1.dtsi"
157 enet1: enet1_grp2: ethernet@b1000 {
158 };
159
160/include/ "pq3-etsec2-2.dtsi"
161 enet2: enet2_grp2: ethernet@b2000 {
162 };
163
164 global-utilities@e0000 {
165 compatible = "fsl,p1021-guts";
166 reg = <0xe0000 0x1000>;
167 fsl,has-rstcr;
168 };
169};
170
171&qe {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 device_type = "qe";
175 compatible = "fsl,qe";
176 fsl,qe-num-riscs = <1>;
177 fsl,qe-num-snums = <28>;
178
179 qeic: interrupt-controller@80 {
180 interrupt-controller;
181 compatible = "fsl,qe-ic";
182 #address-cells = <0>;
183 #interrupt-cells = <1>;
184 reg = <0x80 0x80>;
185 interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44
186 };
187
188 ucc@2000 {
189 cell-index = <1>;
190 reg = <0x2000 0x200>;
191 interrupts = <32>;
192 interrupt-parent = <&qeic>;
193 };
194
195 mdio@2120 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 reg = <0x2120 0x18>;
199 compatible = "fsl,ucc-mdio";
200 };
201
202 ucc@2400 {
203 cell-index = <5>;
204 reg = <0x2400 0x200>;
205 interrupts = <40>;
206 interrupt-parent = <&qeic>;
207 };
208
209 muram@10000 {
210 #address-cells = <1>;
211 #size-cells = <1>;
212 compatible = "fsl,qe-muram", "fsl,cpm-muram";
213 ranges = <0x0 0x10000 0x6000>;
214
215 data-only@0 {
216 compatible = "fsl,qe-muram-data",
217 "fsl,cpm-muram-data";
218 reg = <0x0 0x6000>;
219 };
220 };
221};
222
223/include/ "pq3-etsec2-grp2-0.dtsi"
224/include/ "pq3-etsec2-grp2-1.dtsi"
225/include/ "pq3-etsec2-grp2-2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
new file mode 100644
index 000000000000..4abd54bc3308
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
@@ -0,0 +1,68 @@
1/*
2 * P1021/P1012 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1021";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,P1021@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61
62 PowerPC,P1021@1 {
63 device_type = "cpu";
64 reg = <0x1>;
65 next-level-cache = <&L2>;
66 };
67 };
68};
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
index ad5b85269004..b1bef1fa66da 100644
--- a/arch/powerpc/boot/dts/p1021mds.dts
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -9,53 +9,22 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/p1021si-pre.dtsi"
13/ { 13/ {
14 model = "fsl,P1021"; 14 model = "fsl,P1021";
15 compatible = "fsl,P1021MDS"; 15 compatible = "fsl,P1021MDS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 16
19 aliases { 17 aliases {
20 serial0 = &serial0;
21 serial1 = &serial1;
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3; 18 ethernet3 = &enet3;
26 ethernet4 = &enet4; 19 ethernet4 = &enet4;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,P1021@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 next-level-cache = <&L2>;
39 };
40
41 PowerPC,P1021@1 {
42 device_type = "cpu";
43 reg = <0x1>;
44 next-level-cache = <&L2>;
45 };
46 }; 20 };
47 21
48 memory { 22 memory {
49 device_type = "memory"; 23 device_type = "memory";
50 }; 24 };
51 25
52 localbus@ffe05000 { 26 lbc: localbus@ffe05000 {
53 #address-cells = <2>; 27 reg = <0x0 0xffe05000 0x0 0x1000>;
54 #size-cells = <1>;
55 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
56 reg = <0 0xffe05000 0 0x1000>;
57 interrupts = <19 2>;
58 interrupt-parent = <&mpic>;
59 28
60 /* NAND Flash, BCSR, PMC0/1*/ 29 /* NAND Flash, BCSR, PMC0/1*/
61 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000 30 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
@@ -138,99 +107,26 @@
138 }; 107 };
139 }; 108 };
140 109
141 soc@ffe00000 { 110 soc: soc@ffe00000 {
142
143 #address-cells = <1>;
144 #size-cells = <1>;
145 device_type = "soc";
146 compatible = "fsl,p1021-immr", "simple-bus"; 111 compatible = "fsl,p1021-immr", "simple-bus";
147 ranges = <0x0 0x0 0xffe00000 0x100000>; 112 ranges = <0x0 0x0 0xffe00000 0x100000>;
148 bus-frequency = <0>; // Filled out by uboot.
149
150 ecm-law@0 {
151 compatible = "fsl,ecm-law";
152 reg = <0x0 0x1000>;
153 fsl,num-laws = <12>;
154 };
155
156 ecm@1000 {
157 compatible = "fsl,p1021-ecm", "fsl,ecm";
158 reg = <0x1000 0x1000>;
159 interrupts = <16 2>;
160 interrupt-parent = <&mpic>;
161 };
162
163 memory-controller@2000 {
164 compatible = "fsl,p1021-memory-controller";
165 reg = <0x2000 0x1000>;
166 interrupt-parent = <&mpic>;
167 interrupts = <16 2>;
168 };
169 113
170 i2c@3000 { 114 i2c@3000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 cell-index = <0>;
174 compatible = "fsl-i2c";
175 reg = <0x3000 0x100>;
176 interrupts = <43 2>;
177 interrupt-parent = <&mpic>;
178 dfsrr;
179 rtc@68 { 115 rtc@68 {
180 compatible = "dallas,ds1374"; 116 compatible = "dallas,ds1374";
181 reg = <0x68>; 117 reg = <0x68>;
182 }; 118 };
183 }; 119 };
184 120
185 i2c@3100 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 cell-index = <1>;
189 compatible = "fsl-i2c";
190 reg = <0x3100 0x100>;
191 interrupts = <43 2>;
192 interrupt-parent = <&mpic>;
193 dfsrr;
194 };
195
196 serial0: serial@4500 {
197 cell-index = <0>;
198 device_type = "serial";
199 compatible = "ns16550";
200 reg = <0x4500 0x100>;
201 clock-frequency = <0>;
202 interrupts = <42 2>;
203 interrupt-parent = <&mpic>;
204 };
205
206 serial1: serial@4600 {
207 cell-index = <1>;
208 device_type = "serial";
209 compatible = "ns16550";
210 reg = <0x4600 0x100>;
211 clock-frequency = <0>;
212 interrupts = <42 2>;
213 interrupt-parent = <&mpic>;
214 };
215
216 spi@7000 { 121 spi@7000 {
217 cell-index = <0>; 122
218 #address-cells = <1>; 123 flash@0 {
219 #size-cells = <0>;
220 compatible = "fsl,espi";
221 reg = <0x7000 0x1000>;
222 interrupts = <59 0x2>;
223 interrupt-parent = <&mpic>;
224 espi,num-ss-bits = <4>;
225 mode = "cpu";
226
227 fsl_m25p80@0 {
228 #address-cells = <1>; 124 #address-cells = <1>;
229 #size-cells = <1>; 125 #size-cells = <1>;
230 compatible = "fsl,espi-flash"; 126 compatible = "spansion,s25sl12801";
231 reg = <0>; 127 reg = <0>;
232 linux,modalias = "fsl_m25p80";
233 spi-max-frequency = <40000000>; /* input clock */ 128 spi-max-frequency = <40000000>; /* input clock */
129
234 partition@u-boot { 130 partition@u-boot {
235 label = "u-boot-spi"; 131 label = "u-boot-spi";
236 reg = <0x00000000 0x00100000>; 132 reg = <0x00000000 0x00100000>;
@@ -253,237 +149,45 @@
253 }; 149 };
254 }; 150 };
255 151
256 gpio: gpio-controller@f000 {
257 #gpio-cells = <2>;
258 compatible = "fsl,mpc8572-gpio";
259 reg = <0xf000 0x100>;
260 interrupts = <47 0x2>;
261 interrupt-parent = <&mpic>;
262 gpio-controller;
263 };
264
265 L2: l2-cache-controller@20000 {
266 compatible = "fsl,p1021-l2-cache-controller";
267 reg = <0x20000 0x1000>;
268 cache-line-size = <32>; // 32 bytes
269 cache-size = <0x40000>; // L2,256K
270 interrupt-parent = <&mpic>;
271 interrupts = <16 2>;
272 };
273
274 dma@21300 {
275 #address-cells = <1>;
276 #size-cells = <1>;
277 compatible = "fsl,eloplus-dma";
278 reg = <0x21300 0x4>;
279 ranges = <0x0 0x21100 0x200>;
280 cell-index = <0>;
281 dma-channel@0 {
282 compatible = "fsl,eloplus-dma-channel";
283 reg = <0x0 0x80>;
284 cell-index = <0>;
285 interrupt-parent = <&mpic>;
286 interrupts = <20 2>;
287 };
288 dma-channel@80 {
289 compatible = "fsl,eloplus-dma-channel";
290 reg = <0x80 0x80>;
291 cell-index = <1>;
292 interrupt-parent = <&mpic>;
293 interrupts = <21 2>;
294 };
295 dma-channel@100 {
296 compatible = "fsl,eloplus-dma-channel";
297 reg = <0x100 0x80>;
298 cell-index = <2>;
299 interrupt-parent = <&mpic>;
300 interrupts = <22 2>;
301 };
302 dma-channel@180 {
303 compatible = "fsl,eloplus-dma-channel";
304 reg = <0x180 0x80>;
305 cell-index = <3>;
306 interrupt-parent = <&mpic>;
307 interrupts = <23 2>;
308 };
309 };
310
311 usb@22000 { 152 usb@22000 {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "fsl-usb2-dr";
315 reg = <0x22000 0x1000>;
316 interrupt-parent = <&mpic>;
317 interrupts = <28 0x2>;
318 phy_type = "ulpi"; 153 phy_type = "ulpi";
319 }; 154 };
320 155
321 mdio@24000 { 156 mdio@24000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,etsec2-mdio";
325 reg = <0x24000 0x1000 0xb0030 0x4>;
326
327 phy0: ethernet-phy@0 { 157 phy0: ethernet-phy@0 {
328 interrupt-parent = <&mpic>; 158 interrupts = <1 1 0 0>;
329 interrupts = <1 1>;
330 reg = <0x0>; 159 reg = <0x0>;
331 }; 160 };
332 phy1: ethernet-phy@1 { 161 phy1: ethernet-phy@1 {
333 interrupt-parent = <&mpic>; 162 interrupts = <2 1 0 0>;
334 interrupts = <2 1>;
335 reg = <0x1>; 163 reg = <0x1>;
336 }; 164 };
337 phy4: ethernet-phy@4 { 165 phy4: ethernet-phy@4 {
338 interrupt-parent = <&mpic>;
339 reg = <0x4>; 166 reg = <0x4>;
340 }; 167 };
341 }; 168 };
342 169
343 mdio@25000 { 170 mdio@25000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "fsl,etsec2-tbi";
347 reg = <0x25000 0x1000 0xb1030 0x4>;
348 tbi0: tbi-phy@11 { 171 tbi0: tbi-phy@11 {
349 reg = <0x11>; 172 reg = <0x11>;
350 device_type = "tbi-phy"; 173 device_type = "tbi-phy";
351 }; 174 };
352 }; 175 };
353 176
354 enet0: ethernet@B0000 { 177 ethernet@b0000 {
355 #address-cells = <1>;
356 #size-cells = <1>;
357 cell-index = <0>;
358 device_type = "network";
359 model = "eTSEC";
360 compatible = "fsl,etsec2";
361 fsl,num_rx_queues = <0x8>;
362 fsl,num_tx_queues = <0x8>;
363 local-mac-address = [ 00 00 00 00 00 00 ];
364 interrupt-parent = <&mpic>;
365 phy-handle = <&phy0>; 178 phy-handle = <&phy0>;
366 phy-connection-type = "rgmii-id"; 179 phy-connection-type = "rgmii-id";
367 queue-group@0{
368 #address-cells = <1>;
369 #size-cells = <1>;
370 reg = <0xB0000 0x1000>;
371 interrupts = <29 2 30 2 34 2>;
372 };
373 queue-group@1{
374 #address-cells = <1>;
375 #size-cells = <1>;
376 reg = <0xB4000 0x1000>;
377 interrupts = <17 2 18 2 24 2>;
378 };
379 }; 180 };
380 181
381 enet1: ethernet@B1000 { 182 ethernet@b1000 {
382 #address-cells = <1>;
383 #size-cells = <1>;
384 cell-index = <0>;
385 device_type = "network";
386 model = "eTSEC";
387 compatible = "fsl,etsec2";
388 fsl,num_rx_queues = <0x8>;
389 fsl,num_tx_queues = <0x8>;
390 local-mac-address = [ 00 00 00 00 00 00 ];
391 interrupt-parent = <&mpic>;
392 phy-handle = <&phy4>; 183 phy-handle = <&phy4>;
393 tbi-handle = <&tbi0>; 184 tbi-handle = <&tbi0>;
394 phy-connection-type = "sgmii"; 185 phy-connection-type = "sgmii";
395 queue-group@0{
396 #address-cells = <1>;
397 #size-cells = <1>;
398 reg = <0xB1000 0x1000>;
399 interrupts = <35 2 36 2 40 2>;
400 };
401 queue-group@1{
402 #address-cells = <1>;
403 #size-cells = <1>;
404 reg = <0xB5000 0x1000>;
405 interrupts = <51 2 52 2 67 2>;
406 };
407 }; 186 };
408 187
409 enet2: ethernet@B2000 { 188 ethernet@b2000 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 cell-index = <0>;
413 device_type = "network";
414 model = "eTSEC";
415 compatible = "fsl,etsec2";
416 fsl,num_rx_queues = <0x8>;
417 fsl,num_tx_queues = <0x8>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupt-parent = <&mpic>;
420 phy-handle = <&phy1>; 189 phy-handle = <&phy1>;
421 phy-connection-type = "rgmii-id"; 190 phy-connection-type = "rgmii-id";
422 queue-group@0{
423 #address-cells = <1>;
424 #size-cells = <1>;
425 reg = <0xB2000 0x1000>;
426 interrupts = <31 2 32 2 33 2>;
427 };
428 queue-group@1{
429 #address-cells = <1>;
430 #size-cells = <1>;
431 reg = <0xB6000 0x1000>;
432 interrupts = <25 2 26 2 27 2>;
433 };
434 };
435
436 sdhci@2e000 {
437 compatible = "fsl,p1021-esdhc", "fsl,esdhc";
438 reg = <0x2e000 0x1000>;
439 interrupts = <72 0x2>;
440 interrupt-parent = <&mpic>;
441 /* Filled in by U-Boot */
442 clock-frequency = <0>;
443 };
444
445 crypto@30000 {
446 compatible = "fsl,sec3.3", "fsl,sec3.1",
447 "fsl,sec3.0", "fsl,sec2.4",
448 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
449 reg = <0x30000 0x10000>;
450 interrupts = <45 2 58 2>;
451 interrupt-parent = <&mpic>;
452 fsl,num-channels = <4>;
453 fsl,channel-fifo-len = <24>;
454 fsl,exec-units-mask = <0x97c>;
455 fsl,descriptor-types-mask = <0x3a30abf>;
456 };
457
458 mpic: pic@40000 {
459 interrupt-controller;
460 #address-cells = <0>;
461 #interrupt-cells = <2>;
462 reg = <0x40000 0x40000>;
463 compatible = "chrp,open-pic";
464 device_type = "open-pic";
465 };
466
467 msi@41600 {
468 compatible = "fsl,p1021-msi", "fsl,mpic-msi";
469 reg = <0x41600 0x80>;
470 msi-available-ranges = <0 0x100>;
471 interrupts = <
472 0xe0 0
473 0xe1 0
474 0xe2 0
475 0xe3 0
476 0xe4 0
477 0xe5 0
478 0xe6 0
479 0xe7 0>;
480 interrupt-parent = <&mpic>;
481 };
482
483 global-utilities@e0000 { //global utilities block
484 compatible = "fsl,p1021-guts";
485 reg = <0xe0000 0x1000>;
486 fsl,has-rstcr;
487 }; 191 };
488 192
489 par_io@e0100 { 193 par_io@e0100 {
@@ -499,8 +203,7 @@
499 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 203 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
500 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 204 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
501 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ 205 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
502 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 206 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
503*/
504 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ 207 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
505 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ 208 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
506 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ 209 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
@@ -535,31 +238,10 @@
535 }; 238 };
536 239
537 pci0: pcie@ffe09000 { 240 pci0: pcie@ffe09000 {
538 compatible = "fsl,mpc8548-pcie";
539 device_type = "pci";
540 #interrupt-cells = <1>;
541 #size-cells = <2>;
542 #address-cells = <3>;
543 reg = <0 0xffe09000 0 0x1000>; 241 reg = <0 0xffe09000 0 0x1000>;
544 bus-range = <0 255>;
545 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 242 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
546 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 243 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
547 clock-frequency = <33333333>;
548 interrupt-parent = <&mpic>;
549 interrupts = <16 2>;
550 interrupt-map-mask = <0xf800 0 0 7>;
551 interrupt-map = <
552 /* IDSEL 0x0 */
553 0000 0 0 1 &mpic 4 1
554 0000 0 0 2 &mpic 5 1
555 0000 0 0 3 &mpic 6 1
556 0000 0 0 4 &mpic 7 1
557 >;
558 pcie@0 { 244 pcie@0 {
559 reg = <0x0 0x0 0x0 0x0 0x0>;
560 #size-cells = <2>;
561 #address-cells = <3>;
562 device_type = "pci";
563 ranges = <0x2000000 0x0 0xa0000000 245 ranges = <0x2000000 0x0 0xa0000000
564 0x2000000 0x0 0xa0000000 246 0x2000000 0x0 0xa0000000
565 0x0 0x20000000 247 0x0 0x20000000
@@ -571,31 +253,10 @@
571 }; 253 };
572 254
573 pci1: pcie@ffe0a000 { 255 pci1: pcie@ffe0a000 {
574 compatible = "fsl,mpc8548-pcie";
575 device_type = "pci";
576 #interrupt-cells = <1>;
577 #size-cells = <2>;
578 #address-cells = <3>;
579 reg = <0 0xffe0a000 0 0x1000>; 256 reg = <0 0xffe0a000 0 0x1000>;
580 bus-range = <0 255>;
581 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 257 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
582 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 258 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
583 clock-frequency = <33333333>;
584 interrupt-parent = <&mpic>;
585 interrupts = <16 2>;
586 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = <
588 /* IDSEL 0x0 */
589 0000 0 0 1 &mpic 0 1
590 0000 0 0 2 &mpic 1 1
591 0000 0 0 3 &mpic 2 1
592 0000 0 0 4 &mpic 3 1
593 >;
594 pcie@0 { 259 pcie@0 {
595 reg = <0x0 0x0 0x0 0x0 0x0>;
596 #size-cells = <2>;
597 #address-cells = <3>;
598 device_type = "pci";
599 ranges = <0x2000000 0x0 0xc0000000 260 ranges = <0x2000000 0x0 0xc0000000
600 0x2000000 0x0 0xc0000000 261 0x2000000 0x0 0xc0000000
601 0x0 0x20000000 262 0x0 0x20000000
@@ -606,36 +267,16 @@
606 }; 267 };
607 }; 268 };
608 269
609 qe@ffe80000 { 270 qe: qe@ffe80000 {
610 #address-cells = <1>;
611 #size-cells = <1>;
612 device_type = "qe";
613 compatible = "fsl,qe";
614 ranges = <0x0 0x0 0xffe80000 0x40000>; 271 ranges = <0x0 0x0 0xffe80000 0x40000>;
615 reg = <0 0xffe80000 0 0x480>; 272 reg = <0 0xffe80000 0 0x480>;
616 brg-frequency = <0>; 273 brg-frequency = <0>;
617 bus-frequency = <0>; 274 bus-frequency = <0>;
618 fsl,qe-num-riscs = <1>;
619 fsl,qe-num-snums = <28>;
620 status = "disabled"; /* no firmware loaded */ 275 status = "disabled"; /* no firmware loaded */
621 276
622 qeic: interrupt-controller@80 {
623 interrupt-controller;
624 compatible = "fsl,qe-ic";
625 #address-cells = <0>;
626 #interrupt-cells = <1>;
627 reg = <0x80 0x80>;
628 interrupts = <63 2 60 2>; //high:47 low:44
629 interrupt-parent = <&mpic>;
630 };
631
632 enet3: ucc@2000 { 277 enet3: ucc@2000 {
633 device_type = "network"; 278 device_type = "network";
634 compatible = "ucc_geth"; 279 compatible = "ucc_geth";
635 cell-index = <1>;
636 reg = <0x2000 0x200>;
637 interrupts = <32>;
638 interrupt-parent = <&qeic>;
639 local-mac-address = [ 00 00 00 00 00 00 ]; 280 local-mac-address = [ 00 00 00 00 00 00 ];
640 rx-clock-name = "clk12"; 281 rx-clock-name = "clk12";
641 tx-clock-name = "clk9"; 282 tx-clock-name = "clk9";
@@ -645,20 +286,15 @@
645 }; 286 };
646 287
647 mdio@2120 { 288 mdio@2120 {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 reg = <0x2120 0x18>;
651 compatible = "fsl,ucc-mdio";
652
653 qe_phy0: ethernet-phy@0 { 289 qe_phy0: ethernet-phy@0 {
654 interrupt-parent = <&mpic>; 290 interrupt-parent = <&mpic>;
655 interrupts = <4 1>; 291 interrupts = <4 1 0 0>;
656 reg = <0x0>; 292 reg = <0x0>;
657 device_type = "ethernet-phy"; 293 device_type = "ethernet-phy";
658 }; 294 };
659 qe_phy1: ethernet-phy@03 { 295 qe_phy1: ethernet-phy@03 {
660 interrupt-parent = <&mpic>; 296 interrupt-parent = <&mpic>;
661 interrupts = <5 1>; 297 interrupts = <5 1 0 0>;
662 reg = <0x3>; 298 reg = <0x3>;
663 device_type = "ethernet-phy"; 299 device_type = "ethernet-phy";
664 }; 300 };
@@ -671,10 +307,6 @@
671 enet4: ucc@2400 { 307 enet4: ucc@2400 {
672 device_type = "network"; 308 device_type = "network";
673 compatible = "ucc_geth"; 309 compatible = "ucc_geth";
674 cell-index = <5>;
675 reg = <0x2400 0x200>;
676 interrupts = <40>;
677 interrupt-parent = <&qeic>;
678 local-mac-address = [ 00 00 00 00 00 00 ]; 310 local-mac-address = [ 00 00 00 00 00 00 ];
679 rx-clock-name = "none"; 311 rx-clock-name = "none";
680 tx-clock-name = "clk13"; 312 tx-clock-name = "clk13";
@@ -682,18 +314,7 @@
682 phy-handle = <&qe_phy1>; 314 phy-handle = <&qe_phy1>;
683 phy-connection-type = "rmii"; 315 phy-connection-type = "rmii";
684 }; 316 };
685
686 muram@10000 {
687 #address-cells = <1>;
688 #size-cells = <1>;
689 compatible = "fsl,qe-muram", "fsl,cpm-muram";
690 ranges = <0x0 0x10000 0x6000>;
691
692 data-only@0 {
693 compatible = "fsl,qe-muram-data",
694 "fsl,cpm-muram-data";
695 reg = <0x0 0x6000>;
696 };
697 };
698 }; 317 };
699}; 318};
319
320/include/ "fsl/p1021si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 14:21:49 -0500