diff options
author | Kumar Gala <galak@kernel.crashing.org> | 2007-09-12 12:52:31 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2007-09-14 09:53:16 -0400 |
commit | f0c8ac8083cbd9347b398bfddcca20f1e2786016 (patch) | |
tree | 7fb8b26ef9242dfba1db898a476437ed234f7989 /arch/powerpc/boot/dts/mpc8555cds.dts | |
parent | 5d54ddcbcf931bf07cd1ce262bda4674ebd1427f (diff) |
[POWERPC] DTS cleanup
Removed the following cruft from .dts files:
* 32-bit in cpu node -- doesn't exist in any spec and not used by kernel
* removed built-in (chrp legacy)
* Removed #interrupt-cells in places they don't need to be set
* Fixed ranges on lite5200*
* Removed clock-frequency from i8259 pic node, not sure where this came from
* Removed big-endian from i8259 pic nodes, this was just bogus
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8555cds.dts')
-rw-r--r-- | arch/powerpc/boot/dts/mpc8555cds.dts | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index c3c888252121..ce11d11293d0 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts | |||
@@ -30,7 +30,6 @@ | |||
30 | timebase-frequency = <0>; // 33 MHz, from uboot | 30 | timebase-frequency = <0>; // 33 MHz, from uboot |
31 | bus-frequency = <0>; // 166 MHz | 31 | bus-frequency = <0>; // 166 MHz |
32 | clock-frequency = <0>; // 825 MHz, from uboot | 32 | clock-frequency = <0>; // 825 MHz, from uboot |
33 | 32-bit; | ||
34 | }; | 33 | }; |
35 | }; | 34 | }; |
36 | 35 | ||
@@ -42,7 +41,6 @@ | |||
42 | soc8555@e0000000 { | 41 | soc8555@e0000000 { |
43 | #address-cells = <1>; | 42 | #address-cells = <1>; |
44 | #size-cells = <1>; | 43 | #size-cells = <1>; |
45 | #interrupt-cells = <2>; | ||
46 | device_type = "soc"; | 44 | device_type = "soc"; |
47 | ranges = <0 e0000000 00100000>; | 45 | ranges = <0 e0000000 00100000>; |
48 | reg = <e0000000 00100000>; // CCSRBAR 1M | 46 | reg = <e0000000 00100000>; // CCSRBAR 1M |
@@ -197,15 +195,12 @@ | |||
197 | device_type = "pci"; | 195 | device_type = "pci"; |
198 | 196 | ||
199 | i8259@19000 { | 197 | i8259@19000 { |
200 | clock-frequency = <0>; | ||
201 | interrupt-controller; | 198 | interrupt-controller; |
202 | device_type = "interrupt-controller"; | 199 | device_type = "interrupt-controller"; |
203 | reg = <19000 0 0 0 1>; | 200 | reg = <19000 0 0 0 1>; |
204 | #address-cells = <0>; | 201 | #address-cells = <0>; |
205 | #interrupt-cells = <2>; | 202 | #interrupt-cells = <2>; |
206 | built-in; | ||
207 | compatible = "chrp,iic"; | 203 | compatible = "chrp,iic"; |
208 | big-endian; | ||
209 | interrupts = <1>; | 204 | interrupts = <1>; |
210 | interrupt-parent = <&pci1>; | 205 | interrupt-parent = <&pci1>; |
211 | }; | 206 | }; |
@@ -240,7 +235,6 @@ | |||
240 | #address-cells = <0>; | 235 | #address-cells = <0>; |
241 | #interrupt-cells = <2>; | 236 | #interrupt-cells = <2>; |
242 | reg = <40000 40000>; | 237 | reg = <40000 40000>; |
243 | built-in; | ||
244 | compatible = "chrp,open-pic"; | 238 | compatible = "chrp,open-pic"; |
245 | device_type = "open-pic"; | 239 | device_type = "open-pic"; |
246 | big-endian; | 240 | big-endian; |