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authorStefan Roese <sr@denx.de>2009-08-13 00:30:44 -0400
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2009-08-31 08:24:14 -0400
commitf661be6c8af3ae357e159c3ac6d6aea4aaf7581c (patch)
tree5b527e581a0231d6feca8e56a38fd27c5540330f /arch/powerpc/boot/dts/arches.dts
parent77c0a700c1c292edafa11c1e52821ce4636f81b0 (diff)
powerpc/44x: Update Arches dts
This patch adds some nodes to the AMCC Arches dts: - L2 cache support - NOR FLASH mapping with default partitioning - I2C HWMON device (AD7414) Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot/dts/arches.dts')
-rw-r--r--arch/powerpc/boot/dts/arches.dts50
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/arches.dts b/arch/powerpc/boot/dts/arches.dts
index d9113b1e8c1d..414ef8b7e575 100644
--- a/arch/powerpc/boot/dts/arches.dts
+++ b/arch/powerpc/boot/dts/arches.dts
@@ -124,6 +124,16 @@
124 dcr-reg = <0x00c 0x002>; 124 dcr-reg = <0x00c 0x002>;
125 }; 125 };
126 126
127 L2C0: l2c {
128 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
129 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
130 0x030 0x008>; /* L2 cache DCR's */
131 cache-line-size = <32>; /* 32 bytes */
132 cache-size = <262144>; /* L2, 256K */
133 interrupt-parent = <&UIC1>;
134 interrupts = <11 1>;
135 };
136
127 plb { 137 plb {
128 compatible = "ibm,plb-460gt", "ibm,plb4"; 138 compatible = "ibm,plb-460gt", "ibm,plb4";
129 #address-cells = <2>; 139 #address-cells = <2>;
@@ -168,6 +178,38 @@
168 /* ranges property is supplied by U-Boot */ 178 /* ranges property is supplied by U-Boot */
169 interrupts = <0x6 0x4>; 179 interrupts = <0x6 0x4>;
170 interrupt-parent = <&UIC1>; 180 interrupt-parent = <&UIC1>;
181
182 nor_flash@0,0 {
183 compatible = "amd,s29gl256n", "cfi-flash";
184 bank-width = <2>;
185 reg = <0x00000000 0x00000000 0x02000000>;
186 #address-cells = <1>;
187 #size-cells = <1>;
188 partition@0 {
189 label = "kernel";
190 reg = <0x00000000 0x001e0000>;
191 };
192 partition@1e0000 {
193 label = "dtb";
194 reg = <0x001e0000 0x00020000>;
195 };
196 partition@200000 {
197 label = "root";
198 reg = <0x00200000 0x00200000>;
199 };
200 partition@400000 {
201 label = "user";
202 reg = <0x00400000 0x01b60000>;
203 };
204 partition@1f60000 {
205 label = "env";
206 reg = <0x01f60000 0x00040000>;
207 };
208 partition@1fa0000 {
209 label = "u-boot";
210 reg = <0x01fa0000 0x00060000>;
211 };
212 };
171 }; 213 };
172 214
173 UART0: serial@ef600300 { 215 UART0: serial@ef600300 {
@@ -186,6 +228,14 @@
186 reg = <0xef600700 0x00000014>; 228 reg = <0xef600700 0x00000014>;
187 interrupt-parent = <&UIC0>; 229 interrupt-parent = <&UIC0>;
188 interrupts = <0x2 0x4>; 230 interrupts = <0x2 0x4>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 sttm@4a {
234 compatible = "ad,ad7414";
235 reg = <0x4a>;
236 interrupt-parent = <&UIC1>;
237 interrupts = <0x0 0x8>;
238 };
189 }; 239 };
190 240
191 IIC1: i2c@ef600800 { 241 IIC1: i2c@ef600800 {