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authorManuel Lauss <manuel.lauss@googlemail.com>2011-08-12 05:39:45 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-10-24 18:34:24 -0400
commit3766386037827fe7064f57f9aec27b3b5e9417aa (patch)
tree306a7b1ccf3100469fd711af37963801d8d387c0 /arch/mips
parent50d5676ebac57c187ac347bae24290f0dc16fdbe (diff)
MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines
Now that no driver any longer depends on the CONFIG_SOC_AU1??? symbols, it's time to get rid of them: Move some of the platform devices to the boards which can use them, Rename a few (unused) constants in the header, Replace them with MIPS_ALCHEMY in the various Kconfig files. Finally delete them altogether from the Alchemy Kconfig file. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kconfig2
-rw-r--r--arch/mips/alchemy/Kconfig50
-rw-r--r--arch/mips/alchemy/common/platform.c175
-rw-r--r--arch/mips/alchemy/devboards/db1200/platform.c78
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c4
-rw-r--r--arch/mips/alchemy/devboards/db1x00/platform.c32
-rw-r--r--arch/mips/alchemy/devboards/pb1100/platform.c29
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c137
-rw-r--r--arch/mips/alchemy/devboards/pb1500/platform.c1
-rw-r--r--arch/mips/alchemy/devboards/pb1550/platform.c33
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h203
11 files changed, 410 insertions, 334 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b122adc8bdbb..d4d569b158fd 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -47,6 +47,8 @@ config MIPS_ALCHEMY
47 select GENERIC_GPIO 47 select GENERIC_GPIO
48 select ARCH_WANT_OPTIONAL_GPIOLIB 48 select ARCH_WANT_OPTIONAL_GPIOLIB
49 select SYS_SUPPORTS_ZBOOT 49 select SYS_SUPPORTS_ZBOOT
50 select USB_ARCH_HAS_OHCI
51 select USB_ARCH_HAS_EHCI
50 52
51config AR7 53config AR7
52 bool "Texas Instruments AR7" 54 bool "Texas Instruments AR7"
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 2ccfd4a135bc..2a68be6a1b97 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -18,20 +18,20 @@ config MIPS_MTX1
18 bool "4G Systems MTX-1 board" 18 bool "4G Systems MTX-1 board"
19 select DMA_NONCOHERENT 19 select DMA_NONCOHERENT
20 select HW_HAS_PCI 20 select HW_HAS_PCI
21 select SOC_AU1500 21 select ALCHEMY_GPIOINT_AU1000
22 select SYS_SUPPORTS_LITTLE_ENDIAN 22 select SYS_SUPPORTS_LITTLE_ENDIAN
23 select SYS_HAS_EARLY_PRINTK 23 select SYS_HAS_EARLY_PRINTK
24 24
25config MIPS_BOSPORUS 25config MIPS_BOSPORUS
26 bool "Alchemy Bosporus board" 26 bool "Alchemy Bosporus board"
27 select SOC_AU1500 27 select ALCHEMY_GPIOINT_AU1000
28 select DMA_NONCOHERENT 28 select DMA_NONCOHERENT
29 select SYS_SUPPORTS_LITTLE_ENDIAN 29 select SYS_SUPPORTS_LITTLE_ENDIAN
30 select SYS_HAS_EARLY_PRINTK 30 select SYS_HAS_EARLY_PRINTK
31 31
32config MIPS_DB1000 32config MIPS_DB1000
33 bool "Alchemy DB1000 board" 33 bool "Alchemy DB1000 board"
34 select SOC_AU1000 34 select ALCHEMY_GPIOINT_AU1000
35 select DMA_NONCOHERENT 35 select DMA_NONCOHERENT
36 select HW_HAS_PCI 36 select HW_HAS_PCI
37 select SYS_SUPPORTS_LITTLE_ENDIAN 37 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -39,14 +39,14 @@ config MIPS_DB1000
39 39
40config MIPS_DB1100 40config MIPS_DB1100
41 bool "Alchemy DB1100 board" 41 bool "Alchemy DB1100 board"
42 select SOC_AU1100 42 select ALCHEMY_GPIOINT_AU1000
43 select DMA_NONCOHERENT 43 select DMA_NONCOHERENT
44 select SYS_SUPPORTS_LITTLE_ENDIAN 44 select SYS_SUPPORTS_LITTLE_ENDIAN
45 select SYS_HAS_EARLY_PRINTK 45 select SYS_HAS_EARLY_PRINTK
46 46
47config MIPS_DB1200 47config MIPS_DB1200
48 bool "Alchemy DB1200 board" 48 bool "Alchemy DB1200 board"
49 select SOC_AU1200 49 select ALCHEMY_GPIOINT_AU1000
50 select DMA_COHERENT 50 select DMA_COHERENT
51 select MIPS_DISABLE_OBSOLETE_IDE 51 select MIPS_DISABLE_OBSOLETE_IDE
52 select SYS_SUPPORTS_LITTLE_ENDIAN 52 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -54,7 +54,7 @@ config MIPS_DB1200
54 54
55config MIPS_DB1500 55config MIPS_DB1500
56 bool "Alchemy DB1500 board" 56 bool "Alchemy DB1500 board"
57 select SOC_AU1500 57 select ALCHEMY_GPIOINT_AU1000
58 select DMA_NONCOHERENT 58 select DMA_NONCOHERENT
59 select HW_HAS_PCI 59 select HW_HAS_PCI
60 select MIPS_DISABLE_OBSOLETE_IDE 60 select MIPS_DISABLE_OBSOLETE_IDE
@@ -64,7 +64,7 @@ config MIPS_DB1500
64 64
65config MIPS_DB1550 65config MIPS_DB1550
66 bool "Alchemy DB1550 board" 66 bool "Alchemy DB1550 board"
67 select SOC_AU1550 67 select ALCHEMY_GPIOINT_AU1000
68 select HW_HAS_PCI 68 select HW_HAS_PCI
69 select DMA_NONCOHERENT 69 select DMA_NONCOHERENT
70 select MIPS_DISABLE_OBSOLETE_IDE 70 select MIPS_DISABLE_OBSOLETE_IDE
@@ -74,13 +74,13 @@ config MIPS_DB1550
74config MIPS_MIRAGE 74config MIPS_MIRAGE
75 bool "Alchemy Mirage board" 75 bool "Alchemy Mirage board"
76 select DMA_NONCOHERENT 76 select DMA_NONCOHERENT
77 select SOC_AU1500 77 select ALCHEMY_GPIOINT_AU1000
78 select SYS_SUPPORTS_LITTLE_ENDIAN 78 select SYS_SUPPORTS_LITTLE_ENDIAN
79 select SYS_HAS_EARLY_PRINTK 79 select SYS_HAS_EARLY_PRINTK
80 80
81config MIPS_PB1000 81config MIPS_PB1000
82 bool "Alchemy PB1000 board" 82 bool "Alchemy PB1000 board"
83 select SOC_AU1000 83 select ALCHEMY_GPIOINT_AU1000
84 select DMA_NONCOHERENT 84 select DMA_NONCOHERENT
85 select HW_HAS_PCI 85 select HW_HAS_PCI
86 select SWAP_IO_SPACE 86 select SWAP_IO_SPACE
@@ -89,7 +89,7 @@ config MIPS_PB1000
89 89
90config MIPS_PB1100 90config MIPS_PB1100
91 bool "Alchemy PB1100 board" 91 bool "Alchemy PB1100 board"
92 select SOC_AU1100 92 select ALCHEMY_GPIOINT_AU1000
93 select DMA_NONCOHERENT 93 select DMA_NONCOHERENT
94 select HW_HAS_PCI 94 select HW_HAS_PCI
95 select SWAP_IO_SPACE 95 select SWAP_IO_SPACE
@@ -98,7 +98,7 @@ config MIPS_PB1100
98 98
99config MIPS_PB1200 99config MIPS_PB1200
100 bool "Alchemy PB1200 board" 100 bool "Alchemy PB1200 board"
101 select SOC_AU1200 101 select ALCHEMY_GPIOINT_AU1000
102 select DMA_NONCOHERENT 102 select DMA_NONCOHERENT
103 select MIPS_DISABLE_OBSOLETE_IDE 103 select MIPS_DISABLE_OBSOLETE_IDE
104 select SYS_SUPPORTS_LITTLE_ENDIAN 104 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -106,7 +106,7 @@ config MIPS_PB1200
106 106
107config MIPS_PB1500 107config MIPS_PB1500
108 bool "Alchemy PB1500 board" 108 bool "Alchemy PB1500 board"
109 select SOC_AU1500 109 select ALCHEMY_GPIOINT_AU1000
110 select DMA_NONCOHERENT 110 select DMA_NONCOHERENT
111 select HW_HAS_PCI 111 select HW_HAS_PCI
112 select SYS_SUPPORTS_LITTLE_ENDIAN 112 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -114,7 +114,7 @@ config MIPS_PB1500
114 114
115config MIPS_PB1550 115config MIPS_PB1550
116 bool "Alchemy PB1550 board" 116 bool "Alchemy PB1550 board"
117 select SOC_AU1550 117 select ALCHEMY_GPIOINT_AU1000
118 select DMA_NONCOHERENT 118 select DMA_NONCOHERENT
119 select HW_HAS_PCI 119 select HW_HAS_PCI
120 select MIPS_DISABLE_OBSOLETE_IDE 120 select MIPS_DISABLE_OBSOLETE_IDE
@@ -124,13 +124,13 @@ config MIPS_PB1550
124config MIPS_XXS1500 124config MIPS_XXS1500
125 bool "MyCable XXS1500 board" 125 bool "MyCable XXS1500 board"
126 select DMA_NONCOHERENT 126 select DMA_NONCOHERENT
127 select SOC_AU1500 127 select ALCHEMY_GPIOINT_AU1000
128 select SYS_SUPPORTS_LITTLE_ENDIAN 128 select SYS_SUPPORTS_LITTLE_ENDIAN
129 select SYS_HAS_EARLY_PRINTK 129 select SYS_HAS_EARLY_PRINTK
130 130
131config MIPS_GPR 131config MIPS_GPR
132 bool "Trapeze ITS GPR board" 132 bool "Trapeze ITS GPR board"
133 select SOC_AU1550 133 select ALCHEMY_GPIOINT_AU1000
134 select HW_HAS_PCI 134 select HW_HAS_PCI
135 select DMA_NONCOHERENT 135 select DMA_NONCOHERENT
136 select MIPS_DISABLE_OBSOLETE_IDE 136 select MIPS_DISABLE_OBSOLETE_IDE
@@ -138,23 +138,3 @@ config MIPS_GPR
138 select SYS_HAS_EARLY_PRINTK 138 select SYS_HAS_EARLY_PRINTK
139 139
140endchoice 140endchoice
141
142config SOC_AU1000
143 bool
144 select ALCHEMY_GPIOINT_AU1000
145
146config SOC_AU1100
147 bool
148 select ALCHEMY_GPIOINT_AU1000
149
150config SOC_AU1500
151 bool
152 select ALCHEMY_GPIOINT_AU1000
153
154config SOC_AU1550
155 bool
156 select ALCHEMY_GPIOINT_AU1000
157
158config SOC_AU1200
159 bool
160 select ALCHEMY_GPIOINT_AU1000
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 657ae2778374..c8e5d72a5826 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -189,159 +189,6 @@ static void __init alchemy_setup_usb(int ctype)
189 } 189 }
190} 190}
191 191
192/*** AU1100 LCD controller ***/
193
194#ifdef CONFIG_FB_AU1100
195static struct resource au1100_lcd_resources[] = {
196 [0] = {
197 .start = AU1100_LCD_PHYS_ADDR,
198 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
199 .flags = IORESOURCE_MEM,
200 },
201 [1] = {
202 .start = AU1100_LCD_INT,
203 .end = AU1100_LCD_INT,
204 .flags = IORESOURCE_IRQ,
205 }
206};
207
208static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
209
210static struct platform_device au1100_lcd_device = {
211 .name = "au1100-lcd",
212 .id = 0,
213 .dev = {
214 .dma_mask = &au1100_lcd_dmamask,
215 .coherent_dma_mask = DMA_BIT_MASK(32),
216 },
217 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
218 .resource = au1100_lcd_resources,
219};
220#endif
221
222#ifdef CONFIG_SOC_AU1200
223
224static struct resource au1200_lcd_resources[] = {
225 [0] = {
226 .start = AU1200_LCD_PHYS_ADDR,
227 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
228 .flags = IORESOURCE_MEM,
229 },
230 [1] = {
231 .start = AU1200_LCD_INT,
232 .end = AU1200_LCD_INT,
233 .flags = IORESOURCE_IRQ,
234 }
235};
236
237static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
238
239static struct platform_device au1200_lcd_device = {
240 .name = "au1200-lcd",
241 .id = 0,
242 .dev = {
243 .dma_mask = &au1200_lcd_dmamask,
244 .coherent_dma_mask = DMA_BIT_MASK(32),
245 },
246 .num_resources = ARRAY_SIZE(au1200_lcd_resources),
247 .resource = au1200_lcd_resources,
248};
249
250static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
251
252extern struct au1xmmc_platform_data au1xmmc_platdata[2];
253
254static struct resource au1200_mmc0_resources[] = {
255 [0] = {
256 .start = AU1100_SD0_PHYS_ADDR,
257 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
258 .flags = IORESOURCE_MEM,
259 },
260 [1] = {
261 .start = AU1200_SD_INT,
262 .end = AU1200_SD_INT,
263 .flags = IORESOURCE_IRQ,
264 },
265 [2] = {
266 .start = AU1200_DSCR_CMD0_SDMS_TX0,
267 .end = AU1200_DSCR_CMD0_SDMS_TX0,
268 .flags = IORESOURCE_DMA,
269 },
270 [3] = {
271 .start = AU1200_DSCR_CMD0_SDMS_RX0,
272 .end = AU1200_DSCR_CMD0_SDMS_RX0,
273 .flags = IORESOURCE_DMA,
274 }
275};
276
277static struct platform_device au1200_mmc0_device = {
278 .name = "au1xxx-mmc",
279 .id = 0,
280 .dev = {
281 .dma_mask = &au1xxx_mmc_dmamask,
282 .coherent_dma_mask = DMA_BIT_MASK(32),
283 .platform_data = &au1xmmc_platdata[0],
284 },
285 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
286 .resource = au1200_mmc0_resources,
287};
288
289#ifndef CONFIG_MIPS_DB1200
290static struct resource au1200_mmc1_resources[] = {
291 [0] = {
292 .start = AU1100_SD1_PHYS_ADDR,
293 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
294 .flags = IORESOURCE_MEM,
295 },
296 [1] = {
297 .start = AU1200_SD_INT,
298 .end = AU1200_SD_INT,
299 .flags = IORESOURCE_IRQ,
300 },
301 [2] = {
302 .start = AU1200_DSCR_CMD0_SDMS_TX1,
303 .end = AU1200_DSCR_CMD0_SDMS_TX1,
304 .flags = IORESOURCE_DMA,
305 },
306 [3] = {
307 .start = AU1200_DSCR_CMD0_SDMS_RX1,
308 .end = AU1200_DSCR_CMD0_SDMS_RX1,
309 .flags = IORESOURCE_DMA,
310 }
311};
312
313static struct platform_device au1200_mmc1_device = {
314 .name = "au1xxx-mmc",
315 .id = 1,
316 .dev = {
317 .dma_mask = &au1xxx_mmc_dmamask,
318 .coherent_dma_mask = DMA_BIT_MASK(32),
319 .platform_data = &au1xmmc_platdata[1],
320 },
321 .num_resources = ARRAY_SIZE(au1200_mmc1_resources),
322 .resource = au1200_mmc1_resources,
323};
324#endif /* #ifndef CONFIG_MIPS_DB1200 */
325#endif /* #ifdef CONFIG_SOC_AU1200 */
326
327/* All Alchemy demoboards with I2C have this #define in their headers */
328#ifdef SMBUS_PSC_BASE
329static struct resource pbdb_smbus_resources[] = {
330 {
331 .start = SMBUS_PSC_BASE,
332 .end = SMBUS_PSC_BASE + 0xfff,
333 .flags = IORESOURCE_MEM,
334 },
335};
336
337static struct platform_device pbdb_smbus_device = {
338 .name = "au1xpsc_smbus",
339 .id = 0, /* bus number */
340 .num_resources = ARRAY_SIZE(pbdb_smbus_resources),
341 .resource = pbdb_smbus_resources,
342};
343#endif
344
345/* Macro to help defining the Ethernet MAC resources */ 192/* Macro to help defining the Ethernet MAC resources */
346#define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */ 193#define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */
347#define MAC_RES(_base, _enable, _irq, _macdma) \ 194#define MAC_RES(_base, _enable, _irq, _macdma) \
@@ -503,33 +350,15 @@ static void __init alchemy_setup_macs(int ctype)
503 } 350 }
504} 351}
505 352
506static struct platform_device *au1xxx_platform_devices[] __initdata = {
507#ifdef CONFIG_FB_AU1100
508 &au1100_lcd_device,
509#endif
510#ifdef CONFIG_SOC_AU1200
511 &au1200_lcd_device,
512 &au1200_mmc0_device,
513#ifndef CONFIG_MIPS_DB1200
514 &au1200_mmc1_device,
515#endif
516#endif
517#ifdef SMBUS_PSC_BASE
518 &pbdb_smbus_device,
519#endif
520};
521
522static int __init au1xxx_platform_init(void) 353static int __init au1xxx_platform_init(void)
523{ 354{
524 int err, ctype = alchemy_get_cputype(); 355 int ctype = alchemy_get_cputype();
525 356
526 alchemy_setup_uarts(ctype); 357 alchemy_setup_uarts(ctype);
527 alchemy_setup_macs(ctype); 358 alchemy_setup_macs(ctype);
528 alchemy_setup_usb(ctype); 359 alchemy_setup_usb(ctype);
529 360
530 err = platform_add_devices(au1xxx_platform_devices, 361 return 0;
531 ARRAY_SIZE(au1xxx_platform_devices));
532 return err;
533} 362}
534 363
535arch_initcall(au1xxx_platform_init); 364arch_initcall(au1xxx_platform_init);
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index 1bc16f0e3651..aae08c1e876e 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -333,15 +333,77 @@ static struct led_classdev db1200_mmc_led = {
333 .brightness_set = db1200_mmcled_set, 333 .brightness_set = db1200_mmcled_set,
334}; 334};
335 335
336/* needed by arch/mips/alchemy/common/platform.c */ 336static struct au1xmmc_platform_data db1200mmc_platdata = {
337struct au1xmmc_platform_data au1xmmc_platdata[] = { 337 .cd_setup = db1200_mmc_cd_setup,
338 .set_power = db1200_mmc_set_power,
339 .card_inserted = db1200_mmc_card_inserted,
340 .card_readonly = db1200_mmc_card_readonly,
341 .led = &db1200_mmc_led,
342};
343
344static struct resource au1200_mmc0_resources[] = {
345 [0] = {
346 .start = AU1100_SD0_PHYS_ADDR,
347 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = AU1200_SD_INT,
352 .end = AU1200_SD_INT,
353 .flags = IORESOURCE_IRQ,
354 },
355 [2] = {
356 .start = AU1200_DSCR_CMD0_SDMS_TX0,
357 .end = AU1200_DSCR_CMD0_SDMS_TX0,
358 .flags = IORESOURCE_DMA,
359 },
360 [3] = {
361 .start = AU1200_DSCR_CMD0_SDMS_RX0,
362 .end = AU1200_DSCR_CMD0_SDMS_RX0,
363 .flags = IORESOURCE_DMA,
364 }
365};
366
367static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
368
369static struct platform_device db1200_mmc0_dev = {
370 .name = "au1xxx-mmc",
371 .id = 0,
372 .dev = {
373 .dma_mask = &au1xxx_mmc_dmamask,
374 .coherent_dma_mask = DMA_BIT_MASK(32),
375 .platform_data = &db1200mmc_platdata,
376 },
377 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
378 .resource = au1200_mmc0_resources,
379};
380
381/**********************************************************************/
382
383static struct resource au1200_lcd_res[] = {
338 [0] = { 384 [0] = {
339 .cd_setup = db1200_mmc_cd_setup, 385 .start = AU1200_LCD_PHYS_ADDR,
340 .set_power = db1200_mmc_set_power, 386 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
341 .card_inserted = db1200_mmc_card_inserted, 387 .flags = IORESOURCE_MEM,
342 .card_readonly = db1200_mmc_card_readonly, 388 },
343 .led = &db1200_mmc_led, 389 [1] = {
390 .start = AU1200_LCD_INT,
391 .end = AU1200_LCD_INT,
392 .flags = IORESOURCE_IRQ,
393 }
394};
395
396static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
397
398static struct platform_device au1200_lcd_dev = {
399 .name = "au1200-lcd",
400 .id = 0,
401 .dev = {
402 .dma_mask = &au1200_lcd_dmamask,
403 .coherent_dma_mask = DMA_BIT_MASK(32),
344 }, 404 },
405 .num_resources = ARRAY_SIZE(au1200_lcd_res),
406 .resource = au1200_lcd_res,
345}; 407};
346 408
347/**********************************************************************/ 409/**********************************************************************/
@@ -442,6 +504,8 @@ static struct platform_device db1200_stac_dev = {
442static struct platform_device *db1200_devs[] __initdata = { 504static struct platform_device *db1200_devs[] __initdata = {
443 NULL, /* PSC0, selected by S6.8 */ 505 NULL, /* PSC0, selected by S6.8 */
444 &db1200_ide_dev, 506 &db1200_ide_dev,
507 &db1200_mmc0_dev,
508 &au1200_lcd_dev,
445 &db1200_eth_dev, 509 &db1200_eth_dev,
446 &db1200_rtc_dev, 510 &db1200_rtc_dev,
447 &db1200_nand_dev, 511 &db1200_nand_dev,
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 2b2178f3f30b..7cd36e631f6c 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -134,9 +134,7 @@ void __init board_setup(void)
134 /* initialize board register space */ 134 /* initialize board register space */
135 bcsr_init(bcsr1, bcsr2); 135 bcsr_init(bcsr1, bcsr2);
136 136
137 /* Not valid for Au1550 */ 137#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR)
138#if defined(CONFIG_IRDA) && \
139 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
140 { 138 {
141 u32 pin_func; 139 u32 pin_func;
142 140
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
index 990367f8401d..8704865306a5 100644
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -19,6 +19,7 @@
19 */ 19 */
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/dma-mapping.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23 24
24#include <asm/mach-au1x00/au1000.h> 25#include <asm/mach-au1x00/au1000.h>
@@ -208,6 +209,34 @@ static int __init db15x0_pci_init(void)
208arch_initcall(db15x0_pci_init); 209arch_initcall(db15x0_pci_init);
209#endif 210#endif
210 211
212#ifdef CONFIG_MIPS_DB1100
213static struct resource au1100_lcd_resources[] = {
214 [0] = {
215 .start = AU1100_LCD_PHYS_ADDR,
216 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
217 .flags = IORESOURCE_MEM,
218 },
219 [1] = {
220 .start = AU1100_LCD_INT,
221 .end = AU1100_LCD_INT,
222 .flags = IORESOURCE_IRQ,
223 }
224};
225
226static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
227
228static struct platform_device au1100_lcd_device = {
229 .name = "au1100-lcd",
230 .id = 0,
231 .dev = {
232 .dma_mask = &au1100_lcd_dmamask,
233 .coherent_dma_mask = DMA_BIT_MASK(32),
234 },
235 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
236 .resource = au1100_lcd_resources,
237};
238#endif
239
211static int __init db1xxx_dev_init(void) 240static int __init db1xxx_dev_init(void)
212{ 241{
213#ifdef DB1XXX_HAS_PCMCIA 242#ifdef DB1XXX_HAS_PCMCIA
@@ -231,6 +260,9 @@ static int __init db1xxx_dev_init(void)
231 DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1, 260 DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
232 /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1); 261 /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
233#endif 262#endif
263#ifdef CONFIG_MIPS_DB1100
264 platform_device_register(&au1100_lcd_device);
265#endif
234 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); 266 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
235 return 0; 267 return 0;
236} 268}
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
index 8a4e733f0f9f..9c57c01a68c4 100644
--- a/arch/mips/alchemy/devboards/pb1100/platform.c
+++ b/arch/mips/alchemy/devboards/pb1100/platform.c
@@ -19,12 +19,40 @@
19 */ 19 */
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/dma-mapping.h>
23#include <linux/platform_device.h>
22 24
23#include <asm/mach-au1x00/au1000.h> 25#include <asm/mach-au1x00/au1000.h>
24#include <asm/mach-db1x00/bcsr.h> 26#include <asm/mach-db1x00/bcsr.h>
25 27
26#include "../platform.h" 28#include "../platform.h"
27 29
30static struct resource au1100_lcd_resources[] = {
31 [0] = {
32 .start = AU1100_LCD_PHYS_ADDR,
33 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
34 .flags = IORESOURCE_MEM,
35 },
36 [1] = {
37 .start = AU1100_LCD_INT,
38 .end = AU1100_LCD_INT,
39 .flags = IORESOURCE_IRQ,
40 }
41};
42
43static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
44
45static struct platform_device au1100_lcd_device = {
46 .name = "au1100-lcd",
47 .id = 0,
48 .dev = {
49 .dma_mask = &au1100_lcd_dmamask,
50 .coherent_dma_mask = DMA_BIT_MASK(32),
51 },
52 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
53 .resource = au1100_lcd_resources,
54};
55
28static int __init pb1100_dev_init(void) 56static int __init pb1100_dev_init(void)
29{ 57{
30 int swapped; 58 int swapped;
@@ -42,6 +70,7 @@ static int __init pb1100_dev_init(void)
42 70
43 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; 71 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
44 db1x_register_norflash(64 * 1024 * 1024, 4, swapped); 72 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
73 platform_device_register(&au1100_lcd_device);
45 74
46 return 0; 75 return 0;
47} 76}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index d7915b054be7..54f7f7b0676e 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -90,7 +90,7 @@ static int pb1200mmc1_card_inserted(void *mmc_host)
90 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; 90 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
91} 91}
92 92
93const struct au1xmmc_platform_data au1xmmc_platdata[2] = { 93static struct au1xmmc_platform_data pb1200mmc_platdata[2] = {
94 [0] = { 94 [0] = {
95 .set_power = pb1200mmc0_set_power, 95 .set_power = pb1200mmc0_set_power,
96 .card_inserted = pb1200mmc0_card_inserted, 96 .card_inserted = pb1200mmc0_card_inserted,
@@ -107,6 +107,79 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
107 }, 107 },
108}; 108};
109 109
110static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
111
112static struct resource au1200_mmc0_res[] = {
113 [0] = {
114 .start = AU1100_SD0_PHYS_ADDR,
115 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
116 .flags = IORESOURCE_MEM,
117 },
118 [1] = {
119 .start = AU1200_SD_INT,
120 .end = AU1200_SD_INT,
121 .flags = IORESOURCE_IRQ,
122 },
123 [2] = {
124 .start = AU1200_DSCR_CMD0_SDMS_TX0,
125 .end = AU1200_DSCR_CMD0_SDMS_TX0,
126 .flags = IORESOURCE_DMA,
127 },
128 [3] = {
129 .start = AU1200_DSCR_CMD0_SDMS_RX0,
130 .end = AU1200_DSCR_CMD0_SDMS_RX0,
131 .flags = IORESOURCE_DMA,
132 }
133};
134
135static struct platform_device pb1200_mmc0_dev = {
136 .name = "au1xxx-mmc",
137 .id = 0,
138 .dev = {
139 .dma_mask = &au1xxx_mmc_dmamask,
140 .coherent_dma_mask = DMA_BIT_MASK(32),
141 .platform_data = &pb1200mmc_platdata[0],
142 },
143 .num_resources = ARRAY_SIZE(au1200_mmc0_res),
144 .resource = au1200_mmc0_res,
145};
146
147static struct resource au1200_mmc1_res[] = {
148 [0] = {
149 .start = AU1100_SD1_PHYS_ADDR,
150 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
151 .flags = IORESOURCE_MEM,
152 },
153 [1] = {
154 .start = AU1200_SD_INT,
155 .end = AU1200_SD_INT,
156 .flags = IORESOURCE_IRQ,
157 },
158 [2] = {
159 .start = AU1200_DSCR_CMD0_SDMS_TX1,
160 .end = AU1200_DSCR_CMD0_SDMS_TX1,
161 .flags = IORESOURCE_DMA,
162 },
163 [3] = {
164 .start = AU1200_DSCR_CMD0_SDMS_RX1,
165 .end = AU1200_DSCR_CMD0_SDMS_RX1,
166 .flags = IORESOURCE_DMA,
167 }
168};
169
170static struct platform_device pb1200_mmc1_dev = {
171 .name = "au1xxx-mmc",
172 .id = 1,
173 .dev = {
174 .dma_mask = &au1xxx_mmc_dmamask,
175 .coherent_dma_mask = DMA_BIT_MASK(32),
176 .platform_data = &pb1200mmc_platdata[1],
177 },
178 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
179 .resource = au1200_mmc1_res,
180};
181
182
110static struct resource ide_resources[] = { 183static struct resource ide_resources[] = {
111 [0] = { 184 [0] = {
112 .start = IDE_PHYS_ADDR, 185 .start = IDE_PHYS_ADDR,
@@ -168,9 +241,69 @@ static struct platform_device smc91c111_device = {
168 .resource = smc91c111_resources 241 .resource = smc91c111_resources
169}; 242};
170 243
244static struct resource au1200_psc0_res[] = {
245 [0] = {
246 .start = AU1550_PSC0_PHYS_ADDR,
247 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
248 .flags = IORESOURCE_MEM,
249 },
250 [1] = {
251 .start = AU1200_PSC0_INT,
252 .end = AU1200_PSC0_INT,
253 .flags = IORESOURCE_IRQ,
254 },
255 [2] = {
256 .start = AU1200_DSCR_CMD0_PSC0_TX,
257 .end = AU1200_DSCR_CMD0_PSC0_TX,
258 .flags = IORESOURCE_DMA,
259 },
260 [3] = {
261 .start = AU1200_DSCR_CMD0_PSC0_RX,
262 .end = AU1200_DSCR_CMD0_PSC0_RX,
263 .flags = IORESOURCE_DMA,
264 },
265};
266
267static struct platform_device pb1200_i2c_dev = {
268 .name = "au1xpsc_smbus",
269 .id = 0, /* bus number */
270 .num_resources = ARRAY_SIZE(au1200_psc0_res),
271 .resource = au1200_psc0_res,
272};
273
274static struct resource au1200_lcd_res[] = {
275 [0] = {
276 .start = AU1200_LCD_PHYS_ADDR,
277 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
278 .flags = IORESOURCE_MEM,
279 },
280 [1] = {
281 .start = AU1200_LCD_INT,
282 .end = AU1200_LCD_INT,
283 .flags = IORESOURCE_IRQ,
284 }
285};
286
287static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
288
289static struct platform_device au1200_lcd_dev = {
290 .name = "au1200-lcd",
291 .id = 0,
292 .dev = {
293 .dma_mask = &au1200_lcd_dmamask,
294 .coherent_dma_mask = DMA_BIT_MASK(32),
295 },
296 .num_resources = ARRAY_SIZE(au1200_lcd_res),
297 .resource = au1200_lcd_res,
298};
299
171static struct platform_device *board_platform_devices[] __initdata = { 300static struct platform_device *board_platform_devices[] __initdata = {
172 &ide_device, 301 &ide_device,
173 &smc91c111_device 302 &smc91c111_device,
303 &pb1200_i2c_dev,
304 &pb1200_mmc0_dev,
305 &pb1200_mmc1_dev,
306 &au1200_lcd_dev,
174}; 307};
175 308
176static int __init board_register_devices(void) 309static int __init board_register_devices(void)
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
index 9f0b5a0b4795..1e52a01bac00 100644
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -18,6 +18,7 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/dma-mapping.h>
21#include <linux/init.h> 22#include <linux/init.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23#include <asm/mach-au1x00/au1000.h> 24#include <asm/mach-au1x00/au1000.h>
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
index 0c5711fa0734..a4604b8a349e 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -18,9 +18,11 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/dma-mapping.h>
21#include <linux/init.h> 22#include <linux/init.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23#include <asm/mach-au1x00/au1000.h> 24#include <asm/mach-au1x00/au1000.h>
25#include <asm/mach-au1x00/au1xxx_dbdma.h>
24#include <asm/mach-pb1x00/pb1550.h> 26#include <asm/mach-pb1x00/pb1550.h>
25#include <asm/mach-db1x00/bcsr.h> 27#include <asm/mach-db1x00/bcsr.h>
26 28
@@ -69,6 +71,36 @@ static struct platform_device pb1550_pci_host = {
69 .resource = alchemy_pci_host_res, 71 .resource = alchemy_pci_host_res,
70}; 72};
71 73
74static struct resource au1550_psc2_res[] = {
75 [0] = {
76 .start = AU1550_PSC2_PHYS_ADDR,
77 .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
78 .flags = IORESOURCE_MEM,
79 },
80 [1] = {
81 .start = AU1550_PSC2_INT,
82 .end = AU1550_PSC2_INT,
83 .flags = IORESOURCE_IRQ,
84 },
85 [2] = {
86 .start = AU1550_DSCR_CMD0_PSC2_TX,
87 .end = AU1550_DSCR_CMD0_PSC2_TX,
88 .flags = IORESOURCE_DMA,
89 },
90 [3] = {
91 .start = AU1550_DSCR_CMD0_PSC2_RX,
92 .end = AU1550_DSCR_CMD0_PSC2_RX,
93 .flags = IORESOURCE_DMA,
94 },
95};
96
97static struct platform_device pb1550_i2c_dev = {
98 .name = "au1xpsc_smbus",
99 .id = 0, /* bus number */
100 .num_resources = ARRAY_SIZE(au1550_psc2_res),
101 .resource = au1550_psc2_res,
102};
103
72static int __init pb1550_dev_init(void) 104static int __init pb1550_dev_init(void)
73{ 105{
74 int swapped; 106 int swapped;
@@ -101,6 +133,7 @@ static int __init pb1550_dev_init(void)
101 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; 133 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
102 db1x_register_norflash(128 * 1024 * 1024, 4, swapped); 134 db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
103 platform_device_register(&pb1550_pci_host); 135 platform_device_register(&pb1550_pci_host);
136 platform_device_register(&pb1550_i2c_dev);
104 137
105 return 0; 138 return 0;
106} 139}
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 49a227d681e3..de24ec57dd2f 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -592,113 +592,6 @@ enum soc_au1200_ints {
592#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 592#endif /* !defined (_LANGUAGE_ASSEMBLY) */
593 593
594/* 594/*
595 * SDRAM register offsets
596 */
597#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
598 defined(CONFIG_SOC_AU1100)
599#define MEM_SDMODE0 0x0000
600#define MEM_SDMODE1 0x0004
601#define MEM_SDMODE2 0x0008
602#define MEM_SDADDR0 0x000C
603#define MEM_SDADDR1 0x0010
604#define MEM_SDADDR2 0x0014
605#define MEM_SDREFCFG 0x0018
606#define MEM_SDPRECMD 0x001C
607#define MEM_SDAUTOREF 0x0020
608#define MEM_SDWRMD0 0x0024
609#define MEM_SDWRMD1 0x0028
610#define MEM_SDWRMD2 0x002C
611#define MEM_SDSLEEP 0x0030
612#define MEM_SDSMCKE 0x0034
613
614/*
615 * MEM_SDMODE register content definitions
616 */
617#define MEM_SDMODE_F (1 << 22)
618#define MEM_SDMODE_SR (1 << 21)
619#define MEM_SDMODE_BS (1 << 20)
620#define MEM_SDMODE_RS (3 << 18)
621#define MEM_SDMODE_CS (7 << 15)
622#define MEM_SDMODE_TRAS (15 << 11)
623#define MEM_SDMODE_TMRD (3 << 9)
624#define MEM_SDMODE_TWR (3 << 7)
625#define MEM_SDMODE_TRP (3 << 5)
626#define MEM_SDMODE_TRCD (3 << 3)
627#define MEM_SDMODE_TCL (7 << 0)
628
629#define MEM_SDMODE_BS_2Bank (0 << 20)
630#define MEM_SDMODE_BS_4Bank (1 << 20)
631#define MEM_SDMODE_RS_11Row (0 << 18)
632#define MEM_SDMODE_RS_12Row (1 << 18)
633#define MEM_SDMODE_RS_13Row (2 << 18)
634#define MEM_SDMODE_RS_N(N) ((N) << 18)
635#define MEM_SDMODE_CS_7Col (0 << 15)
636#define MEM_SDMODE_CS_8Col (1 << 15)
637#define MEM_SDMODE_CS_9Col (2 << 15)
638#define MEM_SDMODE_CS_10Col (3 << 15)
639#define MEM_SDMODE_CS_11Col (4 << 15)
640#define MEM_SDMODE_CS_N(N) ((N) << 15)
641#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
642#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
643#define MEM_SDMODE_TWR_N(N) ((N) << 7)
644#define MEM_SDMODE_TRP_N(N) ((N) << 5)
645#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
646#define MEM_SDMODE_TCL_N(N) ((N) << 0)
647
648/*
649 * MEM_SDADDR register contents definitions
650 */
651#define MEM_SDADDR_E (1 << 20)
652#define MEM_SDADDR_CSBA (0x03FF << 10)
653#define MEM_SDADDR_CSMASK (0x03FF << 0)
654#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
655#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
656
657/*
658 * MEM_SDREFCFG register content definitions
659 */
660#define MEM_SDREFCFG_TRC (15 << 28)
661#define MEM_SDREFCFG_TRPM (3 << 26)
662#define MEM_SDREFCFG_E (1 << 25)
663#define MEM_SDREFCFG_RE (0x1ffffff << 0)
664#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
665#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
666#define MEM_SDREFCFG_REF_N(N) (N)
667#endif
668
669/***********************************************************************/
670
671/*
672 * Au1550 SDRAM Register Offsets
673 */
674
675/***********************************************************************/
676
677#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
678#define MEM_SDMODE0 0x0800
679#define MEM_SDMODE1 0x0808
680#define MEM_SDMODE2 0x0810
681#define MEM_SDADDR0 0x0820
682#define MEM_SDADDR1 0x0828
683#define MEM_SDADDR2 0x0830
684#define MEM_SDCONFIGA 0x0840
685#define MEM_SDCONFIGB 0x0848
686#define MEM_SDSTAT 0x0850
687#define MEM_SDERRADDR 0x0858
688#define MEM_SDSTRIDE0 0x0860
689#define MEM_SDSTRIDE1 0x0868
690#define MEM_SDSTRIDE2 0x0870
691#define MEM_SDWRMD0 0x0880
692#define MEM_SDWRMD1 0x0888
693#define MEM_SDWRMD2 0x0890
694#define MEM_SDPRECMD 0x08C0
695#define MEM_SDAUTOREF 0x08C8
696#define MEM_SDSREF 0x08D0
697#define MEM_SDSLEEP MEM_SDSREF
698
699#endif
700
701/*
702 * Physical base addresses for integrated peripherals 595 * Physical base addresses for integrated peripherals
703 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 596 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
704 */ 597 */
@@ -761,6 +654,92 @@ enum soc_au1200_ints {
761#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ 654#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */
762 655
763 656
657/* Au1000 SDRAM memory controller register offsets */
658#define AU1000_MEM_SDMODE0 0x0000
659#define AU1000_MEM_SDMODE1 0x0004
660#define AU1000_MEM_SDMODE2 0x0008
661#define AU1000_MEM_SDADDR0 0x000C
662#define AU1000_MEM_SDADDR1 0x0010
663#define AU1000_MEM_SDADDR2 0x0014
664#define AU1000_MEM_SDREFCFG 0x0018
665#define AU1000_MEM_SDPRECMD 0x001C
666#define AU1000_MEM_SDAUTOREF 0x0020
667#define AU1000_MEM_SDWRMD0 0x0024
668#define AU1000_MEM_SDWRMD1 0x0028
669#define AU1000_MEM_SDWRMD2 0x002C
670#define AU1000_MEM_SDSLEEP 0x0030
671#define AU1000_MEM_SDSMCKE 0x0034
672
673/* MEM_SDMODE register content definitions */
674#define MEM_SDMODE_F (1 << 22)
675#define MEM_SDMODE_SR (1 << 21)
676#define MEM_SDMODE_BS (1 << 20)
677#define MEM_SDMODE_RS (3 << 18)
678#define MEM_SDMODE_CS (7 << 15)
679#define MEM_SDMODE_TRAS (15 << 11)
680#define MEM_SDMODE_TMRD (3 << 9)
681#define MEM_SDMODE_TWR (3 << 7)
682#define MEM_SDMODE_TRP (3 << 5)
683#define MEM_SDMODE_TRCD (3 << 3)
684#define MEM_SDMODE_TCL (7 << 0)
685
686#define MEM_SDMODE_BS_2Bank (0 << 20)
687#define MEM_SDMODE_BS_4Bank (1 << 20)
688#define MEM_SDMODE_RS_11Row (0 << 18)
689#define MEM_SDMODE_RS_12Row (1 << 18)
690#define MEM_SDMODE_RS_13Row (2 << 18)
691#define MEM_SDMODE_RS_N(N) ((N) << 18)
692#define MEM_SDMODE_CS_7Col (0 << 15)
693#define MEM_SDMODE_CS_8Col (1 << 15)
694#define MEM_SDMODE_CS_9Col (2 << 15)
695#define MEM_SDMODE_CS_10Col (3 << 15)
696#define MEM_SDMODE_CS_11Col (4 << 15)
697#define MEM_SDMODE_CS_N(N) ((N) << 15)
698#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
699#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
700#define MEM_SDMODE_TWR_N(N) ((N) << 7)
701#define MEM_SDMODE_TRP_N(N) ((N) << 5)
702#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
703#define MEM_SDMODE_TCL_N(N) ((N) << 0)
704
705/* MEM_SDADDR register contents definitions */
706#define MEM_SDADDR_E (1 << 20)
707#define MEM_SDADDR_CSBA (0x03FF << 10)
708#define MEM_SDADDR_CSMASK (0x03FF << 0)
709#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
710#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
711
712/* MEM_SDREFCFG register content definitions */
713#define MEM_SDREFCFG_TRC (15 << 28)
714#define MEM_SDREFCFG_TRPM (3 << 26)
715#define MEM_SDREFCFG_E (1 << 25)
716#define MEM_SDREFCFG_RE (0x1ffffff << 0)
717#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
718#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
719#define MEM_SDREFCFG_REF_N(N) (N)
720
721/* Au1550 SDRAM Register Offsets */
722#define AU1550_MEM_SDMODE0 0x0800
723#define AU1550_MEM_SDMODE1 0x0808
724#define AU1550_MEM_SDMODE2 0x0810
725#define AU1550_MEM_SDADDR0 0x0820
726#define AU1550_MEM_SDADDR1 0x0828
727#define AU1550_MEM_SDADDR2 0x0830
728#define AU1550_MEM_SDCONFIGA 0x0840
729#define AU1550_MEM_SDCONFIGB 0x0848
730#define AU1550_MEM_SDSTAT 0x0850
731#define AU1550_MEM_SDERRADDR 0x0858
732#define AU1550_MEM_SDSTRIDE0 0x0860
733#define AU1550_MEM_SDSTRIDE1 0x0868
734#define AU1550_MEM_SDSTRIDE2 0x0870
735#define AU1550_MEM_SDWRMD0 0x0880
736#define AU1550_MEM_SDWRMD1 0x0888
737#define AU1550_MEM_SDWRMD2 0x0890
738#define AU1550_MEM_SDPRECMD 0x08C0
739#define AU1550_MEM_SDAUTOREF 0x08C8
740#define AU1550_MEM_SDSREF 0x08D0
741#define AU1550_MEM_SDSLEEP MEM_SDSREF
742
764/* Static Bus Controller */ 743/* Static Bus Controller */
765#define MEM_STCFG0 0xB4001000 744#define MEM_STCFG0 0xB4001000
766#define MEM_STTIME0 0xB4001004 745#define MEM_STTIME0 0xB4001004
@@ -778,14 +757,12 @@ enum soc_au1200_ints {
778#define MEM_STTIME3 0xB4001034 757#define MEM_STTIME3 0xB4001034
779#define MEM_STADDR3 0xB4001038 758#define MEM_STADDR3 0xB4001038
780 759
781#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
782#define MEM_STNDCTL 0xB4001100 760#define MEM_STNDCTL 0xB4001100
783#define MEM_STSTAT 0xB4001104 761#define MEM_STSTAT 0xB4001104
784 762
785#define MEM_STNAND_CMD 0x0 763#define MEM_STNAND_CMD 0x0
786#define MEM_STNAND_ADDR 0x4 764#define MEM_STNAND_ADDR 0x4
787#define MEM_STNAND_DATA 0x20 765#define MEM_STNAND_DATA 0x20
788#endif
789 766
790 767
791/* Programmable Counters 0 and 1 */ 768/* Programmable Counters 0 and 1 */
@@ -1172,7 +1149,6 @@ enum soc_au1200_ints {
1172# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1149# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1173 1150
1174/* Au1200 only */ 1151/* Au1200 only */
1175#ifdef CONFIG_SOC_AU1200
1176#define SYS_PINFUNC_DMA (1 << 31) 1152#define SYS_PINFUNC_DMA (1 << 31)
1177#define SYS_PINFUNC_S0A (1 << 30) 1153#define SYS_PINFUNC_S0A (1 << 30)
1178#define SYS_PINFUNC_S1A (1 << 29) 1154#define SYS_PINFUNC_S1A (1 << 29)
@@ -1200,7 +1176,6 @@ enum soc_au1200_ints {
1200#define SYS_PINFUNC_P0B (1 << 4) 1176#define SYS_PINFUNC_P0B (1 << 4)
1201#define SYS_PINFUNC_U0T (1 << 3) 1177#define SYS_PINFUNC_U0T (1 << 3)
1202#define SYS_PINFUNC_S1B (1 << 2) 1178#define SYS_PINFUNC_S1B (1 << 2)
1203#endif
1204 1179
1205/* Power Management */ 1180/* Power Management */
1206#define SYS_SCRATCH0 0xB1900018 1181#define SYS_SCRATCH0 0xB1900018
@@ -1256,12 +1231,12 @@ enum soc_au1200_ints {
1256# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) 1231# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1257# define SYS_CS_DI2 (1 << 16) 1232# define SYS_CS_DI2 (1 << 16)
1258# define SYS_CS_CI2 (1 << 15) 1233# define SYS_CS_CI2 (1 << 15)
1259#ifdef CONFIG_SOC_AU1100 1234
1260# define SYS_CS_ML_BIT 7 1235# define SYS_CS_ML_BIT 7
1261# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) 1236# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1262# define SYS_CS_DL (1 << 6) 1237# define SYS_CS_DL (1 << 6)
1263# define SYS_CS_CL (1 << 5) 1238# define SYS_CS_CL (1 << 5)
1264#else 1239
1265# define SYS_CS_MUH_BIT 12 1240# define SYS_CS_MUH_BIT 12
1266# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) 1241# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1267# define SYS_CS_DUH (1 << 11) 1242# define SYS_CS_DUH (1 << 11)
@@ -1270,7 +1245,7 @@ enum soc_au1200_ints {
1270# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) 1245# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1271# define SYS_CS_DUD (1 << 6) 1246# define SYS_CS_DUD (1 << 6)
1272# define SYS_CS_CUD (1 << 5) 1247# define SYS_CS_CUD (1 << 5)
1273#endif 1248
1274# define SYS_CS_MIR_BIT 2 1249# define SYS_CS_MIR_BIT 2
1275# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) 1250# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1276# define SYS_CS_DIR (1 << 1) 1251# define SYS_CS_DIR (1 << 1)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 22:14:44 -0500