aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/mti-sead3/sead3-i2c-drv.c
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2013-01-22 06:59:30 -0500
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 04:00:22 -0500
commit7034228792cc561e79ff8600f02884bd4c80e287 (patch)
tree89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/mti-sead3/sead3-i2c-drv.c
parent405ab01c70e18058d9c01a1256769a61fc65413e (diff)
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mti-sead3/sead3-i2c-drv.c')
-rw-r--r--arch/mips/mti-sead3/sead3-i2c-drv.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/mips/mti-sead3/sead3-i2c-drv.c b/arch/mips/mti-sead3/sead3-i2c-drv.c
index 7aa2225e75b9..1f787a6a7878 100644
--- a/arch/mips/mti-sead3/sead3-i2c-drv.c
+++ b/arch/mips/mti-sead3/sead3-i2c-drv.c
@@ -13,32 +13,32 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14 14
15#define PIC32_I2CxCON 0x0000 15#define PIC32_I2CxCON 0x0000
16#define PIC32_I2CCON_ON (1<<15) 16#define PIC32_I2CCON_ON (1<<15)
17#define PIC32_I2CCON_ACKDT (1<<5) 17#define PIC32_I2CCON_ACKDT (1<<5)
18#define PIC32_I2CCON_ACKEN (1<<4) 18#define PIC32_I2CCON_ACKEN (1<<4)
19#define PIC32_I2CCON_RCEN (1<<3) 19#define PIC32_I2CCON_RCEN (1<<3)
20#define PIC32_I2CCON_PEN (1<<2) 20#define PIC32_I2CCON_PEN (1<<2)
21#define PIC32_I2CCON_RSEN (1<<1) 21#define PIC32_I2CCON_RSEN (1<<1)
22#define PIC32_I2CCON_SEN (1<<0) 22#define PIC32_I2CCON_SEN (1<<0)
23#define PIC32_I2CxCONCLR 0x0004 23#define PIC32_I2CxCONCLR 0x0004
24#define PIC32_I2CxCONSET 0x0008 24#define PIC32_I2CxCONSET 0x0008
25#define PIC32_I2CxSTAT 0x0010 25#define PIC32_I2CxSTAT 0x0010
26#define PIC32_I2CxSTATCLR 0x0014 26#define PIC32_I2CxSTATCLR 0x0014
27#define PIC32_I2CSTAT_ACKSTAT (1<<15) 27#define PIC32_I2CSTAT_ACKSTAT (1<<15)
28#define PIC32_I2CSTAT_TRSTAT (1<<14) 28#define PIC32_I2CSTAT_TRSTAT (1<<14)
29#define PIC32_I2CSTAT_BCL (1<<10) 29#define PIC32_I2CSTAT_BCL (1<<10)
30#define PIC32_I2CSTAT_IWCOL (1<<7) 30#define PIC32_I2CSTAT_IWCOL (1<<7)
31#define PIC32_I2CSTAT_I2COV (1<<6) 31#define PIC32_I2CSTAT_I2COV (1<<6)
32#define PIC32_I2CxBRG 0x0040 32#define PIC32_I2CxBRG 0x0040
33#define PIC32_I2CxTRN 0x0050 33#define PIC32_I2CxTRN 0x0050
34#define PIC32_I2CxRCV 0x0060 34#define PIC32_I2CxRCV 0x0060
35 35
36static DEFINE_SPINLOCK(pic32_bus_lock); 36static DEFINE_SPINLOCK(pic32_bus_lock);
37 37
38static void __iomem *bus_xfer = (void __iomem *)0xbf000600; 38static void __iomem *bus_xfer = (void __iomem *)0xbf000600;
39static void __iomem *bus_status = (void __iomem *)0xbf000060; 39static void __iomem *bus_status = (void __iomem *)0xbf000060;
40 40
41#define DELAY() udelay(100) 41#define DELAY() udelay(100)
42 42
43static inline unsigned int ioready(void) 43static inline unsigned int ioready(void)
44{ 44{