MIPS: microMIPS: Add support for exception handling.

All exceptions must be taken in microMIPS mode, never in classic
MIPS mode or the kernel falls apart. A few NOP instructions are
used to maintain the correct alignment of microMIPS versions of
the exception vectors.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>

2 files changed, 7 insertions, 6 deletions

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index f64e17fa3e96..87e6207b05e4 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -596,6 +596,7 @@
 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
+#define MIPS_CONF3_ISA_OE       (_ULCAST_(3) << 16)
 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 
 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index c99384018161..a89d1b10d027 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -139,7 +139,7 @@
 1:              move    ra, k0
                 li      k0, 3
                 mtc0    k0, $22
-#endif /* CONFIG_CPU_LOONGSON2F */
+#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */
 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
                 lui     k1, %hi(kernelsp)
 #else
@@ -189,6 +189,7 @@
                 LONG_S  $0, PT_R0(sp)
                 mfc0    v1, CP0_STATUS
                 LONG_S  $2, PT_R2(sp)
+                LONG_S  v1, PT_STATUS(sp)
 #ifdef CONFIG_MIPS_MT_SMTC
                 /*
                  * Ideally, these instructions would be shuffled in
@@ -200,21 +201,20 @@
                 LONG_S  k0, PT_TCSTATUS(sp)
 #endif /* CONFIG_MIPS_MT_SMTC */
                 LONG_S  $4, PT_R4(sp)
-                LONG_S  $5, PT_R5(sp)
-                LONG_S  v1, PT_STATUS(sp)
                 mfc0    v1, CP0_CAUSE
-                LONG_S  $6, PT_R6(sp)
-                LONG_S  $7, PT_R7(sp)
+                LONG_S  $5, PT_R5(sp)
                 LONG_S  v1, PT_CAUSE(sp)
+                LONG_S  $6, PT_R6(sp)
                 MFC0    v1, CP0_EPC
+                LONG_S  $7, PT_R7(sp)
 #ifdef CONFIG_64BIT
                 LONG_S  $8, PT_R8(sp)
                 LONG_S  $9, PT_R9(sp)
 #endif
+                LONG_S  v1, PT_EPC(sp)
                 LONG_S  $25, PT_R25(sp)
                 LONG_S  $28, PT_R28(sp)
                 LONG_S  $31, PT_R31(sp)
-                LONG_S  v1, PT_EPC(sp)
                 ori     $28, sp, _THREAD_MASK
                 xori    $28, _THREAD_MASK
 #ifdef CONFIG_CPU_CAVIUM_OCTEON