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authorRalf Baechle <ralf@linux-mips.org>2013-05-09 11:56:40 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-05-09 11:56:40 -0400
commit5e0e61dd2c89c673f89fb57dcd3cc746dc0c1706 (patch)
tree5ebe6156cbc8620625b736a5c9f4d3f47e6d9ebc /arch/mips/include/asm/mmu_context.h
parent9b3539e0e545e4c2f338acfc1ce52033a6f5e7f7 (diff)
parent50c8308538dc9671490d6cb65259ef0ed79f5d13 (diff)
Merge branch 'next/kvm' into mips-for-linux-next
Diffstat (limited to 'arch/mips/include/asm/mmu_context.h')
-rw-r--r--arch/mips/include/asm/mmu_context.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 952701c3ad2e..820116067c10 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -111,15 +111,21 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
111static inline void 111static inline void
112get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 112get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
113{ 113{
114 extern void kvm_local_flush_tlb_all(void);
114 unsigned long asid = asid_cache(cpu); 115 unsigned long asid = asid_cache(cpu);
115 116
116 if (! ((asid += ASID_INC) & ASID_MASK) ) { 117 if (! ((asid += ASID_INC) & ASID_MASK) ) {
117 if (cpu_has_vtag_icache) 118 if (cpu_has_vtag_icache)
118 flush_icache_all(); 119 flush_icache_all();
120#ifdef CONFIG_VIRTUALIZATION
121 kvm_local_flush_tlb_all(); /* start new asid cycle */
122#else
119 local_flush_tlb_all(); /* start new asid cycle */ 123 local_flush_tlb_all(); /* start new asid cycle */
124#endif
120 if (!asid) /* fix version if needed */ 125 if (!asid) /* fix version if needed */
121 asid = ASID_FIRST_VERSION; 126 asid = ASID_FIRST_VERSION;
122 } 127 }
128
123 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 129 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
124} 130}
125 131