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authorMichal Simek <monstr@monstr.eu>2010-04-23 05:38:43 -0400
committerMichal Simek <monstr@monstr.eu>2010-05-06 05:21:59 -0400
commitc17e1a1cedb723d48d4822cae1af1c010b608b5c (patch)
treef20de9ba7d16eef7910bcd2d95ad628761685305 /arch/microblaze
parentf1525765fb9c432f5dc5d0d18102fbe9980a14ae (diff)
microblaze: Fix typo fault in cache code
Copy & paste error. Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze')
-rw-r--r--arch/microblaze/kernel/cpu/cache.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
index f04d8a86dead..19dae71dbaaf 100644
--- a/arch/microblaze/kernel/cpu/cache.c
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -393,7 +393,7 @@ static void __invalidate_dcache_range_wb(unsigned long start,
393#ifdef ASM_LOOP 393#ifdef ASM_LOOP
394 CACHE_RANGE_LOOP_2(start, end, cpuinfo.dcache_line_length, wdc.clear); 394 CACHE_RANGE_LOOP_2(start, end, cpuinfo.dcache_line_length, wdc.clear);
395#else 395#else
396 for (i = start; i < end; i += cpuinfo.icache_line_length) 396 for (i = start; i < end; i += cpuinfo.dcache_line_length)
397 __asm__ __volatile__ ("wdc.clear %0, r0;" \ 397 __asm__ __volatile__ ("wdc.clear %0, r0;" \
398 : : "r" (i)); 398 : : "r" (i));
399#endif 399#endif
@@ -413,7 +413,7 @@ static void __invalidate_dcache_range_nomsr_wt(unsigned long start,
413#ifdef ASM_LOOP 413#ifdef ASM_LOOP
414 CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc); 414 CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);
415#else 415#else
416 for (i = start; i < end; i += cpuinfo.icache_line_length) 416 for (i = start; i < end; i += cpuinfo.dcache_line_length)
417 __asm__ __volatile__ ("wdc %0, r0;" \ 417 __asm__ __volatile__ ("wdc %0, r0;" \
418 : : "r" (i)); 418 : : "r" (i));
419#endif 419#endif
@@ -437,7 +437,7 @@ static void __invalidate_dcache_range_msr_irq_wt(unsigned long start,
437#ifdef ASM_LOOP 437#ifdef ASM_LOOP
438 CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc); 438 CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);
439#else 439#else
440 for (i = start; i < end; i += cpuinfo.icache_line_length) 440 for (i = start; i < end; i += cpuinfo.dcache_line_length)
441 __asm__ __volatile__ ("wdc %0, r0;" \ 441 __asm__ __volatile__ ("wdc %0, r0;" \
442 : : "r" (i)); 442 : : "r" (i));
443#endif 443#endif
@@ -465,7 +465,7 @@ static void __invalidate_dcache_range_nomsr_irq(unsigned long start,
465#ifdef ASM_LOOP 465#ifdef ASM_LOOP
466 CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc); 466 CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);
467#else 467#else
468 for (i = start; i < end; i += cpuinfo.icache_line_length) 468 for (i = start; i < end; i += cpuinfo.dcache_line_length)
469 __asm__ __volatile__ ("wdc %0, r0;" \ 469 __asm__ __volatile__ ("wdc %0, r0;" \
470 : : "r" (i)); 470 : : "r" (i));
471#endif 471#endif
@@ -504,7 +504,7 @@ static void __flush_dcache_range_wb(unsigned long start, unsigned long end)
504#ifdef ASM_LOOP 504#ifdef ASM_LOOP
505 CACHE_RANGE_LOOP_2(start, end, cpuinfo.dcache_line_length, wdc.flush); 505 CACHE_RANGE_LOOP_2(start, end, cpuinfo.dcache_line_length, wdc.flush);
506#else 506#else
507 for (i = start; i < end; i += cpuinfo.icache_line_length) 507 for (i = start; i < end; i += cpuinfo.dcache_line_length)
508 __asm__ __volatile__ ("wdc.flush %0, r0;" \ 508 __asm__ __volatile__ ("wdc.flush %0, r0;" \
509 : : "r" (i)); 509 : : "r" (i));
510#endif 510#endif