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authorGreg Ungerer <gerg@uclinux.org>2012-09-17 01:04:42 -0400
committerGreg Ungerer <gerg@uclinux.org>2012-09-27 09:33:58 -0400
commit23bcdacd88a0cad2a7d502b5dd35ce52d4be74d9 (patch)
tree55c593e2bf1ee4185193e8ca9bfd274a8acda6bf /arch/m68k
parenta91f741589f010e1dfa6ec6fe7afbad0ef47d937 (diff)
m68knommu: remove a lot of unsed definitions for 532x ColdFire
There are a lot of unused and uneccessary definitions in the header to support the ColdFire 532x CPU family. Remove the junk. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/include/asm/m532xsim.h1033
1 files changed, 1 insertions, 1032 deletions
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 5ca7b298c6eb..38333703a563 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -152,42 +152,6 @@
152#define MCFPM_PPMHR1 0xfc040038 152#define MCFPM_PPMHR1 0xfc040038
153#define MCFPM_LPCR 0xec090007 153#define MCFPM_LPCR 0xec090007
154 154
155/*********************************************************************
156 *
157 * Inter-IC (I2C) Module
158 *
159 *********************************************************************/
160
161/* Read/Write access macros for general use */
162#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
163#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
164#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
165#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
166#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
167
168/* Bit level definitions and macros */
169#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
170
171#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
172
173#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable
174#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable
175#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode
176#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode
177#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
178#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start
179
180#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit
181#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
182#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy
183#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost
184#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write
185#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt
186#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge
187
188#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
189
190
191/* 155/*
192 * The M5329EVB board needs a help getting its devices initialized 156 * The M5329EVB board needs a help getting its devices initialized
193 * at kernel start time if dBUG doesn't set it up (for example 157 * at kernel start time if dBUG doesn't set it up (for example
@@ -287,78 +251,6 @@
287 251
288/********************************************************************* 252/*********************************************************************
289 * 253 *
290 * DMA Timers (DTIM)
291 *
292 *********************************************************************/
293
294/* Register read/write macros */
295#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000)
296#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002)
297#define MCF_DTIM0_DTER MCF_REG08(0xFC070003)
298#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004)
299#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008)
300#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C)
301#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000)
302#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002)
303#define MCF_DTIM1_DTER MCF_REG08(0xFC074003)
304#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004)
305#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008)
306#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C)
307#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000)
308#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002)
309#define MCF_DTIM2_DTER MCF_REG08(0xFC078003)
310#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004)
311#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008)
312#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C)
313#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000)
314#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002)
315#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003)
316#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004)
317#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008)
318#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C)
319#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000))
320#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000))
321#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000))
322#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000))
323#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000))
324#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000))
325
326/* Bit definitions and macros for MCF_DTIM_DTMR */
327#define MCF_DTIM_DTMR_RST (0x0001)
328#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
329#define MCF_DTIM_DTMR_FRR (0x0008)
330#define MCF_DTIM_DTMR_ORRI (0x0010)
331#define MCF_DTIM_DTMR_OM (0x0020)
332#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6)
333#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8)
334#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
335#define MCF_DTIM_DTMR_CE_FALL (0x0080)
336#define MCF_DTIM_DTMR_CE_RISE (0x0040)
337#define MCF_DTIM_DTMR_CE_NONE (0x0000)
338#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
339#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
340#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
341#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
342
343/* Bit definitions and macros for MCF_DTIM_DTXMR */
344#define MCF_DTIM_DTXMR_MODE16 (0x01)
345#define MCF_DTIM_DTXMR_DMAEN (0x80)
346
347/* Bit definitions and macros for MCF_DTIM_DTER */
348#define MCF_DTIM_DTER_CAP (0x01)
349#define MCF_DTIM_DTER_REF (0x02)
350
351/* Bit definitions and macros for MCF_DTIM_DTRR */
352#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
353
354/* Bit definitions and macros for MCF_DTIM_DTCR */
355#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
356
357/* Bit definitions and macros for MCF_DTIM_DTCN */
358#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
359
360/*********************************************************************
361 *
362 * FlexBus Chip Selects (FBCS) 254 * FlexBus Chip Selects (FBCS)
363 * 255 *
364 *********************************************************************/ 256 *********************************************************************/
@@ -1215,709 +1107,6 @@
1215#define MCFGPIO_IRQ_MAX 8 1107#define MCFGPIO_IRQ_MAX 8
1216#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 1108#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
1217 1109
1218
1219/*********************************************************************
1220 *
1221 * Interrupt Controller (INTC)
1222 *
1223 *********************************************************************/
1224
1225/* Register read/write macros */
1226#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
1227#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
1228#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
1229#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
1230#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
1231#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
1232#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
1233#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
1234#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
1235#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
1236#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
1237#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040)
1238#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
1239#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
1240#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
1241#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
1242#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
1243#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
1244#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
1245#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
1246#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
1247#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
1248#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
1249#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
1250#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
1251#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
1252#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
1253#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
1254#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
1255#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
1256#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
1257#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
1258#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
1259#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
1260#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
1261#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
1262#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
1263#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
1264#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
1265#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
1266#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
1267#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
1268#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
1269#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
1270#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
1271#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
1272#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
1273#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
1274#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
1275#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
1276#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
1277#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
1278#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
1279#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
1280#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
1281#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
1282#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
1283#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
1284#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
1285#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
1286#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
1287#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
1288#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
1289#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
1290#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
1291#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
1292#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
1293#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
1294#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
1295#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
1296#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
1297#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
1298#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
1299#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
1300#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
1301#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001))
1302#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
1303#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
1304#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
1305#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
1306#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
1307#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
1308#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
1309#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
1310#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004))
1311#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
1312#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
1313#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
1314#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
1315#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
1316#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
1317#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
1318#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
1319#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
1320#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
1321#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
1322#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040)
1323#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
1324#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
1325#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
1326#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
1327#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
1328#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
1329#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
1330#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
1331#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
1332#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
1333#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
1334#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
1335#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
1336#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
1337#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
1338#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
1339#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
1340#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
1341#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
1342#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
1343#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
1344#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
1345#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
1346#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
1347#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
1348#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
1349#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
1350#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
1351#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
1352#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
1353#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
1354#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
1355#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
1356#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
1357#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
1358#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
1359#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
1360#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
1361#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
1362#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
1363#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
1364#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
1365#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
1366#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
1367#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
1368#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
1369#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
1370#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
1371#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
1372#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
1373#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
1374#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
1375#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
1376#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
1377#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
1378#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
1379#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
1380#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
1381#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
1382#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
1383#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
1384#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
1385#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
1386#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001))
1387#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
1388#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
1389#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
1390#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
1391#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
1392#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
1393#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8)
1394#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
1395#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004))
1396#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
1397#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
1398#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
1399#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
1400#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
1401#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
1402#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
1403#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
1404#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
1405#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
1406#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
1407#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000))
1408#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
1409#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
1410#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
1411#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
1412#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
1413#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
1414#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
1415#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
1416#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
1417#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
1418#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
1419#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
1420#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
1421#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
1422#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
1423#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
1424#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
1425#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
1426#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
1427#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
1428#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
1429#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
1430#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
1431#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
1432#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
1433#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
1434#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
1435#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
1436#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
1437#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
1438#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
1439#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
1440#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
1441#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
1442#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
1443#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
1444#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
1445#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
1446#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
1447#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
1448#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
1449#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
1450#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
1451#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
1452#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
1453#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
1454#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
1455#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
1456#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
1457#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
1458#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
1459#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
1460#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
1461#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
1462#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
1463#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
1464#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
1465#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
1466#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
1467#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
1468#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
1469#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
1470#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
1471#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
1472#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
1473#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
1474#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
1475#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
1476#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
1477#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
1478#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
1479
1480/* Bit definitions and macros for MCF_INTC_IPRH */
1481#define MCF_INTC_IPRH_INT32 (0x00000001)
1482#define MCF_INTC_IPRH_INT33 (0x00000002)
1483#define MCF_INTC_IPRH_INT34 (0x00000004)
1484#define MCF_INTC_IPRH_INT35 (0x00000008)
1485#define MCF_INTC_IPRH_INT36 (0x00000010)
1486#define MCF_INTC_IPRH_INT37 (0x00000020)
1487#define MCF_INTC_IPRH_INT38 (0x00000040)
1488#define MCF_INTC_IPRH_INT39 (0x00000080)
1489#define MCF_INTC_IPRH_INT40 (0x00000100)
1490#define MCF_INTC_IPRH_INT41 (0x00000200)
1491#define MCF_INTC_IPRH_INT42 (0x00000400)
1492#define MCF_INTC_IPRH_INT43 (0x00000800)
1493#define MCF_INTC_IPRH_INT44 (0x00001000)
1494#define MCF_INTC_IPRH_INT45 (0x00002000)
1495#define MCF_INTC_IPRH_INT46 (0x00004000)
1496#define MCF_INTC_IPRH_INT47 (0x00008000)
1497#define MCF_INTC_IPRH_INT48 (0x00010000)
1498#define MCF_INTC_IPRH_INT49 (0x00020000)
1499#define MCF_INTC_IPRH_INT50 (0x00040000)
1500#define MCF_INTC_IPRH_INT51 (0x00080000)
1501#define MCF_INTC_IPRH_INT52 (0x00100000)
1502#define MCF_INTC_IPRH_INT53 (0x00200000)
1503#define MCF_INTC_IPRH_INT54 (0x00400000)
1504#define MCF_INTC_IPRH_INT55 (0x00800000)
1505#define MCF_INTC_IPRH_INT56 (0x01000000)
1506#define MCF_INTC_IPRH_INT57 (0x02000000)
1507#define MCF_INTC_IPRH_INT58 (0x04000000)
1508#define MCF_INTC_IPRH_INT59 (0x08000000)
1509#define MCF_INTC_IPRH_INT60 (0x10000000)
1510#define MCF_INTC_IPRH_INT61 (0x20000000)
1511#define MCF_INTC_IPRH_INT62 (0x40000000)
1512#define MCF_INTC_IPRH_INT63 (0x80000000)
1513
1514/* Bit definitions and macros for MCF_INTC_IPRL */
1515#define MCF_INTC_IPRL_INT0 (0x00000001)
1516#define MCF_INTC_IPRL_INT1 (0x00000002)
1517#define MCF_INTC_IPRL_INT2 (0x00000004)
1518#define MCF_INTC_IPRL_INT3 (0x00000008)
1519#define MCF_INTC_IPRL_INT4 (0x00000010)
1520#define MCF_INTC_IPRL_INT5 (0x00000020)
1521#define MCF_INTC_IPRL_INT6 (0x00000040)
1522#define MCF_INTC_IPRL_INT7 (0x00000080)
1523#define MCF_INTC_IPRL_INT8 (0x00000100)
1524#define MCF_INTC_IPRL_INT9 (0x00000200)
1525#define MCF_INTC_IPRL_INT10 (0x00000400)
1526#define MCF_INTC_IPRL_INT11 (0x00000800)
1527#define MCF_INTC_IPRL_INT12 (0x00001000)
1528#define MCF_INTC_IPRL_INT13 (0x00002000)
1529#define MCF_INTC_IPRL_INT14 (0x00004000)
1530#define MCF_INTC_IPRL_INT15 (0x00008000)
1531#define MCF_INTC_IPRL_INT16 (0x00010000)
1532#define MCF_INTC_IPRL_INT17 (0x00020000)
1533#define MCF_INTC_IPRL_INT18 (0x00040000)
1534#define MCF_INTC_IPRL_INT19 (0x00080000)
1535#define MCF_INTC_IPRL_INT20 (0x00100000)
1536#define MCF_INTC_IPRL_INT21 (0x00200000)
1537#define MCF_INTC_IPRL_INT22 (0x00400000)
1538#define MCF_INTC_IPRL_INT23 (0x00800000)
1539#define MCF_INTC_IPRL_INT24 (0x01000000)
1540#define MCF_INTC_IPRL_INT25 (0x02000000)
1541#define MCF_INTC_IPRL_INT26 (0x04000000)
1542#define MCF_INTC_IPRL_INT27 (0x08000000)
1543#define MCF_INTC_IPRL_INT28 (0x10000000)
1544#define MCF_INTC_IPRL_INT29 (0x20000000)
1545#define MCF_INTC_IPRL_INT30 (0x40000000)
1546#define MCF_INTC_IPRL_INT31 (0x80000000)
1547
1548/* Bit definitions and macros for MCF_INTC_IMRH */
1549#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
1550#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
1551#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
1552#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
1553#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
1554#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
1555#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
1556#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
1557#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
1558#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
1559#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
1560#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
1561#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
1562#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
1563#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
1564#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
1565#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
1566#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
1567#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
1568#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
1569#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
1570#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
1571#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
1572#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
1573#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
1574#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
1575#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
1576#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
1577#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
1578#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
1579#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
1580#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
1581
1582/* Bit definitions and macros for MCF_INTC_IMRL */
1583#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
1584#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
1585#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
1586#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
1587#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
1588#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
1589#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
1590#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
1591#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
1592#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
1593#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
1594#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
1595#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
1596#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
1597#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
1598#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
1599#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
1600#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
1601#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
1602#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
1603#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
1604#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
1605#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
1606#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
1607#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
1608#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
1609#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
1610#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
1611#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
1612#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
1613#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
1614#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
1615
1616/* Bit definitions and macros for MCF_INTC_INTFRCH */
1617#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
1618#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
1619#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
1620#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
1621#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
1622#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
1623#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
1624#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
1625#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
1626#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
1627#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
1628#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
1629#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
1630#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
1631#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
1632#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
1633#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
1634#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
1635#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
1636#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
1637#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
1638#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
1639#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
1640#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
1641#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
1642#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
1643#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
1644#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
1645#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
1646#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
1647#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
1648#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
1649
1650/* Bit definitions and macros for MCF_INTC_INTFRCL */
1651#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
1652#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
1653#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
1654#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
1655#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
1656#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
1657#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
1658#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
1659#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
1660#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
1661#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
1662#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
1663#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
1664#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
1665#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
1666#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
1667#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
1668#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
1669#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
1670#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
1671#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
1672#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
1673#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
1674#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
1675#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
1676#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
1677#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
1678#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
1679#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
1680#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
1681#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
1682#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
1683
1684/* Bit definitions and macros for MCF_INTC_ICONFIG */
1685#define MCF_INTC_ICONFIG_EMASK (0x0020)
1686#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
1687#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
1688#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
1689#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
1690#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
1691#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
1692#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
1693
1694/* Bit definitions and macros for MCF_INTC_SIMR */
1695#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
1696
1697/* Bit definitions and macros for MCF_INTC_CIMR */
1698#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
1699
1700/* Bit definitions and macros for MCF_INTC_CLMASK */
1701#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
1702
1703/* Bit definitions and macros for MCF_INTC_SLMASK */
1704#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
1705
1706/* Bit definitions and macros for MCF_INTC_ICR */
1707#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
1708
1709/* Bit definitions and macros for MCF_INTC_SWIACK */
1710#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
1711
1712/* Bit definitions and macros for MCF_INTC_LIACK */
1713#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
1714
1715/********************************************************************/
1716/*********************************************************************
1717*
1718* LCD Controller (LCDC)
1719*
1720*********************************************************************/
1721
1722/* Register read/write macros */
1723#define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000)
1724#define MCF_LCDC_LSR MCF_REG32(0xFC0AC004)
1725#define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008)
1726#define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C)
1727#define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010)
1728#define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014)
1729#define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018)
1730#define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C)
1731#define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020)
1732#define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024)
1733#define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028)
1734#define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C)
1735#define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030)
1736#define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034)
1737#define MCF_LCDC_LICR MCF_REG32(0xFC0AC038)
1738#define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C)
1739#define MCF_LCDC_LISR MCF_REG32(0xFC0AC040)
1740#define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050)
1741#define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054)
1742#define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058)
1743#define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C)
1744#define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060)
1745#define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064)
1746#define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068)
1747#define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800)
1748#define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00)
1749
1750/* Bit definitions and macros for MCF_LCDC_LSSAR */
1751#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
1752
1753/* Bit definitions and macros for MCF_LCDC_LSR */
1754#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
1755#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
1756
1757/* Bit definitions and macros for MCF_LCDC_LVPWR */
1758#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
1759
1760/* Bit definitions and macros for MCF_LCDC_LCPR */
1761#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
1762#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
1763#define MCF_LCDC_LCPR_OP (0x10000000)
1764#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
1765#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000)
1766#define MCF_LCDC_LCPR_CC_OR (0x40000000)
1767#define MCF_LCDC_LCPR_CC_XOR (0x80000000)
1768#define MCF_LCDC_LCPR_CC_AND (0xC0000000)
1769#define MCF_LCDC_LCPR_OP_ON (0x10000000)
1770#define MCF_LCDC_LCPR_OP_OFF (0x00000000)
1771
1772/* Bit definitions and macros for MCF_LCDC_LCWHBR */
1773#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
1774#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
1775#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
1776#define MCF_LCDC_LCWHBR_BK_EN (0x80000000)
1777#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000)
1778#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000)
1779
1780/* Bit definitions and macros for MCF_LCDC_LCCMR */
1781#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
1782#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
1783#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
1784
1785/* Bit definitions and macros for MCF_LCDC_LPCR */
1786#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
1787#define MCF_LCDC_LPCR_SHARP (0x00000040)
1788#define MCF_LCDC_LPCR_SCLKSEL (0x00000080)
1789#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
1790#define MCF_LCDC_LPCR_ACDSEL (0x00008000)
1791#define MCF_LCDC_LPCR_REV_VS (0x00010000)
1792#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000)
1793#define MCF_LCDC_LPCR_ENDSEL (0x00040000)
1794#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000)
1795#define MCF_LCDC_LPCR_OEPOL (0x00100000)
1796#define MCF_LCDC_LPCR_CLKPOL (0x00200000)
1797#define MCF_LCDC_LPCR_LPPOL (0x00400000)
1798#define MCF_LCDC_LPCR_FLM (0x00800000)
1799#define MCF_LCDC_LPCR_PIXPOL (0x01000000)
1800#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
1801#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
1802#define MCF_LCDC_LPCR_COLOR (0x40000000)
1803#define MCF_LCDC_LPCR_TFT (0x80000000)
1804#define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000)
1805#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000)
1806#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000)
1807#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000)
1808#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000)
1809#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000)
1810#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000)
1811#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000)
1812#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000)
1813#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000)
1814#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000)
1815#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000)
1816#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000)
1817#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000)
1818
1819#define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
1820
1821/* Bit definitions and macros for MCF_LCDC_LHCR */
1822#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
1823#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
1824#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
1825
1826/* Bit definitions and macros for MCF_LCDC_LVCR */
1827#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
1828#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
1829#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
1830
1831/* Bit definitions and macros for MCF_LCDC_LPOR */
1832#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
1833
1834/* Bit definitions and macros for MCF_LCDC_LPCCR */
1835#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
1836#define MCF_LCDC_LPCCR_CC_EN (0x00000100)
1837#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
1838#define MCF_LCDC_LPCCR_LDMSK (0x00008000)
1839#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
1840#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
1841#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
1842#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
1843
1844/* Bit definitions and macros for MCF_LCDC_LDCR */
1845#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
1846#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
1847#define MCF_LCDC_LDCR_BURST (0x80000000)
1848
1849/* Bit definitions and macros for MCF_LCDC_LRMCR */
1850#define MCF_LCDC_LRMCR_SEL_REF (0x00000001)
1851
1852/* Bit definitions and macros for MCF_LCDC_LICR */
1853#define MCF_LCDC_LICR_INTCON (0x00000001)
1854#define MCF_LCDC_LICR_INTSYN (0x00000004)
1855#define MCF_LCDC_LICR_GW_INT_CON (0x00000010)
1856
1857/* Bit definitions and macros for MCF_LCDC_LIER */
1858#define MCF_LCDC_LIER_BOF_EN (0x00000001)
1859#define MCF_LCDC_LIER_EOF_EN (0x00000002)
1860#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004)
1861#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008)
1862#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010)
1863#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020)
1864#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040)
1865#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
1866
1867/* Bit definitions and macros for MCF_LCDC_LISR */
1868#define MCF_LCDC_LISR_BOF (0x00000001)
1869#define MCF_LCDC_LISR_EOF (0x00000002)
1870#define MCF_LCDC_LISR_ERR_RES (0x00000004)
1871#define MCF_LCDC_LISR_UDR_ERR (0x00000008)
1872#define MCF_LCDC_LISR_GW_BOF (0x00000010)
1873#define MCF_LCDC_LISR_GW_EOF (0x00000020)
1874#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040)
1875#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080)
1876
1877/* Bit definitions and macros for MCF_LCDC_LGWSAR */
1878#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
1879
1880/* Bit definitions and macros for MCF_LCDC_LGWSR */
1881#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
1882#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
1883
1884/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
1885#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
1886
1887/* Bit definitions and macros for MCF_LCDC_LGWPOR */
1888#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
1889
1890/* Bit definitions and macros for MCF_LCDC_LGWPR */
1891#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
1892#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
1893
1894/* Bit definitions and macros for MCF_LCDC_LGWCR */
1895#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
1896#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
1897#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
1898#define MCF_LCDC_LGWCR_GW_RVS (0x00200000)
1899#define MCF_LCDC_LGWCR_GWE (0x00400000)
1900#define MCF_LCDC_LGWCR_GWCKE (0x00800000)
1901#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
1902
1903/* Bit definitions and macros for MCF_LCDC_LGWDCR */
1904#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
1905#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
1906#define MCF_LCDC_LGWDCR_GWBT (0x80000000)
1907
1908/* Bit definitions and macros for MCF_LCDC_LSCR */
1909#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26)
1910#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16)
1911#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
1912#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4)
1913#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0)
1914
1915/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
1916#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1917
1918/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
1919#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1920
1921/********************************************************************* 1110/*********************************************************************
1922 * 1111 *
1923 * Phase Locked Loop (PLL) 1112 * Phase Locked Loop (PLL)
@@ -2046,143 +1235,9 @@
2046#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) 1235#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
2047#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) 1236#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
2048 1237
2049/*********************************************************************
2050 *
2051 * FlexCAN module registers
2052 *
2053 *********************************************************************/
2054#define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800)
2055#define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00)
2056#define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04)
2057#define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08)
2058#define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10)
2059#define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14)
2060#define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18)
2061#define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
2062#define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20)
2063#define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28)
2064#define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30)
2065
2066#define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
2067#define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
2068#define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
2069
2070/*
2071 * FlexCAN Module Configuration Register
2072 */
2073#define CANMCR_MDIS (0x80000000)
2074#define CANMCR_FRZ (0x40000000)
2075#define CANMCR_HALT (0x10000000)
2076#define CANMCR_SOFTRST (0x02000000)
2077#define CANMCR_FRZACK (0x01000000)
2078#define CANMCR_SUPV (0x00800000)
2079#define CANMCR_MAXMB(x) ((x)&0x0F)
2080
2081/*
2082 * FlexCAN Control Register
2083 */
2084#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
2085#define CANCTRL_RJW(x) (((x)&0x03)<<22)
2086#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
2087#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
2088#define CANCTRL_BOFFMSK (0x00008000)
2089#define CANCTRL_ERRMSK (0x00004000)
2090#define CANCTRL_CLKSRC (0x00002000)
2091#define CANCTRL_LPB (0x00001000)
2092#define CANCTRL_SAMP (0x00000080)
2093#define CANCTRL_BOFFREC (0x00000040)
2094#define CANCTRL_TSYNC (0x00000020)
2095#define CANCTRL_LBUF (0x00000010)
2096#define CANCTRL_LOM (0x00000008)
2097#define CANCTRL_PROPSEG(x) ((x)&0x07)
2098
2099/*
2100 * FlexCAN Error Counter Register
2101 */
2102#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
2103#define ERRCNT_TXECTR(x) ((x)&0xFF)
2104
2105/*
2106 * FlexCAN Error and Status Register
2107 */
2108#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
2109#define ERRSTAT_ACKERR (0x00002000)
2110#define ERRSTAT_CRCERR (0x00001000)
2111#define ERRSTAT_FRMERR (0x00000800)
2112#define ERRSTAT_STFERR (0x00000400)
2113#define ERRSTAT_TXWRN (0x00000200)
2114#define ERRSTAT_RXWRN (0x00000100)
2115#define ERRSTAT_IDLE (0x00000080)
2116#define ERRSTAT_TXRX (0x00000040)
2117#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
2118#define ERRSTAT_BOFFINT (0x00000004)
2119#define ERRSTAT_ERRINT (0x00000002)
2120
2121/* 1238/*
2122 * Interrupt Mask Register
2123 */
2124#define IMASK_BUF15M (0x8000)
2125#define IMASK_BUF14M (0x4000)
2126#define IMASK_BUF13M (0x2000)
2127#define IMASK_BUF12M (0x1000)
2128#define IMASK_BUF11M (0x0800)
2129#define IMASK_BUF10M (0x0400)
2130#define IMASK_BUF9M (0x0200)
2131#define IMASK_BUF8M (0x0100)
2132#define IMASK_BUF7M (0x0080)
2133#define IMASK_BUF6M (0x0040)
2134#define IMASK_BUF5M (0x0020)
2135#define IMASK_BUF4M (0x0010)
2136#define IMASK_BUF3M (0x0008)
2137#define IMASK_BUF2M (0x0004)
2138#define IMASK_BUF1M (0x0002)
2139#define IMASK_BUF0M (0x0001)
2140#define IMASK_BUFnM(x) (0x1<<(x))
2141#define IMASK_BUFF_ENABLE_ALL (0x1111)
2142#define IMASK_BUFF_DISABLE_ALL (0x0000)
2143
2144/*
2145 * Interrupt Flag Register
2146 */
2147#define IFLAG_BUF15M (0x8000)
2148#define IFLAG_BUF14M (0x4000)
2149#define IFLAG_BUF13M (0x2000)
2150#define IFLAG_BUF12M (0x1000)
2151#define IFLAG_BUF11M (0x0800)
2152#define IFLAG_BUF10M (0x0400)
2153#define IFLAG_BUF9M (0x0200)
2154#define IFLAG_BUF8M (0x0100)
2155#define IFLAG_BUF7M (0x0080)
2156#define IFLAG_BUF6M (0x0040)
2157#define IFLAG_BUF5M (0x0020)
2158#define IFLAG_BUF4M (0x0010)
2159#define IFLAG_BUF3M (0x0008)
2160#define IFLAG_BUF2M (0x0004)
2161#define IFLAG_BUF1M (0x0002)
2162#define IFLAG_BUF0M (0x0001)
2163#define IFLAG_BUFF_SET_ALL (0xFFFF)
2164#define IFLAG_BUFF_CLEAR_ALL (0x0000)
2165#define IFLAG_BUFnM(x) (0x1<<(x))
2166
2167/*
2168 * Message Buffers
2169 */
2170#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
2171#define MB_CNT_SRR (0x00400000)
2172#define MB_CNT_IDE (0x00200000)
2173#define MB_CNT_RTR (0x00100000)
2174#define MB_CNT_LENGTH(x) (((x)&0x0F)<<16)
2175#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
2176#define MB_ID_STD(x) (((x)&0x07FF)<<18)
2177#define MB_ID_EXT(x) ((x)&0x3FFFF)
2178
2179/*********************************************************************
2180 *
2181 * Edge Port Module (EPORT) 1239 * Edge Port Module (EPORT)
2182 * 1240 */
2183 *********************************************************************/
2184
2185/* Register read/write macros */
2186#define MCFEPORT_EPPAR (0xFC094000) 1241#define MCFEPORT_EPPAR (0xFC094000)
2187#define MCFEPORT_EPDDR (0xFC094002) 1242#define MCFEPORT_EPDDR (0xFC094002)
2188#define MCFEPORT_EPIER (0xFC094003) 1243#define MCFEPORT_EPIER (0xFC094003)
@@ -2190,91 +1245,5 @@
2190#define MCFEPORT_EPPDR (0xFC094005) 1245#define MCFEPORT_EPPDR (0xFC094005)
2191#define MCFEPORT_EPFR (0xFC094006) 1246#define MCFEPORT_EPFR (0xFC094006)
2192 1247
2193/* Bit definitions and macros for MCF_EPORT_EPPAR */
2194#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
2195#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
2196#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
2197#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
2198#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
2199#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
2200#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
2201#define MCF_EPORT_EPPAR_LEVEL (0)
2202#define MCF_EPORT_EPPAR_RISING (1)
2203#define MCF_EPORT_EPPAR_FALLING (2)
2204#define MCF_EPORT_EPPAR_BOTH (3)
2205#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
2206#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
2207#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
2208#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
2209#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
2210#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
2211#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
2212#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
2213#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
2214#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
2215#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
2216#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
2217#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
2218#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
2219#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
2220#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
2221#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
2222#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
2223#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
2224#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
2225#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
2226#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
2227#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
2228#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
2229#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
2230#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
2231#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
2232#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
2233
2234/* Bit definitions and macros for MCF_EPORT_EPDDR */
2235#define MCF_EPORT_EPDDR_EPDD1 (0x02)
2236#define MCF_EPORT_EPDDR_EPDD2 (0x04)
2237#define MCF_EPORT_EPDDR_EPDD3 (0x08)
2238#define MCF_EPORT_EPDDR_EPDD4 (0x10)
2239#define MCF_EPORT_EPDDR_EPDD5 (0x20)
2240#define MCF_EPORT_EPDDR_EPDD6 (0x40)
2241#define MCF_EPORT_EPDDR_EPDD7 (0x80)
2242
2243/* Bit definitions and macros for MCF_EPORT_EPIER */
2244#define MCF_EPORT_EPIER_EPIE1 (0x02)
2245#define MCF_EPORT_EPIER_EPIE2 (0x04)
2246#define MCF_EPORT_EPIER_EPIE3 (0x08)
2247#define MCF_EPORT_EPIER_EPIE4 (0x10)
2248#define MCF_EPORT_EPIER_EPIE5 (0x20)
2249#define MCF_EPORT_EPIER_EPIE6 (0x40)
2250#define MCF_EPORT_EPIER_EPIE7 (0x80)
2251
2252/* Bit definitions and macros for MCF_EPORT_EPDR */
2253#define MCF_EPORT_EPDR_EPD1 (0x02)
2254#define MCF_EPORT_EPDR_EPD2 (0x04)
2255#define MCF_EPORT_EPDR_EPD3 (0x08)
2256#define MCF_EPORT_EPDR_EPD4 (0x10)
2257#define MCF_EPORT_EPDR_EPD5 (0x20)
2258#define MCF_EPORT_EPDR_EPD6 (0x40)
2259#define MCF_EPORT_EPDR_EPD7 (0x80)
2260
2261/* Bit definitions and macros for MCF_EPORT_EPPDR */
2262#define MCF_EPORT_EPPDR_EPPD1 (0x02)
2263#define MCF_EPORT_EPPDR_EPPD2 (0x04)
2264#define MCF_EPORT_EPPDR_EPPD3 (0x08)
2265#define MCF_EPORT_EPPDR_EPPD4 (0x10)
2266#define MCF_EPORT_EPPDR_EPPD5 (0x20)
2267#define MCF_EPORT_EPPDR_EPPD6 (0x40)
2268#define MCF_EPORT_EPPDR_EPPD7 (0x80)
2269
2270/* Bit definitions and macros for MCF_EPORT_EPFR */
2271#define MCF_EPORT_EPFR_EPF1 (0x02)
2272#define MCF_EPORT_EPFR_EPF2 (0x04)
2273#define MCF_EPORT_EPFR_EPF3 (0x08)
2274#define MCF_EPORT_EPFR_EPF4 (0x10)
2275#define MCF_EPORT_EPFR_EPF5 (0x20)
2276#define MCF_EPORT_EPFR_EPF6 (0x40)
2277#define MCF_EPORT_EPFR_EPF7 (0x80)
2278
2279/********************************************************************/ 1248/********************************************************************/
2280#endif /* m532xsim_h */ 1249#endif /* m532xsim_h */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 16:31:24 -0500