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authorHirokazu Takata <takata@linux-m32r.org>2007-08-01 08:09:31 -0400
committerHirokazu Takata <takata@linux-m32r.org>2007-09-02 22:30:18 -0400
commit3264f976d3188bea80819793c13a3220b8a4867c (patch)
treee451b9179430ddbbe1102050ebf391433248c1e1 /arch/m32r/platforms/m32700ut
parente6a7ba7efddbb393b726453eae8601ef02b9a610 (diff)
m32r: Rearrange platform-dependent codes
Rearrange platform-dependent codes from arch/m32r/kernel/*.c to arch/m32r/platforms/{platform}/. Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Diffstat (limited to 'arch/m32r/platforms/m32700ut')
-rw-r--r--arch/m32r/platforms/m32700ut/Makefile1
-rw-r--r--arch/m32r/platforms/m32700ut/io.c395
-rw-r--r--arch/m32r/platforms/m32700ut/setup.c518
3 files changed, 914 insertions, 0 deletions
diff --git a/arch/m32r/platforms/m32700ut/Makefile b/arch/m32r/platforms/m32700ut/Makefile
new file mode 100644
index 000000000000..0de59084f21c
--- /dev/null
+++ b/arch/m32r/platforms/m32700ut/Makefile
@@ -0,0 +1 @@
obj-y := setup.o io.o
diff --git a/arch/m32r/platforms/m32700ut/io.c b/arch/m32r/platforms/m32700ut/io.c
new file mode 100644
index 000000000000..6862586e58db
--- /dev/null
+++ b/arch/m32r/platforms/m32700ut/io.c
@@ -0,0 +1,395 @@
1/*
2 * linux/arch/m32r/platforms/m32700ut/io.c
3 *
4 * Typical I/O routines for M32700UT board.
5 *
6 * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto, Takeo Takahashi
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of this
11 * archive for more details.
12 */
13
14#include <asm/m32r.h>
15#include <asm/page.h>
16#include <asm/io.h>
17#include <asm/byteorder.h>
18
19#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
20#include <linux/types.h>
21
22#define M32R_PCC_IOMAP_SIZE 0x1000
23
24#define M32R_PCC_IOSTART0 0x1000
25#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
26
27extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
28extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
29extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
30extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
31#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
32
33#define PORT2ADDR(port) _port2addr(port)
34#define PORT2ADDR_USB(port) _port2addr_usb(port)
35
36static inline void *_port2addr(unsigned long port)
37{
38 return (void *)(port | NONCACHE_OFFSET);
39}
40
41#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
42static inline void *__port2addr_ata(unsigned long port)
43{
44 static int dummy_reg;
45
46 switch (port) {
47 case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
48 case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
49 case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
50 case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
51 case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
52 case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
53 case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
54 case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
55 case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
56 default: return (void *)&dummy_reg;
57 }
58}
59#endif
60
61/*
62 * M32700UT-LAN is located in the extended bus space
63 * from 0x10000000 to 0x13ffffff on physical address.
64 * The base address of LAN controller(LAN91C111) is 0x300.
65 */
66#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
67#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
68static inline void *_port2addr_ne(unsigned long port)
69{
70 return (void *)(port + 0x10000000);
71}
72static inline void *_port2addr_usb(unsigned long port)
73{
74 return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000);
75}
76
77static inline void delay(void)
78{
79 __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
80}
81
82/*
83 * NIC I/O function
84 */
85
86#define PORT2ADDR_NE(port) _port2addr_ne(port)
87
88static inline unsigned char _ne_inb(void *portp)
89{
90 return *(volatile unsigned char *)portp;
91}
92
93static inline unsigned short _ne_inw(void *portp)
94{
95 return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
96}
97
98static inline void _ne_insb(void *portp, void *addr, unsigned long count)
99{
100 unsigned char *buf = (unsigned char *)addr;
101
102 while (count--)
103 *buf++ = _ne_inb(portp);
104}
105
106static inline void _ne_outb(unsigned char b, void *portp)
107{
108 *(volatile unsigned char *)portp = b;
109}
110
111static inline void _ne_outw(unsigned short w, void *portp)
112{
113 *(volatile unsigned short *)portp = cpu_to_le16(w);
114}
115
116unsigned char _inb(unsigned long port)
117{
118 if (port >= LAN_IOSTART && port < LAN_IOEND)
119 return _ne_inb(PORT2ADDR_NE(port));
120
121#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
122 else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
123 return *(volatile unsigned char *)__port2addr_ata(port);
124 }
125#endif
126#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
127 else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
128 unsigned char b;
129 pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
130 return b;
131 } else
132#endif
133
134 return *(volatile unsigned char *)PORT2ADDR(port);
135}
136
137unsigned short _inw(unsigned long port)
138{
139 if (port >= LAN_IOSTART && port < LAN_IOEND)
140 return _ne_inw(PORT2ADDR_NE(port));
141#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
142 else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
143 return *(volatile unsigned short *)__port2addr_ata(port);
144 }
145#endif
146#if defined(CONFIG_USB)
147 else if(port >= 0x340 && port < 0x3a0)
148 return *(volatile unsigned short *)PORT2ADDR_USB(port);
149#endif
150#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
151 else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
152 unsigned short w;
153 pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
154 return w;
155 } else
156#endif
157 return *(volatile unsigned short *)PORT2ADDR(port);
158}
159
160unsigned long _inl(unsigned long port)
161{
162#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
163 if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
164 unsigned long l;
165 pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
166 return l;
167 } else
168#endif
169 return *(volatile unsigned long *)PORT2ADDR(port);
170}
171
172unsigned char _inb_p(unsigned long port)
173{
174 unsigned char v = _inb(port);
175 delay();
176 return (v);
177}
178
179unsigned short _inw_p(unsigned long port)
180{
181 unsigned short v = _inw(port);
182 delay();
183 return (v);
184}
185
186unsigned long _inl_p(unsigned long port)
187{
188 unsigned long v = _inl(port);
189 delay();
190 return (v);
191}
192
193void _outb(unsigned char b, unsigned long port)
194{
195 if (port >= LAN_IOSTART && port < LAN_IOEND)
196 _ne_outb(b, PORT2ADDR_NE(port));
197 else
198#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
199 if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
200 *(volatile unsigned char *)__port2addr_ata(port) = b;
201 } else
202#endif
203#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
204 if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
205 pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
206 } else
207#endif
208 *(volatile unsigned char *)PORT2ADDR(port) = b;
209}
210
211void _outw(unsigned short w, unsigned long port)
212{
213 if (port >= LAN_IOSTART && port < LAN_IOEND)
214 _ne_outw(w, PORT2ADDR_NE(port));
215 else
216#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
217 if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
218 *(volatile unsigned short *)__port2addr_ata(port) = w;
219 } else
220#endif
221#if defined(CONFIG_USB)
222 if(port >= 0x340 && port < 0x3a0)
223 *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
224 else
225#endif
226#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
227 if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
228 pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
229 } else
230#endif
231 *(volatile unsigned short *)PORT2ADDR(port) = w;
232}
233
234void _outl(unsigned long l, unsigned long port)
235{
236#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
237 if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
238 pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
239 } else
240#endif
241 *(volatile unsigned long *)PORT2ADDR(port) = l;
242}
243
244void _outb_p(unsigned char b, unsigned long port)
245{
246 _outb(b, port);
247 delay();
248}
249
250void _outw_p(unsigned short w, unsigned long port)
251{
252 _outw(w, port);
253 delay();
254}
255
256void _outl_p(unsigned long l, unsigned long port)
257{
258 _outl(l, port);
259 delay();
260}
261
262void _insb(unsigned int port, void *addr, unsigned long count)
263{
264 if (port >= LAN_IOSTART && port < LAN_IOEND)
265 _ne_insb(PORT2ADDR_NE(port), addr, count);
266#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
267 else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
268 unsigned char *buf = addr;
269 unsigned char *portp = __port2addr_ata(port);
270 while (count--)
271 *buf++ = *(volatile unsigned char *)portp;
272 }
273#endif
274#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
275 else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
276 pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
277 count, 1);
278 }
279#endif
280 else {
281 unsigned char *buf = addr;
282 unsigned char *portp = PORT2ADDR(port);
283 while (count--)
284 *buf++ = *(volatile unsigned char *)portp;
285 }
286}
287
288void _insw(unsigned int port, void *addr, unsigned long count)
289{
290 unsigned short *buf = addr;
291 unsigned short *portp;
292
293 if (port >= LAN_IOSTART && port < LAN_IOEND) {
294 /*
295 * This portion is only used by smc91111.c to read data
296 * from the DATA_REG. Do not swap the data.
297 */
298 portp = PORT2ADDR_NE(port);
299 while (count--)
300 *buf++ = *(volatile unsigned short *)portp;
301#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
302 } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
303 pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
304 count, 1);
305#endif
306#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
307 } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
308 portp = __port2addr_ata(port);
309 while (count--)
310 *buf++ = *(volatile unsigned short *)portp;
311#endif
312 } else {
313 portp = PORT2ADDR(port);
314 while (count--)
315 *buf++ = *(volatile unsigned short *)portp;
316 }
317}
318
319void _insl(unsigned int port, void *addr, unsigned long count)
320{
321 unsigned long *buf = addr;
322 unsigned long *portp;
323
324 portp = PORT2ADDR(port);
325 while (count--)
326 *buf++ = *(volatile unsigned long *)portp;
327}
328
329void _outsb(unsigned int port, const void *addr, unsigned long count)
330{
331 const unsigned char *buf = addr;
332 unsigned char *portp;
333
334 if (port >= LAN_IOSTART && port < LAN_IOEND) {
335 portp = PORT2ADDR_NE(port);
336 while (count--)
337 _ne_outb(*buf++, portp);
338#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
339 } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
340 portp = __port2addr_ata(port);
341 while (count--)
342 *(volatile unsigned char *)portp = *buf++;
343#endif
344#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
345 } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
346 pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
347 count, 1);
348#endif
349 } else {
350 portp = PORT2ADDR(port);
351 while (count--)
352 *(volatile unsigned char *)portp = *buf++;
353 }
354}
355
356void _outsw(unsigned int port, const void *addr, unsigned long count)
357{
358 const unsigned short *buf = addr;
359 unsigned short *portp;
360
361 if (port >= LAN_IOSTART && port < LAN_IOEND) {
362 /*
363 * This portion is only used by smc91111.c to write data
364 * into the DATA_REG. Do not swap the data.
365 */
366 portp = PORT2ADDR_NE(port);
367 while (count--)
368 *(volatile unsigned short *)portp = *buf++;
369#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
370 } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
371 portp = __port2addr_ata(port);
372 while (count--)
373 *(volatile unsigned short *)portp = *buf++;
374#endif
375#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
376 } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
377 pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
378 count, 1);
379#endif
380 } else {
381 portp = PORT2ADDR(port);
382 while (count--)
383 *(volatile unsigned short *)portp = *buf++;
384 }
385}
386
387void _outsl(unsigned int port, const void *addr, unsigned long count)
388{
389 const unsigned long *buf = addr;
390 unsigned char *portp;
391
392 portp = PORT2ADDR(port);
393 while (count--)
394 *(volatile unsigned long *)portp = *buf++;
395}
diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c
new file mode 100644
index 000000000000..77b0ae9379e9
--- /dev/null
+++ b/arch/m32r/platforms/m32700ut/setup.c
@@ -0,0 +1,518 @@
1/*
2 * linux/arch/m32r/platforms/m32700ut/setup.c
3 *
4 * Setup routines for Renesas M32700UT Board
5 *
6 * Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto, Takeo Takahashi
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of this
11 * archive for more details.
12 */
13
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18
19#include <asm/system.h>
20#include <asm/m32r.h>
21#include <asm/io.h>
22
23/*
24 * M32700 Interrupt Control Unit (Level 1)
25 */
26#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
27
28icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
29
30static void disable_m32700ut_irq(unsigned int irq)
31{
32 unsigned long port, data;
33
34 port = irq2port(irq);
35 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
36 outl(data, port);
37}
38
39static void enable_m32700ut_irq(unsigned int irq)
40{
41 unsigned long port, data;
42
43 port = irq2port(irq);
44 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
45 outl(data, port);
46}
47
48static void mask_and_ack_m32700ut(unsigned int irq)
49{
50 disable_m32700ut_irq(irq);
51}
52
53static void end_m32700ut_irq(unsigned int irq)
54{
55 enable_m32700ut_irq(irq);
56}
57
58static unsigned int startup_m32700ut_irq(unsigned int irq)
59{
60 enable_m32700ut_irq(irq);
61 return (0);
62}
63
64static void shutdown_m32700ut_irq(unsigned int irq)
65{
66 unsigned long port;
67
68 port = irq2port(irq);
69 outl(M32R_ICUCR_ILEVEL7, port);
70}
71
72static struct hw_interrupt_type m32700ut_irq_type =
73{
74 .typename = "M32700UT-IRQ",
75 .startup = startup_m32700ut_irq,
76 .shutdown = shutdown_m32700ut_irq,
77 .enable = enable_m32700ut_irq,
78 .disable = disable_m32700ut_irq,
79 .ack = mask_and_ack_m32700ut,
80 .end = end_m32700ut_irq
81};
82
83/*
84 * Interrupt Control Unit of PLD on M32700UT (Level 2)
85 */
86#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
87#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
88 (((x) - 1) * sizeof(unsigned short)))
89
90typedef struct {
91 unsigned short icucr; /* ICU Control Register */
92} pld_icu_data_t;
93
94static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
95
96static void disable_m32700ut_pld_irq(unsigned int irq)
97{
98 unsigned long port, data;
99 unsigned int pldirq;
100
101 pldirq = irq2pldirq(irq);
102// disable_m32700ut_irq(M32R_IRQ_INT1);
103 port = pldirq2port(pldirq);
104 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
105 outw(data, port);
106}
107
108static void enable_m32700ut_pld_irq(unsigned int irq)
109{
110 unsigned long port, data;
111 unsigned int pldirq;
112
113 pldirq = irq2pldirq(irq);
114// enable_m32700ut_irq(M32R_IRQ_INT1);
115 port = pldirq2port(pldirq);
116 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
117 outw(data, port);
118}
119
120static void mask_and_ack_m32700ut_pld(unsigned int irq)
121{
122 disable_m32700ut_pld_irq(irq);
123// mask_and_ack_m32700ut(M32R_IRQ_INT1);
124}
125
126static void end_m32700ut_pld_irq(unsigned int irq)
127{
128 enable_m32700ut_pld_irq(irq);
129 end_m32700ut_irq(M32R_IRQ_INT1);
130}
131
132static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
133{
134 enable_m32700ut_pld_irq(irq);
135 return (0);
136}
137
138static void shutdown_m32700ut_pld_irq(unsigned int irq)
139{
140 unsigned long port;
141 unsigned int pldirq;
142
143 pldirq = irq2pldirq(irq);
144// shutdown_m32700ut_irq(M32R_IRQ_INT1);
145 port = pldirq2port(pldirq);
146 outw(PLD_ICUCR_ILEVEL7, port);
147}
148
149static struct hw_interrupt_type m32700ut_pld_irq_type =
150{
151 .typename = "M32700UT-PLD-IRQ",
152 .startup = startup_m32700ut_pld_irq,
153 .shutdown = shutdown_m32700ut_pld_irq,
154 .enable = enable_m32700ut_pld_irq,
155 .disable = disable_m32700ut_pld_irq,
156 .ack = mask_and_ack_m32700ut_pld,
157 .end = end_m32700ut_pld_irq
158};
159
160/*
161 * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
162 */
163#define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
164#define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
165 (((x) - 1) * sizeof(unsigned short)))
166
167static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
168
169static void disable_m32700ut_lanpld_irq(unsigned int irq)
170{
171 unsigned long port, data;
172 unsigned int pldirq;
173
174 pldirq = irq2lanpldirq(irq);
175 port = lanpldirq2port(pldirq);
176 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
177 outw(data, port);
178}
179
180static void enable_m32700ut_lanpld_irq(unsigned int irq)
181{
182 unsigned long port, data;
183 unsigned int pldirq;
184
185 pldirq = irq2lanpldirq(irq);
186 port = lanpldirq2port(pldirq);
187 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
188 outw(data, port);
189}
190
191static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
192{
193 disable_m32700ut_lanpld_irq(irq);
194}
195
196static void end_m32700ut_lanpld_irq(unsigned int irq)
197{
198 enable_m32700ut_lanpld_irq(irq);
199 end_m32700ut_irq(M32R_IRQ_INT0);
200}
201
202static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
203{
204 enable_m32700ut_lanpld_irq(irq);
205 return (0);
206}
207
208static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
209{
210 unsigned long port;
211 unsigned int pldirq;
212
213 pldirq = irq2lanpldirq(irq);
214 port = lanpldirq2port(pldirq);
215 outw(PLD_ICUCR_ILEVEL7, port);
216}
217
218static struct hw_interrupt_type m32700ut_lanpld_irq_type =
219{
220 .typename = "M32700UT-PLD-LAN-IRQ",
221 .startup = startup_m32700ut_lanpld_irq,
222 .shutdown = shutdown_m32700ut_lanpld_irq,
223 .enable = enable_m32700ut_lanpld_irq,
224 .disable = disable_m32700ut_lanpld_irq,
225 .ack = mask_and_ack_m32700ut_lanpld,
226 .end = end_m32700ut_lanpld_irq
227};
228
229/*
230 * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
231 */
232#define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
233#define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
234 (((x) - 1) * sizeof(unsigned short)))
235
236static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
237
238static void disable_m32700ut_lcdpld_irq(unsigned int irq)
239{
240 unsigned long port, data;
241 unsigned int pldirq;
242
243 pldirq = irq2lcdpldirq(irq);
244 port = lcdpldirq2port(pldirq);
245 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
246 outw(data, port);
247}
248
249static void enable_m32700ut_lcdpld_irq(unsigned int irq)
250{
251 unsigned long port, data;
252 unsigned int pldirq;
253
254 pldirq = irq2lcdpldirq(irq);
255 port = lcdpldirq2port(pldirq);
256 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
257 outw(data, port);
258}
259
260static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
261{
262 disable_m32700ut_lcdpld_irq(irq);
263}
264
265static void end_m32700ut_lcdpld_irq(unsigned int irq)
266{
267 enable_m32700ut_lcdpld_irq(irq);
268 end_m32700ut_irq(M32R_IRQ_INT2);
269}
270
271static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
272{
273 enable_m32700ut_lcdpld_irq(irq);
274 return (0);
275}
276
277static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
278{
279 unsigned long port;
280 unsigned int pldirq;
281
282 pldirq = irq2lcdpldirq(irq);
283 port = lcdpldirq2port(pldirq);
284 outw(PLD_ICUCR_ILEVEL7, port);
285}
286
287static struct hw_interrupt_type m32700ut_lcdpld_irq_type =
288{
289 .typename = "M32700UT-PLD-LCD-IRQ",
290 .startup = startup_m32700ut_lcdpld_irq,
291 .shutdown = shutdown_m32700ut_lcdpld_irq,
292 .enable = enable_m32700ut_lcdpld_irq,
293 .disable = disable_m32700ut_lcdpld_irq,
294 .ack = mask_and_ack_m32700ut_lcdpld,
295 .end = end_m32700ut_lcdpld_irq
296};
297
298void __init init_IRQ(void)
299{
300#if defined(CONFIG_SMC91X)
301 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
302 irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
303 irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type;
304 irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
305 irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
306 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
307 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
308#endif /* CONFIG_SMC91X */
309
310 /* MFT2 : system timer */
311 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
312 irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type;
313 irq_desc[M32R_IRQ_MFT2].action = 0;
314 irq_desc[M32R_IRQ_MFT2].depth = 1;
315 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
316 disable_m32700ut_irq(M32R_IRQ_MFT2);
317
318 /* SIO0 : receive */
319 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
320 irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type;
321 irq_desc[M32R_IRQ_SIO0_R].action = 0;
322 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
323 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
324 disable_m32700ut_irq(M32R_IRQ_SIO0_R);
325
326 /* SIO0 : send */
327 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
328 irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type;
329 irq_desc[M32R_IRQ_SIO0_S].action = 0;
330 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
331 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
332 disable_m32700ut_irq(M32R_IRQ_SIO0_S);
333
334 /* SIO1 : receive */
335 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
336 irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type;
337 irq_desc[M32R_IRQ_SIO1_R].action = 0;
338 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
339 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
340 disable_m32700ut_irq(M32R_IRQ_SIO1_R);
341
342 /* SIO1 : send */
343 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
344 irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type;
345 irq_desc[M32R_IRQ_SIO1_S].action = 0;
346 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
347 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
348 disable_m32700ut_irq(M32R_IRQ_SIO1_S);
349
350 /* DMA1 : */
351 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
352 irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type;
353 irq_desc[M32R_IRQ_DMA1].action = 0;
354 irq_desc[M32R_IRQ_DMA1].depth = 1;
355 icu_data[M32R_IRQ_DMA1].icucr = 0;
356 disable_m32700ut_irq(M32R_IRQ_DMA1);
357
358#ifdef CONFIG_SERIAL_M32R_PLDSIO
359 /* INT#1: SIO0 Receive on PLD */
360 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
361 irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type;
362 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
363 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
364 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
365 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
366
367 /* INT#1: SIO0 Send on PLD */
368 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
369 irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type;
370 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
371 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
372 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
373 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
374#endif /* CONFIG_SERIAL_M32R_PLDSIO */
375
376 /* INT#1: CFC IREQ on PLD */
377 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
378 irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type;
379 irq_desc[PLD_IRQ_CFIREQ].action = 0;
380 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
381 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
382 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
383
384 /* INT#1: CFC Insert on PLD */
385 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
386 irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type;
387 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
388 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
389 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
390 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
391
392 /* INT#1: CFC Eject on PLD */
393 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
394 irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type;
395 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
396 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
397 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
398 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
399
400 /*
401 * INT0# is used for LAN, DIO
402 * We enable it here.
403 */
404 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
405 enable_m32700ut_irq(M32R_IRQ_INT0);
406
407 /*
408 * INT1# is used for UART, MMC, CF Controller in FPGA.
409 * We enable it here.
410 */
411 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
412 enable_m32700ut_irq(M32R_IRQ_INT1);
413
414#if defined(CONFIG_USB)
415 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
416
417 irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
418 irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type;
419 irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
420 irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
421 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
422 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
423#endif
424 /*
425 * INT2# is used for BAT, USB, AUDIO
426 * We enable it here.
427 */
428 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
429 enable_m32700ut_irq(M32R_IRQ_INT2);
430
431#if defined(CONFIG_VIDEO_M32R_AR)
432 /*
433 * INT3# is used for AR
434 */
435 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
436 irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type;
437 irq_desc[M32R_IRQ_INT3].action = 0;
438 irq_desc[M32R_IRQ_INT3].depth = 1;
439 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
440 disable_m32700ut_irq(M32R_IRQ_INT3);
441#endif /* CONFIG_VIDEO_M32R_AR */
442}
443
444#if defined(CONFIG_SMC91X)
445
446#define LAN_IOSTART 0x300
447#define LAN_IOEND 0x320
448static struct resource smc91x_resources[] = {
449 [0] = {
450 .start = (LAN_IOSTART),
451 .end = (LAN_IOEND),
452 .flags = IORESOURCE_MEM,
453 },
454 [1] = {
455 .start = M32700UT_LAN_IRQ_LAN,
456 .end = M32700UT_LAN_IRQ_LAN,
457 .flags = IORESOURCE_IRQ,
458 }
459};
460
461static struct platform_device smc91x_device = {
462 .name = "smc91x",
463 .id = 0,
464 .num_resources = ARRAY_SIZE(smc91x_resources),
465 .resource = smc91x_resources,
466};
467#endif
468
469#if defined(CONFIG_FB_S1D13XXX)
470
471#include <video/s1d13xxxfb.h>
472#include <asm/s1d13806.h>
473
474static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
475 .initregs = s1d13xxxfb_initregs,
476 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
477 .platform_init_video = NULL,
478#ifdef CONFIG_PM
479 .platform_suspend_video = NULL,
480 .platform_resume_video = NULL,
481#endif
482};
483
484static struct resource s1d13xxxfb_resources[] = {
485 [0] = {
486 .start = 0x10600000UL,
487 .end = 0x1073FFFFUL,
488 .flags = IORESOURCE_MEM,
489 },
490 [1] = {
491 .start = 0x10400000UL,
492 .end = 0x104001FFUL,
493 .flags = IORESOURCE_MEM,
494 }
495};
496
497static struct platform_device s1d13xxxfb_device = {
498 .name = S1D_DEVICENAME,
499 .id = 0,
500 .dev = {
501 .platform_data = &s1d13xxxfb_data,
502 },
503 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
504 .resource = s1d13xxxfb_resources,
505};
506#endif
507
508static int __init platform_init(void)
509{
510#if defined(CONFIG_SMC91X)
511 platform_device_register(&smc91x_device);
512#endif
513#if defined(CONFIG_FB_S1D13XXX)
514 platform_device_register(&s1d13xxxfb_device);
515#endif
516 return 0;
517}
518arch_initcall(platform_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 19:41:49 -0500