blackfin: mach-common: add sec support for bf60x

Add system event controller support for bf60x so that interrupt can be
handled.

Signed-off-by: Steven Miao <realmz6@gmail.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>

1 files changed, 380 insertions, 38 deletions

diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 332dace6af34..bf5dc5f76824 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -16,6 +16,8 @@
 #include <linux/seq_file.h>
 #include <linux/irq.h>
 #include <linux/sched.h>
+#include <linux/syscore_ops.h>
+#include <asm/delay.h>
 #ifdef CONFIG_IPIPE
 #include <linux/ipipe.h>
 #endif
@@ -25,7 +27,11 @@
 #include <asm/irq_handler.h>
 #include <asm/dpmc.h>
 
-#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
+#ifndef CONFIG_BF60x
+# define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
+#else
+# define SIC_SYSIRQ(irq)        ((irq) - IVG15)
+#endif
 
 /*
  * NOTES:
@@ -50,6 +56,7 @@ unsigned long bfin_sic_iwr[3];	/* Up to 3 SIC_IWRx registers */
 unsigned vr_wakeup;
 #endif
 
+#ifndef CONFIG_BF60x
 static struct ivgx {
         /* irq number for request_irq, available in mach-bf5xx/irq.h */
         unsigned int irqno;
@@ -78,7 +85,8 @@ static void __init search_IAR(void)
 
                 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
                         int irqn;
-                        u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
+                        u32 iar =
+                                bfin_read32((unsigned long *)SIC_IAR0 +
 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
         defined(CONFIG_BF538) || defined(CONFIG_BF539)
                                 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
@@ -86,7 +94,6 @@ static void __init search_IAR(void)
                                 (irqN >> 3)
 #endif
                                 );
-
                         for (irqn = irqN; irqn < irqN + 4; ++irqn) {
                                 int iar_shift = (irqn & 7) * 4;
                                 if (ivg == (0xf & (iar >> iar_shift))) {
@@ -99,11 +106,11 @@ static void __init search_IAR(void)
                 }
         }
 }
+#endif
 
 /*
  * This is for core internal IRQs
  */
-
 void bfin_ack_noop(struct irq_data *d)
 {
         /* Dummy function.  */
@@ -136,21 +143,21 @@ static void bfin_core_unmask_irq(struct irq_data *d)
 void bfin_internal_mask_irq(unsigned int irq)
 {
         unsigned long flags = hard_local_irq_save();
-
+#ifndef CONFIG_BF60x
 #ifdef SIC_IMASK0
         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
-                             ~(1 << mask_bit));
-# ifdef CONFIG_SMP
+                        ~(1 << mask_bit));
+# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
-                             ~(1 << mask_bit));
+                        ~(1 << mask_bit));
 # endif
 #else
         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
-                             ~(1 << SIC_SYSIRQ(irq)));
+                        ~(1 << SIC_SYSIRQ(irq)));
+#endif /* end of SIC_IMASK0 */
 #endif
-
         hard_local_irq_restore(flags);
 }
 
@@ -160,7 +167,7 @@ static void bfin_internal_mask_irq_chip(struct irq_data *d)
 }
 
 #ifdef CONFIG_SMP
-static void bfin_internal_unmask_irq_affinity(unsigned int irq,
+void bfin_internal_unmask_irq_affinity(unsigned int irq,
                 const struct cpumask *affinity)
 #else
 void bfin_internal_unmask_irq(unsigned int irq)
@@ -168,6 +175,7 @@ void bfin_internal_unmask_irq(unsigned int irq)
 {
         unsigned long flags = hard_local_irq_save();
 
+#ifndef CONFIG_BF60x
 #ifdef SIC_IMASK0
         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
@@ -175,22 +183,239 @@ void bfin_internal_unmask_irq(unsigned int irq)
         if (cpumask_test_cpu(0, affinity))
 # endif
                 bfin_write_SIC_IMASK(mask_bank,
-                        bfin_read_SIC_IMASK(mask_bank) |
-                        (1 << mask_bit));
+                                bfin_read_SIC_IMASK(mask_bank) |
+                                (1 << mask_bit));
 # ifdef CONFIG_SMP
         if (cpumask_test_cpu(1, affinity))
                 bfin_write_SICB_IMASK(mask_bank,
-                        bfin_read_SICB_IMASK(mask_bank) |
-                        (1 << mask_bit));
+                                bfin_read_SICB_IMASK(mask_bank) |
+                                (1 << mask_bit));
 # endif
 #else
         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
-                             (1 << SIC_SYSIRQ(irq)));
+                        (1 << SIC_SYSIRQ(irq)));
+#endif
 #endif
+        hard_local_irq_restore(flags);
+}
+
+#ifdef CONFIG_BF60x
+static void bfin_sec_preflow_handler(struct irq_data *d)
+{
+        unsigned long flags = hard_local_irq_save();
+        unsigned int sid = SIC_SYSIRQ(d->irq);
+
+        bfin_write_SEC_SCI(0, SEC_CSID, sid);
+
+        hard_local_irq_restore(flags);
+}
+
+static void bfin_sec_mask_ack_irq(struct irq_data *d)
+{
+        unsigned long flags = hard_local_irq_save();
+        unsigned int sid = SIC_SYSIRQ(d->irq);
+
+        bfin_write_SEC_SCI(0, SEC_CSID, sid);
+
+        hard_local_irq_restore(flags);
+}
+
+static void bfin_sec_unmask_irq(struct irq_data *d)
+{
+        unsigned long flags = hard_local_irq_save();
+        unsigned int sid = SIC_SYSIRQ(d->irq);
+
+        bfin_write32(SEC_END, sid);
+
+        hard_local_irq_restore(flags);
+}
+
+static void bfin_sec_enable_ssi(unsigned int sid)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
+
+        reg_sctl |= SEC_SCTL_SRC_EN;
+        bfin_write_SEC_SCTL(sid, reg_sctl);
+
+        hard_local_irq_restore(flags);
+}
+
+static void bfin_sec_disable_ssi(unsigned int sid)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
+
+        reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
+        bfin_write_SEC_SCTL(sid, reg_sctl);
+
+        hard_local_irq_restore(flags);
+}
+
+static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
+
+        reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
+        bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
+
+        hard_local_irq_restore(flags);
+}
+
+static void bfin_sec_enable_sci(unsigned int sid)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
+
+        if (sid == SIC_SYSIRQ(IRQ_WATCH0))
+                reg_sctl |= SEC_SCTL_FAULT_EN;
+        else
+                reg_sctl |= SEC_SCTL_INT_EN;
+        bfin_write_SEC_SCTL(sid, reg_sctl);
+
+        hard_local_irq_restore(flags);
+}
+
+static void bfin_sec_disable_sci(unsigned int sid)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
+
+        reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
+        bfin_write_SEC_SCTL(sid, reg_sctl);
+
+        hard_local_irq_restore(flags);
+}
+
+static void bfin_sec_enable(struct irq_data *d)
+{
+        unsigned long flags = hard_local_irq_save();
+        unsigned int sid = SIC_SYSIRQ(d->irq);
+
+        bfin_sec_enable_sci(sid);
+        bfin_sec_enable_ssi(sid);
 
         hard_local_irq_restore(flags);
 }
 
+static void bfin_sec_disable(struct irq_data *d)
+{
+        unsigned long flags = hard_local_irq_save();
+        unsigned int sid = SIC_SYSIRQ(d->irq);
+
+        bfin_sec_disable_sci(sid);
+        bfin_sec_disable_ssi(sid);
+
+        hard_local_irq_restore(flags);
+}
+
+static void bfin_sec_raise_irq(unsigned int sid)
+{
+        unsigned long flags = hard_local_irq_save();
+
+        bfin_write32(SEC_RAISE, sid);
+
+        hard_local_irq_restore(flags);
+}
+
+static void init_software_driven_irq(void)
+{
+        bfin_sec_set_ssi_coreid(34, 0);
+        bfin_sec_set_ssi_coreid(35, 1);
+        bfin_sec_set_ssi_coreid(36, 0);
+        bfin_sec_set_ssi_coreid(37, 1);
+}
+
+void bfin_sec_resume(void)
+{
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
+        udelay(100);
+        bfin_write_SEC_GCTL(SEC_GCTL_EN);
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+}
+
+void handle_sec_sfi_fault(uint32_t gstat)
+{
+
+}
+
+void handle_sec_sci_fault(uint32_t gstat)
+{
+        uint32_t core_id;
+        uint32_t cstat;
+
+        core_id = gstat & SEC_GSTAT_SCI;
+        cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
+        if (cstat & SEC_CSTAT_ERR) {
+                switch (cstat & SEC_CSTAT_ERRC) {
+                case SEC_CSTAT_ACKERR:
+                        printk(KERN_DEBUG "sec ack err\n");
+                        break;
+                default:
+                        printk(KERN_DEBUG "sec sci unknow err\n");
+                }
+        }
+
+}
+
+void handle_sec_ssi_fault(uint32_t gstat)
+{
+        uint32_t sid;
+        uint32_t sstat;
+
+        sid = gstat & SEC_GSTAT_SID;
+        sstat = bfin_read_SEC_SSTAT(sid);
+
+}
+
+void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
+{
+        uint32_t sec_gstat;
+
+        raw_spin_lock(&desc->lock);
+
+        sec_gstat = bfin_read32(SEC_GSTAT);
+        if (sec_gstat & SEC_GSTAT_ERR) {
+
+                switch (sec_gstat & SEC_GSTAT_ERRC) {
+                case 0:
+                        handle_sec_sfi_fault(sec_gstat);
+                        break;
+                case SEC_GSTAT_SCIERR:
+                        handle_sec_sci_fault(sec_gstat);
+                        break;
+                case SEC_GSTAT_SSIERR:
+                        handle_sec_ssi_fault(sec_gstat);
+                        break;
+                }
+
+
+        }
+
+        raw_spin_unlock(&desc->lock);
+}
+
+static int sec_suspend(void)
+{
+        return 0;
+}
+
+static void sec_resume(void)
+{
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
+        udelay(100);
+        bfin_write_SEC_GCTL(SEC_GCTL_EN);
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+}
+
+static struct syscore_ops sec_pm_syscore_ops = {
+        .suspend = sec_suspend,
+        .resume = sec_resume,
+};
+
+#endif
+
 #ifdef CONFIG_SMP
 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 {
@@ -276,17 +501,14 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
 
 static struct irq_chip bfin_core_irqchip = {
         .name = "CORE",
-        .irq_ack = bfin_ack_noop,
         .irq_mask = bfin_core_mask_irq,
         .irq_unmask = bfin_core_unmask_irq,
 };
 
 static struct irq_chip bfin_internal_irqchip = {
         .name = "INTN",
-        .irq_ack = bfin_ack_noop,
         .irq_mask = bfin_internal_mask_irq_chip,
         .irq_unmask = bfin_internal_unmask_irq_chip,
-        .irq_mask_ack = bfin_internal_mask_irq_chip,
         .irq_disable = bfin_internal_mask_irq_chip,
         .irq_enable = bfin_internal_unmask_irq_chip,
 #ifdef CONFIG_SMP
@@ -295,6 +517,18 @@ static struct irq_chip bfin_internal_irqchip = {
         .irq_set_wake = bfin_internal_set_wake_chip,
 };
 
+#ifdef CONFIG_BF60x
+static struct irq_chip bfin_sec_irqchip = {
+        .name = "SEC",
+        .irq_mask_ack = bfin_sec_mask_ack_irq,
+        .irq_mask = bfin_sec_mask_ack_irq,
+        .irq_unmask = bfin_sec_unmask_irq,
+        .irq_eoi = bfin_sec_unmask_irq,
+        .irq_disable = bfin_sec_disable,
+        .irq_enable = bfin_sec_enable,
+};
+#endif
+
 void bfin_handle_irq(unsigned irq)
 {
 #ifdef CONFIG_IPIPE
@@ -396,8 +630,6 @@ int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
 
 static struct irq_chip bfin_mac_status_irqchip = {
         .name = "MACST",
-        .irq_ack = bfin_ack_noop,
-        .irq_mask_ack = bfin_mac_status_mask_irq,
         .irq_mask = bfin_mac_status_mask_irq,
         .irq_unmask = bfin_mac_status_unmask_irq,
         .irq_set_wake = bfin_mac_status_set_wake,
@@ -421,15 +653,15 @@ void bfin_demux_mac_status_irq(unsigned int int_err_irq,
                 } else {
                         bfin_mac_status_ack_irq(irq);
                         pr_debug("IRQ %d:"
-                                 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
-                                 irq);
+                                        " MASKED MAC ERROR INTERRUPT ASSERTED\n",
+                                        irq);
                 }
         } else
                 printk(KERN_ERR
-                       "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
-                       " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
-                       "(EMAC_SYSTAT=0x%X)\n",
-                       __func__, __FILE__, __LINE__, status);
+                                "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
+                                " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
+                                "(EMAC_SYSTAT=0x%X)\n",
+                                __func__, __FILE__, __LINE__, status);
 }
 #endif
 
@@ -583,7 +815,7 @@ static void bfin_demux_gpio_block(unsigned int irq)
 }
 
 void bfin_demux_gpio_irq(unsigned int inta_irq,
-                         struct irq_desc *desc)
+                        struct irq_desc *desc)
 {
         unsigned int irq;
 
@@ -635,9 +867,15 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
 
 #else
 
+# ifndef CONFIG_BF60x
 #define NR_PINT_SYS_IRQS        4
-#define NR_PINT_BITS            32
 #define NR_PINTS                160
+# else
+#define NR_PINT_SYS_IRQS        6
+#define NR_PINTS                112
+#endif
+
+#define NR_PINT_BITS            32
 #define IRQ_NOT_AVAIL           0xFF
 
 #define PINT_2_BANK(x)          ((x) >> 5)
@@ -652,8 +890,13 @@ static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
         (struct bfin_pint_regs *)PINT1_MASK_SET,
         (struct bfin_pint_regs *)PINT2_MASK_SET,
         (struct bfin_pint_regs *)PINT3_MASK_SET,
+#ifdef CONFIG_BF60x
+        (struct bfin_pint_regs *)PINT4_MASK_SET,
+        (struct bfin_pint_regs *)PINT5_MASK_SET,
+#endif
 };
 
+#ifndef CONFIG_BF60x
 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 {
         unsigned int irq_base;
@@ -666,6 +909,16 @@ inline unsigned int get_irq_base(u32 bank, u8 bmap)
 
         return irq_base;
 }
+#else
+inline unsigned int get_irq_base(u32 bank, u8 bmap)
+{
+        unsigned int irq_base;
+
+        irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
+
+        return irq_base;
+}
+#endif
 
         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 void init_pint_lut(void)
@@ -854,6 +1107,12 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
         case 1:
                 pint_irq = IRQ_PINT1;
                 break;
+        case 4:
+                pint_irq = IRQ_PINT4;
+                break;
+        case 5:
+                pint_irq = IRQ_PINT5;
+                break;
         default:
                 return -EINVAL;
         }
@@ -867,10 +1126,21 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 #endif
 
 void bfin_demux_gpio_irq(unsigned int inta_irq,
-                         struct irq_desc *desc)
+                        struct irq_desc *desc)
 {
         u32 bank, pint_val;
         u32 request, irq;
+        u32 level_mask;
+        int umask = 0;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+
+        if (chip->irq_mask_ack) {
+                chip->irq_mask_ack(&desc->irq_data);
+        } else {
+                chip->irq_mask(&desc->irq_data);
+                if (chip->irq_ack)
+                        chip->irq_ack(&desc->irq_data);
+        }
 
         switch (inta_irq) {
         case IRQ_PINT0:
@@ -885,6 +1155,14 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
         case IRQ_PINT1:
                 bank = 1;
                 break;
+#ifdef CONFIG_BF60x
+        case IRQ_PINT4:
+                bank = 4;
+                break;
+        case IRQ_PINT5:
+                bank = 5;
+                break;
+#endif
         default:
                 return;
         }
@@ -893,15 +1171,23 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
 
         request = pint[bank]->request;
 
+        level_mask = pint[bank]->edge_set & request;
+
         while (request) {
                 if (request & 1) {
                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
+                        if (level_mask & PINT_BIT(pint_val)) {
+                                umask = 1;
+                                chip->irq_unmask(&desc->irq_data);
+                        }
                         bfin_handle_irq(irq);
                 }
                 pint_val++;
                 request >>= 1;
         }
 
+        if (!umask)
+                chip->irq_unmask(&desc->irq_data);
 }
 #endif
 
@@ -951,6 +1237,7 @@ int __init init_arch_irq(void)
         int irq;
         unsigned long ilat = 0;
 
+#ifndef CONFIG_BF60x
         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
 #ifdef SIC_IMASK0
         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
@@ -958,13 +1245,16 @@ int __init init_arch_irq(void)
 # ifdef SIC_IMASK2
         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
 # endif
-# ifdef CONFIG_SMP
+# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
 # endif
 #else
         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 #endif
+#else /* CONFIG_BF60x */
+        bfin_write_SEC_GCTL(SEC_GCTL_RESET);
+#endif
 
         local_irq_disable();
 
@@ -974,6 +1264,10 @@ int __init init_arch_irq(void)
         pint[1]->assign = CONFIG_PINT1_ASSIGN;
         pint[2]->assign = CONFIG_PINT2_ASSIGN;
         pint[3]->assign = CONFIG_PINT3_ASSIGN;
+# ifdef CONFIG_BF60x
+        pint[4]->assign = CONFIG_PINT4_ASSIGN;
+        pint[5]->assign = CONFIG_PINT5_ASSIGN;
+# endif
 # endif
         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
         init_pint_lut();
@@ -986,6 +1280,7 @@ int __init init_arch_irq(void)
                         irq_set_chip(irq, &bfin_internal_irqchip);
 
                 switch (irq) {
+#ifndef CONFIG_BF60x
 #if BFIN_GPIO_PINT
                 case IRQ_PINT0:
                 case IRQ_PINT1:
@@ -1015,12 +1310,13 @@ int __init init_arch_irq(void)
                                                 bfin_demux_mac_status_irq);
                         break;
 #endif
-#ifdef CONFIG_SMP
+#if defined(CONFIG_SMP) || defined(CONFIG_ICC)
                 case IRQ_SUPPLE_0:
                 case IRQ_SUPPLE_1:
                         irq_set_handler(irq, handle_percpu_irq);
                         break;
 #endif
+#endif
 
 #ifdef CONFIG_TICKSOURCE_CORETMR
                 case IRQ_CORETMR:
@@ -1050,7 +1346,8 @@ int __init init_arch_irq(void)
 
         init_mach_irq();
 
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#ifndef CONFIG_BF60x
+#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) && !defined(CONFIG_BF60x)
         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
                 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
                                          handle_level_irq);
@@ -1060,7 +1357,28 @@ int __init init_arch_irq(void)
                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
                                          handle_level_irq);
-
+#else
+        for (irq = BFIN_IRQ(0); irq <= SYS_IRQS; irq++) {
+                if (irq < CORE_IRQS) {
+                        irq_set_chip(irq, &bfin_sec_irqchip);
+                        __irq_set_handler(irq, handle_sec_fault, 0, NULL);
+                } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
+                        irq_set_chip(irq, &bfin_sec_irqchip);
+                        irq_set_chained_handler(irq, bfin_demux_gpio_irq);
+                } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
+                        irq_set_chip(irq, &bfin_sec_irqchip);
+                        irq_set_handler(irq, handle_percpu_irq);
+                } else {
+                        irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
+                                        handle_fasteoi_irq);
+                        __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
+                }
+        }
+        for (irq = GPIO_IRQ_BASE;
+                irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
+                irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
+                                        handle_level_irq);
+#endif
         bfin_write_IMASK(0);
         CSYNC();
         ilat = bfin_read_ILAT();
@@ -1072,14 +1390,17 @@ int __init init_arch_irq(void)
         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
          * local_irq_enable()
          */
+#ifndef CONFIG_BF60x
         program_IAR();
         /* Therefore it's better to setup IARs before interrupts enabled */
         search_IAR();
 
         /* Enable interrupts IVG7-15 */
         bfin_irq_flags |= IMASK_IVG15 |
-            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
-            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
+                IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
+                IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
+
+        bfin_sti(bfin_irq_flags);
 
         /* This implicitly covers ANOMALY_05000171
          * Boot-ROM code modifies SICA_IWRx wakeup registers
@@ -1103,7 +1424,23 @@ int __init init_arch_irq(void)
 #else
         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
+#else  /* CONFIG_BF60x */
+        /* Enable interrupts IVG7-15 */
+        bfin_irq_flags |= IMASK_IVG15 |
+            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
+            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 
+
+        bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
+        bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
+        bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
+        udelay(100);
+        bfin_write_SEC_GCTL(SEC_GCTL_EN);
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+        init_software_driven_irq();
+        register_syscore_ops(&sec_pm_syscore_ops);
+#endif
         return 0;
 }
 
@@ -1112,13 +1449,14 @@ __attribute__((l1_text))
 #endif
 static int vec_to_irq(int vec)
 {
+#ifndef CONFIG_BF60x
         struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
         struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
         unsigned long sic_status[3];
-
+#endif
         if (likely(vec == EVT_IVTMR_P))
                 return IRQ_CORETMR;
-
+#ifndef CONFIG_BF60x
 #ifdef SIC_ISR
         sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
 #else
@@ -1147,6 +1485,10 @@ static int vec_to_irq(int vec)
 #endif
                         return ivg->irqno;
         }
+#else
+        /* for bf60x read */
+        return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
+#endif  /* end of CONFIG_BF60x */
 }
 
 #ifdef CONFIG_DO_IRQ_L1