Merge git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-irqflags

* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-irqflags:
  Fix IRQ flag handling naming
  MIPS: Add missing #inclusions of <linux/irq.h>
  smc91x: Add missing #inclusion of <linux/irq.h>
  Drop a couple of unnecessary asm/system.h inclusions
  SH: Add missing consts to sys_execve() declaration
  Blackfin: Rename IRQ flags handling functions
  Blackfin: Add missing dep to asm/irqflags.h
  Blackfin: Rename DES PC2() symbol to avoid collision
  Blackfin: Split the BF532 BFIN_*_FIO_FLAG() functions to their own header
  Blackfin: Split PLL code from mach-specific cdef headers

1 files changed, 57 insertions, 0 deletions

diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
new file mode 100644
index 000000000000..169c106d0edb
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/pll.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_PLL_H
+#define _MACH_PLL_H
+
+#include <asm/blackfin.h>
+#include <asm/irqflags.h>
+
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+        unsigned long flags, iwr;
+
+        if (val == bfin_read_PLL_CTL())
+                return;
+
+        flags = hard_local_irq_save();
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr = bfin_read32(SIC_IWR);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+        bfin_write16(PLL_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR, iwr);
+        hard_local_irq_restore(flags);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr;
+
+        if (val == bfin_read_VR_CTL())
+                return;
+
+        flags = hard_local_irq_save();
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr = bfin_read32(SIC_IWR);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+        bfin_write16(VR_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR, iwr);
+        hard_local_irq_restore(flags);
+}
+
+#endif /* _MACH_PLL_H */