diff options
author | Magnus Damm <damm@opensource.se> | 2011-10-12 03:21:26 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2011-11-04 12:01:50 -0400 |
commit | e1b3aa85b2887c06f59c9d38aa3653f797a867cb (patch) | |
tree | 1cf2ea1c5aee4f01d914a50d4eb63932e926efaa /arch/arm | |
parent | e753068093c4c4da80771bd5ee53a6a782dee7b6 (diff) |
ARM: mach-shmobile: Use common INTC IRQ code on sh7377
Make use of INTC_IRQ_PINS_32() for INTCA on sh7377.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-shmobile/intc-sh7377.c | 67 |
1 files changed, 6 insertions, 61 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c index fe45154ce660..2af4e6e9bc5b 100644 --- a/arch/arm/mach-shmobile/intc-sh7377.c +++ b/arch/arm/mach-shmobile/intc-sh7377.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/irq.h> | 22 | #include <linux/irq.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/sh_intc.h> | 24 | #include <linux/sh_intc.h> |
25 | #include <mach/intc.h> | ||
25 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
26 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
27 | 28 | ||
@@ -31,10 +32,6 @@ enum { | |||
31 | DISABLED, | 32 | DISABLED, |
32 | 33 | ||
33 | /* interrupt sources INTCA */ | 34 | /* interrupt sources INTCA */ |
34 | IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, | ||
35 | IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, | ||
36 | IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A, | ||
37 | IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A, | ||
38 | DIRC, | 35 | DIRC, |
39 | _2DG, | 36 | _2DG, |
40 | CRYPT_STD, | 37 | CRYPT_STD, |
@@ -91,22 +88,6 @@ enum { | |||
91 | }; | 88 | }; |
92 | 89 | ||
93 | static struct intc_vect intca_vectors[] __initdata = { | 90 | static struct intc_vect intca_vectors[] __initdata = { |
94 | INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), | ||
95 | INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), | ||
96 | INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), | ||
97 | INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), | ||
98 | INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), | ||
99 | INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), | ||
100 | INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), | ||
101 | INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), | ||
102 | INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220), | ||
103 | INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260), | ||
104 | INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0), | ||
105 | INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0), | ||
106 | INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320), | ||
107 | INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360), | ||
108 | INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0), | ||
109 | INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0), | ||
110 | INTC_VECT(DIRC, 0x0560), | 91 | INTC_VECT(DIRC, 0x0560), |
111 | INTC_VECT(_2DG, 0x05e0), | 92 | INTC_VECT(_2DG, 0x05e0), |
112 | INTC_VECT(CRYPT_STD, 0x0700), | 93 | INTC_VECT(CRYPT_STD, 0x0700), |
@@ -203,15 +184,6 @@ static struct intc_group intca_groups[] __initdata = { | |||
203 | }; | 184 | }; |
204 | 185 | ||
205 | static struct intc_mask_reg intca_mask_registers[] __initdata = { | 186 | static struct intc_mask_reg intca_mask_registers[] __initdata = { |
206 | { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ | ||
207 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, | ||
208 | { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ | ||
209 | { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, | ||
210 | { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */ | ||
211 | { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, | ||
212 | { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */ | ||
213 | { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, | ||
214 | |||
215 | { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ | 187 | { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ |
216 | { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, | 188 | { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, |
217 | AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, | 189 | AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, |
@@ -273,15 +245,6 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = { | |||
273 | }; | 245 | }; |
274 | 246 | ||
275 | static struct intc_prio_reg intca_prio_registers[] __initdata = { | 247 | static struct intc_prio_reg intca_prio_registers[] __initdata = { |
276 | { 0xe6900010, 0, 32, 4, /* INTPRI00A */ | ||
277 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, | ||
278 | { 0xe6900014, 0, 32, 4, /* INTPRI10A */ | ||
279 | { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, | ||
280 | { 0xe6900018, 0, 32, 4, /* INTPRI10A */ | ||
281 | { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, | ||
282 | { 0xe690001c, 0, 32, 4, /* INTPRI30A */ | ||
283 | { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, | ||
284 | |||
285 | { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, | 248 | { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, |
286 | { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, | 249 | { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, |
287 | { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD, | 250 | { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD, |
@@ -315,37 +278,18 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = { | |||
315 | { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, | 278 | { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, |
316 | }; | 279 | }; |
317 | 280 | ||
318 | static struct intc_sense_reg intca_sense_registers[] __initdata = { | ||
319 | { 0xe6900000, 16, 2, /* ICR1A */ | ||
320 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, | ||
321 | { 0xe6900004, 16, 2, /* ICR2A */ | ||
322 | { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, | ||
323 | { 0xe6900008, 16, 2, /* ICR3A */ | ||
324 | { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, | ||
325 | { 0xe690000c, 16, 2, /* ICR4A */ | ||
326 | { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, | ||
327 | }; | ||
328 | |||
329 | static struct intc_mask_reg intca_ack_registers[] __initdata = { | ||
330 | { 0xe6900020, 0, 8, /* INTREQ00A */ | ||
331 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, | ||
332 | { 0xe6900024, 0, 8, /* INTREQ10A */ | ||
333 | { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, | ||
334 | { 0xe6900028, 0, 8, /* INTREQ20A */ | ||
335 | { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, | ||
336 | { 0xe690002c, 0, 8, /* INTREQ30A */ | ||
337 | { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, | ||
338 | }; | ||
339 | |||
340 | static struct intc_desc intca_desc __initdata = { | 281 | static struct intc_desc intca_desc __initdata = { |
341 | .name = "sh7377-intca", | 282 | .name = "sh7377-intca", |
342 | .force_enable = ENABLED, | 283 | .force_enable = ENABLED, |
343 | .force_disable = DISABLED, | 284 | .force_disable = DISABLED, |
344 | .hw = INTC_HW_DESC(intca_vectors, intca_groups, | 285 | .hw = INTC_HW_DESC(intca_vectors, intca_groups, |
345 | intca_mask_registers, intca_prio_registers, | 286 | intca_mask_registers, intca_prio_registers, |
346 | intca_sense_registers, intca_ack_registers), | 287 | NULL, NULL), |
347 | }; | 288 | }; |
348 | 289 | ||
290 | INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, | ||
291 | INTC_VECT, "sh7377-intca-irq-pins"); | ||
292 | |||
349 | /* this macro ignore entry which is also in INTCA */ | 293 | /* this macro ignore entry which is also in INTCA */ |
350 | #define __IGNORE(a...) | 294 | #define __IGNORE(a...) |
351 | #define __IGNORE0(a...) 0 | 295 | #define __IGNORE0(a...) 0 |
@@ -638,6 +582,7 @@ void __init sh7377_init_irq(void) | |||
638 | void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE); | 582 | void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE); |
639 | 583 | ||
640 | register_intc_controller(&intca_desc); | 584 | register_intc_controller(&intca_desc); |
585 | register_intc_controller(&intca_irq_pins_desc); | ||
641 | register_intc_controller(&intcs_desc); | 586 | register_intc_controller(&intcs_desc); |
642 | 587 | ||
643 | /* demux using INTEVTSA */ | 588 | /* demux using INTEVTSA */ |