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authorArnd Bergmann <arnd@arndb.de>2012-05-14 11:31:45 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-14 11:31:45 -0400
commit66a2886d867343eff6bf2646bea2c923d0cbf620 (patch)
treead44dcca4fa410ab2c16b4964f6c19571421b4df /arch/arm
parentd2819f80d465672b09c2f4cb52303b7f951c4d0f (diff)
parentf613e220aebfafb653f7ce264950c15c99e27f2a (diff)
Merge branch 'spear/dt' into spear/clock
Conflicts: arch/arm/mach-spear3xx/clock.c arch/arm/mach-spear3xx/include/mach/generic.h arch/arm/mach-spear3xx/include/mach/misc_regs.h arch/arm/mach-spear3xx/spear320.c arch/arm/mach-spear6xx/clock.c arch/arm/mach-spear6xx/include/mach/misc_regs.h Resolve even more merge conflicts. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/spear300-evb.dts187
-rw-r--r--arch/arm/boot/dts/spear310-evb.dts20
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts25
-rw-r--r--arch/arm/boot/dts/spear3xx.dtsi6
-rw-r--r--arch/arm/boot/dts/spear600-evb.dts29
-rw-r--r--arch/arm/boot/dts/spear600.dtsi6
-rw-r--r--arch/arm/configs/spear3xx_defconfig4
-rw-r--r--arch/arm/configs/spear6xx_defconfig5
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h11
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h21
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h131
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h2
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h37
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h54
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h58
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h67
-rw-r--r--arch/arm/mach-spear3xx/spear300.c42
-rw-r--r--arch/arm/mach-spear3xx/spear310.c63
-rw-r--r--arch/arm/mach-spear3xx/spear320.c71
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c4
-rw-r--r--arch/arm/mach-spear6xx/include/mach/generic.h29
-rw-r--r--arch/arm/mach-spear6xx/include/mach/hardware.h24
-rw-r--r--arch/arm/mach-spear6xx/include/mach/irqs.h76
-rw-r--r--arch/arm/mach-spear6xx/include/mach/misc_regs.h2
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear.h56
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear600.h21
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c49
-rw-r--r--arch/arm/plat-spear/include/plat/debug-macro.S2
-rw-r--r--arch/arm/plat-spear/include/plat/hardware.h17
-rw-r--r--arch/arm/plat-spear/include/plat/uncompress.h2
-rw-r--r--arch/arm/plat-spear/pl080.c1
-rw-r--r--arch/arm/plat-spear/restart.c2
-rw-r--r--arch/arm/plat-spear/time.c40
33 files changed, 443 insertions, 721 deletions
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index 402ca0d55011..fc82b1a26458 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -87,6 +87,31 @@
87 87
88 smi: flash@fc000000 { 88 smi: flash@fc000000 {
89 status = "okay"; 89 status = "okay";
90 clock-rate=<50000000>;
91
92 flash@f8000000 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 reg = <0xf8000000 0x800000>;
96 st,smi-fast-mode;
97
98 partition@0 {
99 label = "xloader";
100 reg = <0x0 0x10000>;
101 };
102 partition@10000 {
103 label = "u-boot";
104 reg = <0x10000 0x40000>;
105 };
106 partition@50000 {
107 label = "linux";
108 reg = <0x50000 0x2c0000>;
109 };
110 partition@310000 {
111 label = "rootfs";
112 reg = <0x310000 0x4f0000>;
113 };
114 };
90 }; 115 };
91 116
92 spi0: spi@d0100000 { 117 spi0: spi@d0100000 {
@@ -119,87 +144,87 @@
119 }; 144 };
120 145
121 kbd@a0000000 { 146 kbd@a0000000 {
122 linux,keymap = < 0x00010000 147 linux,keymap = < 0x00000001
123 0x00020100 148 0x00010002
124 0x00030200 149 0x00020003
125 0x00040300 150 0x00030004
126 0x00050400 151 0x00040005
127 0x00060500 152 0x00050006
128 0x00070600 153 0x00060007
129 0x00080700 154 0x00070008
130 0x00090800 155 0x00080009
131 0x000a0001 156 0x0100000a
132 0x000c0101 157 0x0101000c
133 0x000d0201 158 0x0102000d
134 0x000e0301 159 0x0103000e
135 0x000f0401 160 0x0104000f
136 0x00100501 161 0x01050010
137 0x00110601 162 0x01060011
138 0x00120701 163 0x01070012
139 0x00130801 164 0x01080013
140 0x00140002 165 0x02000014
141 0x00150102 166 0x02010015
142 0x00160202 167 0x02020016
143 0x00170302 168 0x02030017
144 0x00180402 169 0x02040018
145 0x00190502 170 0x02050019
146 0x001a0602 171 0x0206001a
147 0x001b0702 172 0x0207001b
148 0x001c0802 173 0x0208001c
149 0x001d0003 174 0x0300001d
150 0x001e0103 175 0x0301001e
151 0x001f0203 176 0x0302001f
152 0x00200303 177 0x03030020
153 0x00210403 178 0x03040021
154 0x00220503 179 0x03050022
155 0x00230603 180 0x03060023
156 0x00240703 181 0x03070024
157 0x00250803 182 0x03080025
158 0x00260004 183 0x04000026
159 0x00270104 184 0x04010027
160 0x00280204 185 0x04020028
161 0x00290304 186 0x04030029
162 0x002a0404 187 0x0404002a
163 0x002b0504 188 0x0405002b
164 0x002c0604 189 0x0406002c
165 0x002d0704 190 0x0407002d
166 0x002e0804 191 0x0408002e
167 0x002f0005 192 0x0500002f
168 0x00300105 193 0x05010030
169 0x00310205 194 0x05020031
170 0x00320305 195 0x05030032
171 0x00330405 196 0x05040033
172 0x00340505 197 0x05050034
173 0x00350605 198 0x05060035
174 0x00360705 199 0x05070036
175 0x00370805 200 0x05080037
176 0x00380006 201 0x06000038
177 0x00390106 202 0x06010039
178 0x003a0206 203 0x0602003a
179 0x003b0306 204 0x0603003b
180 0x003c0406 205 0x0604003c
181 0x003d0506 206 0x0605003d
182 0x003e0606 207 0x0606003e
183 0x003f0706 208 0x0607003f
184 0x00400806 209 0x06080040
185 0x00410007 210 0x07000041
186 0x00420107 211 0x07010042
187 0x00430207 212 0x07020043
188 0x00440307 213 0x07030044
189 0x00450407 214 0x07040045
190 0x00460507 215 0x07050046
191 0x00470607 216 0x07060047
192 0x00480707 217 0x07070048
193 0x00490807 218 0x07080049
194 0x004a0008 219 0x0800004a
195 0x004b0108 220 0x0801004b
196 0x004c0208 221 0x0802004c
197 0x004d0308 222 0x0803004d
198 0x004e0408 223 0x0804004e
199 0x004f0508 224 0x0805004f
200 0x00500608 225 0x08060050
201 0x00510708 226 0x08070051
202 0x00520808 >; 227 0x08080052 >;
203 autorepeat; 228 autorepeat;
204 st,mode = <0>; 229 st,mode = <0>;
205 status = "okay"; 230 status = "okay";
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index 6d95317100ad..dc5e2d445a93 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -103,11 +103,27 @@
103 clock-rate=<50000000>; 103 clock-rate=<50000000>;
104 104
105 flash@f8000000 { 105 flash@f8000000 {
106 label = "m25p64";
107 reg = <0xf8000000 0x800000>;
108 #address-cells = <1>; 106 #address-cells = <1>;
109 #size-cells = <1>; 107 #size-cells = <1>;
108 reg = <0xf8000000 0x800000>;
110 st,smi-fast-mode; 109 st,smi-fast-mode;
110
111 partition@0 {
112 label = "xloader";
113 reg = <0x0 0x10000>;
114 };
115 partition@10000 {
116 label = "u-boot";
117 reg = <0x10000 0x40000>;
118 };
119 partition@50000 {
120 label = "linux";
121 reg = <0x50000 0x2c0000>;
122 };
123 partition@310000 {
124 label = "rootfs";
125 reg = <0x310000 0x4f0000>;
126 };
111 }; 127 };
112 }; 128 };
113 129
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index 0c6463b71a37..6308fa3bec1e 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -110,6 +110,31 @@
110 110
111 smi: flash@fc000000 { 111 smi: flash@fc000000 {
112 status = "okay"; 112 status = "okay";
113 clock-rate=<50000000>;
114
115 flash@f8000000 {
116 #address-cells = <1>;
117 #size-cells = <1>;
118 reg = <0xf8000000 0x800000>;
119 st,smi-fast-mode;
120
121 partition@0 {
122 label = "xloader";
123 reg = <0x0 0x10000>;
124 };
125 partition@10000 {
126 label = "u-boot";
127 reg = <0x10000 0x40000>;
128 };
129 partition@50000 {
130 label = "linux";
131 reg = <0x50000 0x2c0000>;
132 };
133 partition@310000 {
134 label = "rootfs";
135 reg = <0x310000 0x4f0000>;
136 };
137 };
113 }; 138 };
114 139
115 spi0: spi@d0100000 { 140 spi0: spi@d0100000 {
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index 0ae7c8e86311..91072553963f 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -139,6 +139,12 @@
139 interrupts = <12>; 139 interrupts = <12>;
140 status = "disabled"; 140 status = "disabled";
141 }; 141 };
142
143 timer@f0000000 {
144 compatible = "st,spear-timer";
145 reg = <0xf0000000 0x400>;
146 interrupts = <2>;
147 };
142 }; 148 };
143 }; 149 };
144}; 150};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 790a7a8a5ccd..1119c22c9a82 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -33,6 +33,35 @@
33 status = "okay"; 33 status = "okay";
34 }; 34 };
35 35
36 smi: flash@fc000000 {
37 status = "okay";
38 clock-rate=<50000000>;
39
40 flash@f8000000 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 reg = <0xf8000000 0x800000>;
44 st,smi-fast-mode;
45
46 partition@0 {
47 label = "xloader";
48 reg = <0x0 0x10000>;
49 };
50 partition@10000 {
51 label = "u-boot";
52 reg = <0x10000 0x40000>;
53 };
54 partition@50000 {
55 label = "linux";
56 reg = <0x50000 0x2c0000>;
57 };
58 partition@310000 {
59 label = "rootfs";
60 reg = <0x310000 0x4f0000>;
61 };
62 };
63 };
64
36 apb { 65 apb {
37 serial@d0000000 { 66 serial@d0000000 {
38 status = "okay"; 67 status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index d777e3a6f178..089f0a42c50e 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -177,6 +177,12 @@
177 interrupts = <28>; 177 interrupts = <28>;
178 status = "disabled"; 178 status = "disabled";
179 }; 179 };
180
181 timer@f0000000 {
182 compatible = "st,spear-timer";
183 reg = <0xf0000000 0x400>;
184 interrupts = <16>;
185 };
180 }; 186 };
181 }; 187 };
182}; 188};
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index 7ed42912d69a..865980c5f212 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -14,6 +14,9 @@ CONFIG_BINFMT_MISC=y
14CONFIG_NET=y 14CONFIG_NET=y
15CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 15CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
16CONFIG_MTD=y 16CONFIG_MTD=y
17CONFIG_MTD_OF_PARTS=y
18CONFIG_MTD_CHAR=y
19CONFIG_MTD_BLOCK=y
17CONFIG_MTD_NAND=y 20CONFIG_MTD_NAND=y
18CONFIG_MTD_NAND_FSMC=y 21CONFIG_MTD_NAND_FSMC=y
19CONFIG_BLK_DEV_RAM=y 22CONFIG_BLK_DEV_RAM=y
@@ -73,6 +76,7 @@ CONFIG_MSDOS_FS=m
73CONFIG_VFAT_FS=m 76CONFIG_VFAT_FS=m
74CONFIG_FAT_DEFAULT_IOCHARSET="ascii" 77CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
75CONFIG_TMPFS=y 78CONFIG_TMPFS=y
79CONFIG_JFFS2_FS=y
76CONFIG_NLS_DEFAULT="utf8" 80CONFIG_NLS_DEFAULT="utf8"
77CONFIG_NLS_CODEPAGE_437=y 81CONFIG_NLS_CODEPAGE_437=y
78CONFIG_NLS_ASCII=m 82CONFIG_NLS_ASCII=m
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cf94bc73a0e0..a2a1265f86b6 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -8,11 +8,13 @@ CONFIG_MODVERSIONS=y
8CONFIG_PARTITION_ADVANCED=y 8CONFIG_PARTITION_ADVANCED=y
9CONFIG_PLAT_SPEAR=y 9CONFIG_PLAT_SPEAR=y
10CONFIG_ARCH_SPEAR6XX=y 10CONFIG_ARCH_SPEAR6XX=y
11CONFIG_BOARD_SPEAR600_DT=y
12CONFIG_BINFMT_MISC=y 11CONFIG_BINFMT_MISC=y
13CONFIG_NET=y 12CONFIG_NET=y
14CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 13CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
15CONFIG_MTD=y 14CONFIG_MTD=y
15CONFIG_MTD_OF_PARTS=y
16CONFIG_MTD_CHAR=y
17CONFIG_MTD_BLOCK=y
16CONFIG_MTD_NAND=y 18CONFIG_MTD_NAND=y
17CONFIG_MTD_NAND_FSMC=y 19CONFIG_MTD_NAND_FSMC=y
18CONFIG_BLK_DEV_RAM=y 20CONFIG_BLK_DEV_RAM=y
@@ -64,6 +66,7 @@ CONFIG_MSDOS_FS=m
64CONFIG_VFAT_FS=m 66CONFIG_VFAT_FS=m
65CONFIG_FAT_DEFAULT_IOCHARSET="ascii" 67CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
66CONFIG_TMPFS=y 68CONFIG_TMPFS=y
69CONFIG_JFFS2_FS=y
67CONFIG_NLS_DEFAULT="utf8" 70CONFIG_NLS_DEFAULT="utf8"
68CONFIG_NLS_CODEPAGE_437=y 71CONFIG_NLS_CODEPAGE_437=y
69CONFIG_NLS_ASCII=m 72CONFIG_NLS_ASCII=m
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index c10eac6c10cb..4a95b9453c2a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -21,22 +21,13 @@
21#include <asm/mach/time.h> 21#include <asm/mach/time.h>
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23 23
24/* spear3xx declarations */
25/*
26 * Each GPT has 2 timer channels
27 * Following GPT channels will be used as clock source and clockevent
28 */
29#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
30#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
32
33/* Add spear3xx family device structure declarations here */ 24/* Add spear3xx family device structure declarations here */
34extern struct sys_timer spear3xx_timer; 25extern struct sys_timer spear3xx_timer;
35extern struct pl022_ssp_controller pl022_plat_data; 26extern struct pl022_ssp_controller pl022_plat_data;
36extern struct pl08x_platform_data pl080_plat_data; 27extern struct pl08x_platform_data pl080_plat_data;
37 28
38/* Add spear3xx family function declarations here */ 29/* Add spear3xx family function declarations here */
39void __init spear_setup_timer(void); 30void __init spear_setup_of_timer(void);
40void __init spear3xx_clk_init(void); 31void __init spear3xx_clk_init(void);
41void __init spear3xx_map_io(void); 32void __init spear3xx_map_io(void);
42void __init spear3xx_dt_init_irq(void); 33void __init spear3xx_dt_init_irq(void);
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index defa374f5bee..40a8c178f10d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,20 +1 @@
1/* /* empty */
2 * arch/arm/mach-spear3xx/include/mach/hardware.h
3 *
4 * Hardware definitions for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H
16
17#include <plat/hardware.h>
18#include <mach/spear.h>
19
20#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e265442808e..51bd62a0254c 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,14 @@
14#ifndef __MACH_IRQS_H 14#ifndef __MACH_IRQS_H
15#define __MACH_IRQS_H 15#define __MACH_IRQS_H
16 16
17/* SPEAr3xx IRQ definitions */ 17/* FIXME: probe all these from DT */
18#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
19#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 18#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
20#define SPEAR3XX_IRQ_CPU_GPT1_1 2
21#define SPEAR3XX_IRQ_CPU_GPT1_2 3
22#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
23#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
24#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
25#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
26#define SPEAR3XX_IRQ_BASIC_DMA 8
27#define SPEAR3XX_IRQ_BASIC_SMI 9
28#define SPEAR3XX_IRQ_BASIC_RTC 10
29#define SPEAR3XX_IRQ_BASIC_GPIO 11
30#define SPEAR3XX_IRQ_BASIC_WDT 12
31#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
32#define SPEAR3XX_IRQ_SYS_ERROR 14
33#define SPEAR3XX_IRQ_WAKEUP_RCV 15
34#define SPEAR3XX_IRQ_JPEG 16
35#define SPEAR3XX_IRQ_IRDA 17
36#define SPEAR3XX_IRQ_ADC 18
37#define SPEAR3XX_IRQ_UART 19
38#define SPEAR3XX_IRQ_SSP 20
39#define SPEAR3XX_IRQ_I2C 21
40#define SPEAR3XX_IRQ_MAC_1 22
41#define SPEAR3XX_IRQ_MAC_2 23
42#define SPEAR3XX_IRQ_USB_DEV 24
43#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
44#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
45#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
46#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
47#define SPEAR3XX_IRQ_GEN_RAS_1 28 19#define SPEAR3XX_IRQ_GEN_RAS_1 28
48#define SPEAR3XX_IRQ_GEN_RAS_2 29 20#define SPEAR3XX_IRQ_GEN_RAS_2 29
49#define SPEAR3XX_IRQ_GEN_RAS_3 30 21#define SPEAR3XX_IRQ_GEN_RAS_3 30
50#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
51#define SPEAR3XX_IRQ_VIC_END 32 22#define SPEAR3XX_IRQ_VIC_END 32
52
53#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END 23#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
54 24
55/* SPEAr300 Virtual irq definitions */ 25#define NR_IRQS 160
56/* IRQs sharing IRQ_GEN_RAS_1 */
57#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
58#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
59#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
60#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
61#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
62#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
63#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
64#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
65#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
66
67/* IRQs sharing IRQ_GEN_RAS_3 */
68#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
69
70/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
71#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
72
73/* SPEAr310 Virtual irq definitions */
74/* IRQs sharing IRQ_GEN_RAS_1 */
75#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
76#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
77#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
78#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
79#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
80#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
81#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
82#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
83
84/* IRQs sharing IRQ_GEN_RAS_2 */
85#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
86#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
87#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
88#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
89#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
90
91/* IRQs sharing IRQ_GEN_RAS_3 */
92#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
93#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
94
95/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
96#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
97#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
98#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
99
100/* SPEAr320 Virtual irq definitions */
101/* IRQs sharing IRQ_GEN_RAS_1 */
102#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
103#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
104#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
105
106/* IRQs sharing IRQ_GEN_RAS_2 */
107#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
108
109/* IRQs sharing IRQ_GEN_RAS_3 */
110#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
111#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
112#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
113
114/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
115#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
116#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
117#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
118#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
119#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
120#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
121#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
122#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
123#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
124#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
125#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
126
127/*
128 * GPIO pins virtual irqs
129 * Use the lowest number for the GPIO virtual IRQs base on which subarchs
130 * we have compiled in
131 */
132#if defined(CONFIG_MACH_SPEAR310)
133#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
134#elif defined(CONFIG_MACH_SPEAR320)
135#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
136#else
137#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
138#endif
139
140#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
141#define SPEAR3XX_PLGPIO_COUNT 102
142
143#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
144#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
145#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
146 SPEAR3XX_PLGPIO_COUNT)
147#else
148#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
149#endif
150
151#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
152#define NR_IRQS SPEAR3XX_VIRQ_END
153 26
154#endif /* __MACH_IRQS_H */ 27#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 50cfe0d1a7c4..18e2ac576f25 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,9 +14,9 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h>
18#include <mach/spear.h> 17#include <mach/spear.h>
19 18
20#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
21 21
22#endif /* __MACH_MISC_REGS_H */ 22#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index e7bc8bab83fe..51eb953148a9 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,61 +15,26 @@
15#define __MACH_SPEAR3XX_H 15#define __MACH_SPEAR3XX_H
16 16
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <mach/spear300.h>
19#include <mach/spear310.h>
20#include <mach/spear320.h>
21
22#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
23
24#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
25 18
26/* ICM1 - Low speed connection */ 19/* ICM1 - Low speed connection */
27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) 20#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
28#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) 21#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
29#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) 22#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
30#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) 23#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
31#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
32#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) 24#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
33#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
34#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
35#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
36#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
37
38/* ICM2 - Application Subsystem */
39#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
40#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
41
42/* ICM4 - High Speed Connection */
43#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
44#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
45#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
46#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
47#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
48#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
49#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
50#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
51#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
52 25
53/* ML1 - Multi Layer CPU Subsystem */ 26/* ML1 - Multi Layer CPU Subsystem */
54#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) 27#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
55#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) 28#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
56#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
57 29
58/* ICM3 - Basic Subsystem */ 30/* ICM3 - Basic Subsystem */
59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 31#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 32#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
62#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) 33#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
63#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
64#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
65#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
66#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
67#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
68#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 34#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
69#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) 35#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
70#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 36#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
71#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) 37#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
72#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
73 38
74/* Debug uart for linux, will be used for debug and uncompress messages */ 39/* Debug uart for linux, will be used for debug and uncompress messages */
75#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE 40#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644
index 3b6ea0729040..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear300.h
3 *
4 * SPEAr300 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR300
15
16#ifndef __MACH_SPEAR300_H
17#define __MACH_SPEAR300_H
18
19/* Base address of various IPs */
20#define SPEAR300_TELECOM_BASE UL(0x50000000)
21
22/* Interrupt registers offsets and masks */
23#define SPEAR300_INT_ENB_MASK_REG 0x54
24#define SPEAR300_INT_STS_MASK_REG 0x58
25#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
26#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
27#define SPEAR300_I2S_IRQ_MASK (1 << 2)
28#define SPEAR300_TDM_IRQ_MASK (1 << 3)
29#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
30#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
31#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
32#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
33#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
34
35#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
36
37#define SPEAR300_CLCD_BASE UL(0x60000000)
38#define SPEAR300_SDHCI_BASE UL(0x70000000)
39#define SPEAR300_NAND_0_BASE UL(0x80000000)
40#define SPEAR300_NAND_1_BASE UL(0x84000000)
41#define SPEAR300_NAND_2_BASE UL(0x88000000)
42#define SPEAR300_NAND_3_BASE UL(0x8c000000)
43#define SPEAR300_NOR_0_BASE UL(0x90000000)
44#define SPEAR300_NOR_1_BASE UL(0x91000000)
45#define SPEAR300_NOR_2_BASE UL(0x92000000)
46#define SPEAR300_NOR_3_BASE UL(0x93000000)
47#define SPEAR300_FSMC_BASE UL(0x94000000)
48#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
49#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
50#define SPEAR300_GPIO_BASE UL(0xA9000000)
51
52#endif /* __MACH_SPEAR300_H */
53
54#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644
index 1567d0da725f..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear310.h
3 *
4 * SPEAr310 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR310
15
16#ifndef __MACH_SPEAR310_H
17#define __MACH_SPEAR310_H
18
19#define SPEAR310_NAND_BASE UL(0x40000000)
20#define SPEAR310_FSMC_BASE UL(0x44000000)
21#define SPEAR310_UART1_BASE UL(0xB2000000)
22#define SPEAR310_UART2_BASE UL(0xB2080000)
23#define SPEAR310_UART3_BASE UL(0xB2100000)
24#define SPEAR310_UART4_BASE UL(0xB2180000)
25#define SPEAR310_UART5_BASE UL(0xB2200000)
26#define SPEAR310_HDLC_BASE UL(0xB2800000)
27#define SPEAR310_RS485_0_BASE UL(0xB3000000)
28#define SPEAR310_RS485_1_BASE UL(0xB3800000)
29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30
31/* Interrupt registers offsets and masks */
32#define SPEAR310_INT_STS_MASK_REG 0x04
33#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
34#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
35#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
36#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
37#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
38#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
39#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
40#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
41#define SPEAR310_UART1_IRQ_MASK (1 << 8)
42#define SPEAR310_UART2_IRQ_MASK (1 << 9)
43#define SPEAR310_UART3_IRQ_MASK (1 << 10)
44#define SPEAR310_UART4_IRQ_MASK (1 << 11)
45#define SPEAR310_UART5_IRQ_MASK (1 << 12)
46#define SPEAR310_EMI_IRQ_MASK (1 << 13)
47#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
48#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
49#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
50
51#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
52#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
53#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
54#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
55
56#endif /* __MACH_SPEAR310_H */
57
58#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644
index 8cfa83fa1296..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear320.h
3 *
4 * SPEAr320 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR320
15
16#ifndef __MACH_SPEAR320_H
17#define __MACH_SPEAR320_H
18
19#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
20#define SPEAR320_FSMC_BASE UL(0x4C000000)
21#define SPEAR320_NAND_BASE UL(0x50000000)
22#define SPEAR320_I2S_BASE UL(0x60000000)
23#define SPEAR320_SDHCI_BASE UL(0x70000000)
24#define SPEAR320_CLCD_BASE UL(0x90000000)
25#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
26#define SPEAR320_CAN0_BASE UL(0xA1000000)
27#define SPEAR320_CAN1_BASE UL(0xA2000000)
28#define SPEAR320_UART1_BASE UL(0xA3000000)
29#define SPEAR320_UART2_BASE UL(0xA4000000)
30#define SPEAR320_SSP0_BASE UL(0xA5000000)
31#define SPEAR320_SSP1_BASE UL(0xA6000000)
32#define SPEAR320_I2C_BASE UL(0xA7000000)
33#define SPEAR320_PWM_BASE UL(0xA8000000)
34#define SPEAR320_SMII0_BASE UL(0xAA000000)
35#define SPEAR320_SMII1_BASE UL(0xAB000000)
36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
37
38/* Interrupt registers offsets and masks */
39#define SPEAR320_INT_STS_MASK_REG 0x04
40#define SPEAR320_INT_CLR_MASK_REG 0x04
41#define SPEAR320_INT_ENB_MASK_REG 0x08
42#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
43#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
44#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
45#define SPEAR320_EMI_IRQ_MASK (1 << 7)
46#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
47#define SPEAR320_SPP_IRQ_MASK (1 << 9)
48#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
49#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
50#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
51#define SPEAR320_UART1_IRQ_MASK (1 << 13)
52#define SPEAR320_UART2_IRQ_MASK (1 << 14)
53#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
54#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
55#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
56#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
57#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
58#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
59#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
60
61#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
62#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
63#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
64
65#endif /* __MACH_SPEAR320_H */
66
67#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 2db0bd14e481..f74a05bdb829 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -19,7 +19,46 @@
19#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
20#include <plat/shirq.h> 20#include <plat/shirq.h>
21#include <mach/generic.h> 21#include <mach/generic.h>
22#include <mach/hardware.h> 22#include <mach/spear.h>
23
24/* Base address of various IPs */
25#define SPEAR300_TELECOM_BASE UL(0x50000000)
26
27/* Interrupt registers offsets and masks */
28#define SPEAR300_INT_ENB_MASK_REG 0x54
29#define SPEAR300_INT_STS_MASK_REG 0x58
30#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
31#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
32#define SPEAR300_I2S_IRQ_MASK (1 << 2)
33#define SPEAR300_TDM_IRQ_MASK (1 << 3)
34#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
35#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
36#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
37#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
38#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
39
40#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
41
42#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
43
44
45/* SPEAr300 Virtual irq definitions */
46/* IRQs sharing IRQ_GEN_RAS_1 */
47#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
48#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
49#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
50#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
51#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
52#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
53#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
54#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
55#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
56
57/* IRQs sharing IRQ_GEN_RAS_3 */
58#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
59
60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
23 62
24/* spear3xx shared irq */ 63/* spear3xx shared irq */
25static struct shirq_dev_config shirq_ras1_config[] = { 64static struct shirq_dev_config shirq_ras1_config[] = {
@@ -298,7 +337,6 @@ static const char * const spear300_dt_board_compat[] = {
298static void __init spear300_map_io(void) 337static void __init spear300_map_io(void)
299{ 338{
300 spear3xx_map_io(); 339 spear3xx_map_io();
301 spear300_clk_init();
302} 340}
303 341
304DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") 342DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index aec07c951205..84dfb0900747 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -20,7 +20,67 @@
20#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
21#include <plat/shirq.h> 21#include <plat/shirq.h>
22#include <mach/generic.h> 22#include <mach/generic.h>
23#include <mach/hardware.h> 23#include <mach/spear.h>
24
25#define SPEAR310_UART1_BASE UL(0xB2000000)
26#define SPEAR310_UART2_BASE UL(0xB2080000)
27#define SPEAR310_UART3_BASE UL(0xB2100000)
28#define SPEAR310_UART4_BASE UL(0xB2180000)
29#define SPEAR310_UART5_BASE UL(0xB2200000)
30#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
31
32/* Interrupt registers offsets and masks */
33#define SPEAR310_INT_STS_MASK_REG 0x04
34#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
35#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
36#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
37#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
38#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
39#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
40#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
41#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
42#define SPEAR310_UART1_IRQ_MASK (1 << 8)
43#define SPEAR310_UART2_IRQ_MASK (1 << 9)
44#define SPEAR310_UART3_IRQ_MASK (1 << 10)
45#define SPEAR310_UART4_IRQ_MASK (1 << 11)
46#define SPEAR310_UART5_IRQ_MASK (1 << 12)
47#define SPEAR310_EMI_IRQ_MASK (1 << 13)
48#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
49#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
50#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
51
52#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
53#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
54#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
55#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
56
57/* SPEAr310 Virtual irq definitions */
58/* IRQs sharing IRQ_GEN_RAS_1 */
59#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
60#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
61#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
62#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
63#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
64#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
65#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
66#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
67
68/* IRQs sharing IRQ_GEN_RAS_2 */
69#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
70#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
71#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
72#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
73#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
74
75/* IRQs sharing IRQ_GEN_RAS_3 */
76#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
77#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
78
79/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
80#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
81#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
83
24 84
25/* spear3xx shared irq */ 85/* spear3xx shared irq */
26static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
@@ -418,7 +478,6 @@ static const char * const spear310_dt_board_compat[] = {
418static void __init spear310_map_io(void) 478static void __init spear310_map_io(void)
419{ 479{
420 spear3xx_map_io(); 480 spear3xx_map_io();
421 spear310_clk_init();
422} 481}
423 482
424DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") 483DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index fb28c189688e..a88fa841d29d 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -21,9 +21,67 @@
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22#include <plat/shirq.h> 22#include <plat/shirq.h>
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/hardware.h>
25#include <mach/spear.h> 24#include <mach/spear.h>
26 25
26#define SPEAR320_UART1_BASE UL(0xA3000000)
27#define SPEAR320_UART2_BASE UL(0xA4000000)
28#define SPEAR320_SSP0_BASE UL(0xA5000000)
29#define SPEAR320_SSP1_BASE UL(0xA6000000)
30
31/* Interrupt registers offsets and masks */
32#define SPEAR320_INT_STS_MASK_REG 0x04
33#define SPEAR320_INT_CLR_MASK_REG 0x04
34#define SPEAR320_INT_ENB_MASK_REG 0x08
35#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
36#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
37#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
38#define SPEAR320_EMI_IRQ_MASK (1 << 7)
39#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
40#define SPEAR320_SPP_IRQ_MASK (1 << 9)
41#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
42#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
43#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
44#define SPEAR320_UART1_IRQ_MASK (1 << 13)
45#define SPEAR320_UART2_IRQ_MASK (1 << 14)
46#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
47#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
48#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
49#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
50#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
51#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
52#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
53
54#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
55#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
56#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
57
58/* SPEAr320 Virtual irq definitions */
59/* IRQs sharing IRQ_GEN_RAS_1 */
60#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
61#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
62#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
63
64/* IRQs sharing IRQ_GEN_RAS_2 */
65#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
66
67/* IRQs sharing IRQ_GEN_RAS_3 */
68#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
69#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
70#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
71
72/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
73#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
74#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
75#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
76#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
77#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
78#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
79#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
80#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
81#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
82#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
83#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
84
27/* spear3xx shared irq */ 85/* spear3xx shared irq */
28static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
29 { 87 {
@@ -422,10 +480,19 @@ static const char * const spear320_dt_board_compat[] = {
422 NULL, 480 NULL,
423}; 481};
424 482
483struct map_desc spear320_io_desc[] __initdata = {
484 {
485 .virtual = VA_SPEAR320_SOC_CONFIG_BASE,
486 .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
487 .length = SZ_16M,
488 .type = MT_DEVICE
489 },
490};
491
425static void __init spear320_map_io(void) 492static void __init spear320_map_io(void)
426{ 493{
494 iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
427 spear3xx_map_io(); 495 spear3xx_map_io();
428 spear320_clk_init();
429} 496}
430 497
431DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") 498DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 71927c717807..f22419ed74a8 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -21,7 +21,7 @@
21#include <asm/hardware/vic.h> 21#include <asm/hardware/vic.h>
22#include <plat/pl080.h> 22#include <plat/pl080.h>
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/hardware.h> 24#include <mach/spear.h>
25 25
26/* ssp device registration */ 26/* ssp device registration */
27struct pl022_ssp_controller pl022_plat_data = { 27struct pl022_ssp_controller pl022_plat_data = {
@@ -111,7 +111,7 @@ static void __init spear3xx_timer_init(void)
111 clk_put(gpt_clk); 111 clk_put(gpt_clk);
112 clk_put(pclk); 112 clk_put(pclk);
113 113
114 spear_setup_timer(); 114 spear_setup_of_timer();
115} 115}
116 116
117struct sys_timer spear3xx_timer = { 117struct sys_timer spear3xx_timer = {
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 116b99301cf5..65514b159370 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,34 +15,9 @@
15#define __MACH_GENERIC_H 15#define __MACH_GENERIC_H
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/amba/bus.h>
20#include <asm/mach/time.h>
21#include <asm/mach/map.h>
22
23/*
24 * Each GPT has 2 timer channels
25 * Following GPT channels will be used as clock source and clockevent
26 */
27#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE
28#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
29#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
30
31/* Add spear6xx family device structure declarations here */
32extern struct amba_device gpio_device[];
33extern struct amba_device uart_device[];
34extern struct sys_timer spear6xx_timer;
35
36/* Add spear6xx family function declarations here */
37void __init spear_setup_timer(void);
38void __init spear6xx_map_io(void);
39void __init spear6xx_init_irq(void);
40void __init spear6xx_init(void);
41void __init spear600_init(void);
42void __init spear6xx_clk_init(void);
43 18
19void __init spear_setup_of_timer(void);
44void spear_restart(char, const char *); 20void spear_restart(char, const char *);
45 21void __init spear6xx_clk_init(void);
46/* Add spear600 machine device structure declarations here */
47 22
48#endif /* __MACH_GENERIC_H */ 23#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 0b3f96ae2848..40a8c178f10d 100644
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -1,23 +1 @@
1/* /* empty */
2 * arch/arm/mach-spear6xx/include/mach/hardware.h
3 *
4 * Hardware definitions for SPEAr6xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Rajeev Kumar<rajeev-dlh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H
16
17#include <plat/hardware.h>
18#include <mach/spear.h>
19
20/* Vitual to physical translation of statically mapped space */
21#define IO_ADDRESS(x) (x | 0xF0000000)
22
23#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 8f214b03d75d..37a5c411a866 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,82 +16,10 @@
16 16
17/* IRQ definitions */ 17/* IRQ definitions */
18/* VIC 1 */ 18/* VIC 1 */
19#define IRQ_INTRCOMM_SW_IRQ 0
20#define IRQ_INTRCOMM_CPU_1 1
21#define IRQ_INTRCOMM_CPU_2 2
22#define IRQ_INTRCOMM_RAS2A11_1 3
23#define IRQ_INTRCOMM_RAS2A11_2 4
24#define IRQ_INTRCOMM_RAS2A12_1 5
25#define IRQ_INTRCOMM_RAS2A12_2 6
26#define IRQ_GEN_RAS_0 7
27#define IRQ_GEN_RAS_1 8
28#define IRQ_GEN_RAS_2 9
29#define IRQ_GEN_RAS_3 10
30#define IRQ_GEN_RAS_4 11
31#define IRQ_GEN_RAS_5 12
32#define IRQ_GEN_RAS_6 13
33#define IRQ_GEN_RAS_7 14
34#define IRQ_GEN_RAS_8 15
35#define IRQ_CPU_GPT1_1 16
36#define IRQ_CPU_GPT1_2 17
37#define IRQ_LOCAL_GPIO 18
38#define IRQ_PLL_UNLOCK 19
39#define IRQ_JPEG 20
40#define IRQ_FSMC 21
41#define IRQ_IRDA 22
42#define IRQ_RESERVED 23
43#define IRQ_UART_0 24
44#define IRQ_UART_1 25
45#define IRQ_SSP_1 26
46#define IRQ_SSP_2 27
47#define IRQ_I2C 28
48#define IRQ_GEN_RAS_9 29
49#define IRQ_GEN_RAS_10 30
50#define IRQ_GEN_RAS_11 31
51
52/* VIC 2 */
53#define IRQ_APPL_GPT1_1 32
54#define IRQ_APPL_GPT1_2 33
55#define IRQ_APPL_GPT2_1 34
56#define IRQ_APPL_GPT2_2 35
57#define IRQ_APPL_GPIO 36
58#define IRQ_APPL_SSP 37
59#define IRQ_APPL_ADC 38
60#define IRQ_APPL_RESERVED 39
61#define IRQ_AHB_EXP_MASTER 40
62#define IRQ_DDR_CONTROLLER 41
63#define IRQ_BASIC_DMA 42
64#define IRQ_BASIC_RESERVED1 43
65#define IRQ_BASIC_SMI 44
66#define IRQ_BASIC_CLCD 45
67#define IRQ_EXP_AHB_1 46
68#define IRQ_EXP_AHB_2 47
69#define IRQ_BASIC_GPT1_1 48
70#define IRQ_BASIC_GPT1_2 49
71#define IRQ_BASIC_RTC 50
72#define IRQ_BASIC_GPIO 51
73#define IRQ_BASIC_WDT 52
74#define IRQ_BASIC_RESERVED 53
75#define IRQ_AHB_EXP_SLAVE 54
76#define IRQ_GMAC_1 55
77#define IRQ_GMAC_2 56
78#define IRQ_USB_DEV 57
79#define IRQ_USB_H_OHCI_0 58
80#define IRQ_USB_H_EHCI_0 59
81#define IRQ_USB_H_OHCI_1 60
82#define IRQ_USB_H_EHCI_1 61
83#define IRQ_EXP_AHB_3 62
84#define IRQ_EXP_AHB_4 63
85
86#define IRQ_VIC_END 64 19#define IRQ_VIC_END 64
87 20
88/* GPIO pins virtual irqs */ 21/* GPIO pins virtual irqs */
89#define SPEAR_GPIO_INT_BASE IRQ_VIC_END 22#define VIRTUAL_IRQS 24
90#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE 23#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
91#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
92#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8)
93#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8)
94#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END)
95#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
96 24
97#endif /* __MACH_IRQS_H */ 25#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 633074fddf9a..179e45774b3a 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,9 +14,9 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h>
18#include <mach/spear.h> 17#include <mach/spear.h>
19 18
20#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
21 21
22#endif /* __MACH_MISC_REGS_H */ 22#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 7fd621532def..cb8ed2f4dc85 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -15,69 +15,25 @@
15#define __MACH_SPEAR6XX_H 15#define __MACH_SPEAR6XX_H
16 16
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <mach/spear600.h>
19 18
20#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
21/* ICM1 - Low speed connection */ 19/* ICM1 - Low speed connection */
22#define SPEAR6XX_ICM1_BASE UL(0xD0000000) 20#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
23 21#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000)
24#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) 22#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
25#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) 23#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
26
27#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
28#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
29#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
30#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
31#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
32#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
33#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
34#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
35#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
36
37/* ICM2 - Application Subsystem */
38#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
39#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
40#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
41#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
42#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
43#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
44 24
45/* ML-1, 2 - Multi Layer CPU Subsystem */ 25/* ML-1, 2 - Multi Layer CPU Subsystem */
46#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) 26#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
47#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000) 27#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
48#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
49#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
50#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
51#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
52#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
53 28
54/* ICM3 - Basic Subsystem */ 29/* ICM3 - Basic Subsystem */
55#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
56#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
57#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 30#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
58#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000) 31#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
59#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) 32#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
60#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
61#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
62#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
63#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
64#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
65#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 33#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
66#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) 34#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
67#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 35#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
68#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) 36#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
69
70/* ICM4 - High Speed Connection */
71#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
72#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
73#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
74#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
75#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
76#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
77#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
78#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
79#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
80#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
81 37
82/* Debug uart for linux, will be used for debug and uncompress messages */ 38/* Debug uart for linux, will be used for debug and uncompress messages */
83#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE 39#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
deleted file mode 100644
index c068cc50b0fb..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear600.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-spear66xx/include/mach/spear600.h
3 *
4 * SPEAr600 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR600
15
16#ifndef __MACH_SPEAR600_H
17#define __MACH_SPEAR600_H
18
19#endif /* __MACH_SPEAR600_H */
20
21#endif /* CONFIG_MACH_SPEAR600 */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index e9031ec6d6e0..2e2e3596583e 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -14,6 +14,8 @@
14 */ 14 */
15 15
16#include <linux/amba/pl08x.h> 16#include <linux/amba/pl08x.h>
17#include <linux/clk.h>
18#include <linux/err.h>
17#include <linux/of.h> 19#include <linux/of.h>
18#include <linux/of_address.h> 20#include <linux/of_address.h>
19#include <linux/of_irq.h> 21#include <linux/of_irq.h>
@@ -21,9 +23,11 @@
21#include <asm/hardware/pl080.h> 23#include <asm/hardware/pl080.h>
22#include <asm/hardware/vic.h> 24#include <asm/hardware/vic.h>
23#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27#include <asm/mach/map.h>
24#include <plat/pl080.h> 28#include <plat/pl080.h>
25#include <mach/generic.h> 29#include <mach/generic.h>
26#include <mach/hardware.h> 30#include <mach/spear.h>
27 31
28/* dmac device registration */ 32/* dmac device registration */
29static struct pl08x_channel_data spear600_dma_info[] = { 33static struct pl08x_channel_data spear600_dma_info[] = {
@@ -384,32 +388,29 @@ struct pl08x_platform_data pl080_plat_data = {
384 .num_slave_channels = ARRAY_SIZE(spear600_dma_info), 388 .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
385}; 389};
386 390
387/* Following will create static virtual/physical mappings */ 391/*
388static struct map_desc spear6xx_io_desc[] __initdata = { 392 * Following will create 16MB static virtual/physical mappings
393 * PHYSICAL VIRTUAL
394 * 0xF0000000 0xF0000000
395 * 0xF1000000 0xF1000000
396 * 0xD0000000 0xFD000000
397 * 0xFC000000 0xFC000000
398 */
399struct map_desc spear6xx_io_desc[] __initdata = {
389 { 400 {
390 .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, 401 .virtual = VA_SPEAR6XX_ML_CPU_BASE,
391 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), 402 .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
392 .length = SZ_4K, 403 .length = 2 * SZ_16M,
393 .type = MT_DEVICE
394 }, {
395 .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
396 .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
397 .length = SZ_4K,
398 .type = MT_DEVICE 404 .type = MT_DEVICE
399 }, { 405 }, {
400 .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, 406 .virtual = VA_SPEAR6XX_ICM1_BASE,
401 .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), 407 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
402 .length = SZ_4K, 408 .length = SZ_16M,
403 .type = MT_DEVICE
404 }, {
405 .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
406 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
407 .length = SZ_4K,
408 .type = MT_DEVICE 409 .type = MT_DEVICE
409 }, { 410 }, {
410 .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, 411 .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
411 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), 412 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
412 .length = SZ_4K, 413 .length = SZ_16M,
413 .type = MT_DEVICE 414 .type = MT_DEVICE
414 }, 415 },
415}; 416};
@@ -446,7 +447,7 @@ static void __init spear6xx_timer_init(void)
446 clk_put(gpt_clk); 447 clk_put(gpt_clk);
447 clk_put(pclk); 448 clk_put(pclk);
448 449
449 spear_setup_timer(); 450 spear_setup_of_timer();
450} 451}
451 452
452struct sys_timer spear6xx_timer = { 453struct sys_timer spear6xx_timer = {
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 02b160a1ec9b..ab3de721c5db 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -12,7 +12,7 @@
12 */ 12 */
13 13
14#include <linux/amba/serial.h> 14#include <linux/amba/serial.h>
15#include <mach/hardware.h> 15#include <mach/spear.h>
16 16
17 .macro addruart, rp, rv, tmp 17 .macro addruart, rp, rv, tmp
18 mov \rp, #SPEAR_DBG_UART_BASE @ Physical base 18 mov \rp, #SPEAR_DBG_UART_BASE @ Physical base
diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
deleted file mode 100644
index 70187d763e26..000000000000
--- a/arch/arm/plat-spear/include/plat/hardware.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/hardware.h
3 *
4 * Hardware definitions for SPEAr
5 *
6 * Copyright (C) 2010 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_HARDWARE_H
15#define __PLAT_HARDWARE_H
16
17#endif /* __PLAT_HARDWARE_H */
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 1bf84527aee4..6dd455bafdfd 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -13,7 +13,7 @@
13 13
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/amba/serial.h> 15#include <linux/amba/serial.h>
16#include <mach/hardware.h> 16#include <mach/spear.h>
17 17
18#ifndef __PLAT_UNCOMPRESS_H 18#ifndef __PLAT_UNCOMPRESS_H
19#define __PLAT_UNCOMPRESS_H 19#define __PLAT_UNCOMPRESS_H
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
index d53d75e1af5e..a56a067717c1 100644
--- a/arch/arm/plat-spear/pl080.c
+++ b/arch/arm/plat-spear/pl080.c
@@ -17,6 +17,7 @@
17#include <linux/err.h> 17#include <linux/err.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/spinlock_types.h> 19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
20#include <mach/misc_regs.h> 21#include <mach/misc_regs.h>
21 22
22static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x); 23static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 16f203e78d89..4471a232713a 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -13,7 +13,7 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <asm/system_misc.h> 14#include <asm/system_misc.h>
15#include <asm/hardware/sp810.h> 15#include <asm/hardware/sp810.h>
16#include <mach/hardware.h> 16#include <mach/spear.h>
17#include <mach/generic.h> 17#include <mach/generic.h>
18 18
19void spear_restart(char mode, const char *cmd) 19void spear_restart(char mode, const char *cmd)
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index 1c94989d725f..03321af5de9f 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -15,14 +15,15 @@
15#include <linux/err.h> 15#include <linux/err.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/ioport.h>
18#include <linux/io.h> 19#include <linux/io.h>
19#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/of_irq.h>
22#include <linux/of_address.h>
20#include <linux/time.h> 23#include <linux/time.h>
21#include <linux/irq.h> 24#include <linux/irq.h>
22#include <asm/mach/time.h> 25#include <asm/mach/time.h>
23#include <mach/generic.h> 26#include <mach/generic.h>
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26 27
27/* 28/*
28 * We would use TIMER0 and TIMER1 as clockevent and clocksource. 29 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
@@ -175,7 +176,7 @@ static struct irqaction spear_timer_irq = {
175 .handler = spear_timer_interrupt 176 .handler = spear_timer_interrupt
176}; 177};
177 178
178static void __init spear_clockevent_init(void) 179static void __init spear_clockevent_init(int irq)
179{ 180{
180 u32 tick_rate; 181 u32 tick_rate;
181 182
@@ -195,22 +196,35 @@ static void __init spear_clockevent_init(void)
195 196
196 clockevents_register_device(&clkevt); 197 clockevents_register_device(&clkevt);
197 198
198 setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq); 199 setup_irq(irq, &spear_timer_irq);
199} 200}
200 201
201void __init spear_setup_timer(void) 202const static struct of_device_id timer_of_match[] __initconst = {
203 { .compatible = "st,spear-timer", },
204 { },
205};
206
207void __init spear_setup_of_timer(void)
202{ 208{
203 int ret; 209 struct device_node *np;
210 int irq, ret;
211
212 np = of_find_matching_node(NULL, timer_of_match);
213 if (!np) {
214 pr_err("%s: No timer passed via DT\n", __func__);
215 return;
216 }
204 217
205 if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) { 218 irq = irq_of_parse_and_map(np, 0);
206 pr_err("%s:cannot get IO addr\n", __func__); 219 if (!irq) {
220 pr_err("%s: No irq passed for timer via DT\n", __func__);
207 return; 221 return;
208 } 222 }
209 223
210 gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K); 224 gpt_base = of_iomap(np, 0);
211 if (!gpt_base) { 225 if (!gpt_base) {
212 pr_err("%s:ioremap failed for gpt\n", __func__); 226 pr_err("%s: of iomap failed\n", __func__);
213 goto err_mem; 227 return;
214 } 228 }
215 229
216 gpt_clk = clk_get_sys("gpt0", NULL); 230 gpt_clk = clk_get_sys("gpt0", NULL);
@@ -225,7 +239,7 @@ void __init spear_setup_timer(void)
225 goto err_prepare_enable_clk; 239 goto err_prepare_enable_clk;
226 } 240 }
227 241
228 spear_clockevent_init(); 242 spear_clockevent_init(irq);
229 spear_clocksource_init(); 243 spear_clocksource_init();
230 244
231 return; 245 return;
@@ -234,6 +248,4 @@ err_prepare_enable_clk:
234 clk_put(gpt_clk); 248 clk_put(gpt_clk);
235err_iomap: 249err_iomap:
236 iounmap(gpt_base); 250 iounmap(gpt_base);
237err_mem:
238 release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
239} 251}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 09:12:37 -0500