diff options
author | Rafael J. Wysocki <rjw@sisk.pl> | 2012-07-11 17:02:31 -0400 |
---|---|---|
committer | Rafael J. Wysocki <rjw@sisk.pl> | 2012-07-11 17:02:31 -0400 |
commit | 27748df5eeb4a3b5e5dd588a199852d4cfaec53d (patch) | |
tree | b5c16b3b07229599988187b98ce340cf932104ea /arch/arm | |
parent | 0b14121f93e330a8231f6dafc1c6eaf888f3dbe6 (diff) | |
parent | 911a472aca3dac8aede558760a85ae051966dda0 (diff) |
Merge branch 'renesas-sh7372' into renesas-soc
* renesas-sh7372:
ARM: shmobile: Fix build problem in pm-sh7372.c for unusual .config
ARM: shmobile: Take cpuidle dependencies into account correctly
ARM: shmobile: sh7372: completely switch over to using pm-rmobile API
ARM: shmobile: ap4evb: switch to using pm-rmobile API
ARM: shmobile: mackerel: switch to using pm-rmobile API
ARM: shmobile: sh7372: add pm-rmobile domain support
ARM: shmobile: sh7372 A3SM CPUIdle support
ARM: shmobile: Use INTCA with sh7372 A3SM power domain
ARM: shmobile: use common DMAEngine definitions on sh7372
ARM: shmobile: sh7372: remove unused sh7372_a3sp_init() on !CONFIG_PM
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-shmobile/Kconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/board-ap4evb.c | 16 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/board-mackerel.c | 24 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/include/mach/sh7372.h | 45 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/pm-sh7372.c | 297 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/setup-sh7372.c | 209 |
6 files changed, 203 insertions, 389 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index df33909205e2..eedb0d1888c3 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig | |||
@@ -19,6 +19,7 @@ config ARCH_SH7372 | |||
19 | select CPU_V7 | 19 | select CPU_V7 |
20 | select SH_CLK_CPG | 20 | select SH_CLK_CPG |
21 | select ARCH_WANT_OPTIONAL_GPIOLIB | 21 | select ARCH_WANT_OPTIONAL_GPIOLIB |
22 | select ARM_CPU_SUSPEND if PM || CPU_IDLE | ||
22 | 23 | ||
23 | config ARCH_SH73A0 | 24 | config ARCH_SH73A0 |
24 | bool "SH-Mobile AG5 (R8A73A00)" | 25 | bool "SH-Mobile AG5 (R8A73A00)" |
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index ace60246a5df..7cac1df3085c 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c | |||
@@ -1447,14 +1447,14 @@ static void __init ap4evb_init(void) | |||
1447 | 1447 | ||
1448 | platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); | 1448 | platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); |
1449 | 1449 | ||
1450 | sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc1_device); | 1450 | rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc1_device); |
1451 | sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device); | 1451 | rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device); |
1452 | sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); | 1452 | rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device); |
1453 | 1453 | ||
1454 | sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); | 1454 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device); |
1455 | sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); | 1455 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device); |
1456 | sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device); | 1456 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device); |
1457 | sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device); | 1457 | rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device); |
1458 | 1458 | ||
1459 | hdmi_init_pm_clock(); | 1459 | hdmi_init_pm_clock(); |
1460 | fsi_init_pm_clock(); | 1460 | fsi_init_pm_clock(); |
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 150122a44630..9640f34122bd 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c | |||
@@ -1614,20 +1614,20 @@ static void __init mackerel_init(void) | |||
1614 | 1614 | ||
1615 | platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); | 1615 | platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); |
1616 | 1616 | ||
1617 | sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device); | 1617 | rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device); |
1618 | sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device); | 1618 | rmobile_add_device_to_domain(&sh7372_pd_a4lc, &hdmi_lcdc_device); |
1619 | sh7372_add_device_to_domain(&sh7372_a4lc, &meram_device); | 1619 | rmobile_add_device_to_domain(&sh7372_pd_a4lc, &meram_device); |
1620 | sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); | 1620 | rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device); |
1621 | sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device); | 1621 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs0_device); |
1622 | sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device); | 1622 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs1_device); |
1623 | sh7372_add_device_to_domain(&sh7372_a3sp, &nand_flash_device); | 1623 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &nand_flash_device); |
1624 | sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); | 1624 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device); |
1625 | sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); | 1625 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device); |
1626 | #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) | 1626 | #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) |
1627 | sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device); | 1627 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device); |
1628 | #endif | 1628 | #endif |
1629 | sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device); | 1629 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi2_device); |
1630 | sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device); | 1630 | rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device); |
1631 | 1631 | ||
1632 | hdmi_init_pm_clock(); | 1632 | hdmi_init_pm_clock(); |
1633 | sh7372_pm_init(); | 1633 | sh7372_pm_init(); |
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index 915d0093da08..b59048e6d8fd 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h | |||
@@ -13,6 +13,7 @@ | |||
13 | 13 | ||
14 | #include <linux/sh_clk.h> | 14 | #include <linux/sh_clk.h> |
15 | #include <linux/pm_domain.h> | 15 | #include <linux/pm_domain.h> |
16 | #include <mach/pm-rmobile.h> | ||
16 | 17 | ||
17 | /* | 18 | /* |
18 | * Pin Function Controller: | 19 | * Pin Function Controller: |
@@ -477,42 +478,16 @@ extern struct clk sh7372_fsibck_clk; | |||
477 | extern struct clk sh7372_fsidiva_clk; | 478 | extern struct clk sh7372_fsidiva_clk; |
478 | extern struct clk sh7372_fsidivb_clk; | 479 | extern struct clk sh7372_fsidivb_clk; |
479 | 480 | ||
480 | struct platform_device; | ||
481 | |||
482 | struct sh7372_pm_domain { | ||
483 | struct generic_pm_domain genpd; | ||
484 | struct dev_power_governor *gov; | ||
485 | int (*suspend)(void); | ||
486 | void (*resume)(void); | ||
487 | unsigned int bit_shift; | ||
488 | bool no_debug; | ||
489 | }; | ||
490 | |||
491 | static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d) | ||
492 | { | ||
493 | return container_of(d, struct sh7372_pm_domain, genpd); | ||
494 | } | ||
495 | |||
496 | #ifdef CONFIG_PM | 481 | #ifdef CONFIG_PM |
497 | extern struct sh7372_pm_domain sh7372_a4lc; | 482 | extern struct rmobile_pm_domain sh7372_pd_a4lc; |
498 | extern struct sh7372_pm_domain sh7372_a4mp; | 483 | extern struct rmobile_pm_domain sh7372_pd_a4mp; |
499 | extern struct sh7372_pm_domain sh7372_d4; | 484 | extern struct rmobile_pm_domain sh7372_pd_d4; |
500 | extern struct sh7372_pm_domain sh7372_a4r; | 485 | extern struct rmobile_pm_domain sh7372_pd_a4r; |
501 | extern struct sh7372_pm_domain sh7372_a3rv; | 486 | extern struct rmobile_pm_domain sh7372_pd_a3rv; |
502 | extern struct sh7372_pm_domain sh7372_a3ri; | 487 | extern struct rmobile_pm_domain sh7372_pd_a3ri; |
503 | extern struct sh7372_pm_domain sh7372_a4s; | 488 | extern struct rmobile_pm_domain sh7372_pd_a4s; |
504 | extern struct sh7372_pm_domain sh7372_a3sp; | 489 | extern struct rmobile_pm_domain sh7372_pd_a3sp; |
505 | extern struct sh7372_pm_domain sh7372_a3sg; | 490 | extern struct rmobile_pm_domain sh7372_pd_a3sg; |
506 | |||
507 | extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd); | ||
508 | extern void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd, | ||
509 | struct platform_device *pdev); | ||
510 | extern void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd, | ||
511 | struct sh7372_pm_domain *sh7372_sd); | ||
512 | #else | ||
513 | #define sh7372_init_pm_domain(pd) do { } while(0) | ||
514 | #define sh7372_add_device_to_domain(pd, pdev) do { } while(0) | ||
515 | #define sh7372_pm_add_subdomain(pd, sd) do { } while(0) | ||
516 | #endif /* CONFIG_PM */ | 491 | #endif /* CONFIG_PM */ |
517 | 492 | ||
518 | extern void sh7372_intcs_suspend(void); | 493 | extern void sh7372_intcs_suspend(void); |
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c index a3bdb12acde9..792037069226 100644 --- a/arch/arm/mach-shmobile/pm-sh7372.c +++ b/arch/arm/mach-shmobile/pm-sh7372.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <asm/suspend.h> | 26 | #include <asm/suspend.h> |
27 | #include <mach/common.h> | 27 | #include <mach/common.h> |
28 | #include <mach/sh7372.h> | 28 | #include <mach/sh7372.h> |
29 | #include <mach/pm-rmobile.h> | ||
29 | 30 | ||
30 | /* DBG */ | 31 | /* DBG */ |
31 | #define DBGREG1 0xe6100020 | 32 | #define DBGREG1 0xe6100020 |
@@ -41,13 +42,10 @@ | |||
41 | #define PLLC01STPCR 0xe61500c8 | 42 | #define PLLC01STPCR 0xe61500c8 |
42 | 43 | ||
43 | /* SYSC */ | 44 | /* SYSC */ |
44 | #define SPDCR 0xe6180008 | ||
45 | #define SWUCR 0xe6180014 | ||
46 | #define SBAR 0xe6180020 | 45 | #define SBAR 0xe6180020 |
47 | #define WUPRMSK 0xe6180028 | 46 | #define WUPRMSK 0xe6180028 |
48 | #define WUPSMSK 0xe618002c | 47 | #define WUPSMSK 0xe618002c |
49 | #define WUPSMSK2 0xe6180048 | 48 | #define WUPSMSK2 0xe6180048 |
50 | #define PSTR 0xe6180080 | ||
51 | #define WUPSFAC 0xe6180098 | 49 | #define WUPSFAC 0xe6180098 |
52 | #define IRQCR 0xe618022c | 50 | #define IRQCR 0xe618022c |
53 | #define IRQCR2 0xe6180238 | 51 | #define IRQCR2 0xe6180238 |
@@ -71,188 +69,48 @@ | |||
71 | /* AP-System Core */ | 69 | /* AP-System Core */ |
72 | #define APARMBAREA 0xe6f10020 | 70 | #define APARMBAREA 0xe6f10020 |
73 | 71 | ||
74 | #define PSTR_RETRIES 100 | ||
75 | #define PSTR_DELAY_US 10 | ||
76 | |||
77 | #ifdef CONFIG_PM | 72 | #ifdef CONFIG_PM |
78 | 73 | ||
79 | static int pd_power_down(struct generic_pm_domain *genpd) | 74 | struct rmobile_pm_domain sh7372_pd_a4lc = { |
80 | { | ||
81 | struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd); | ||
82 | unsigned int mask = 1 << sh7372_pd->bit_shift; | ||
83 | |||
84 | if (sh7372_pd->suspend) { | ||
85 | int ret = sh7372_pd->suspend(); | ||
86 | |||
87 | if (ret) | ||
88 | return ret; | ||
89 | } | ||
90 | |||
91 | if (__raw_readl(PSTR) & mask) { | ||
92 | unsigned int retry_count; | ||
93 | |||
94 | __raw_writel(mask, SPDCR); | ||
95 | |||
96 | for (retry_count = PSTR_RETRIES; retry_count; retry_count--) { | ||
97 | if (!(__raw_readl(SPDCR) & mask)) | ||
98 | break; | ||
99 | cpu_relax(); | ||
100 | } | ||
101 | } | ||
102 | |||
103 | if (!sh7372_pd->no_debug) | ||
104 | pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n", | ||
105 | genpd->name, mask, __raw_readl(PSTR)); | ||
106 | |||
107 | return 0; | ||
108 | } | ||
109 | |||
110 | static int __pd_power_up(struct sh7372_pm_domain *sh7372_pd, bool do_resume) | ||
111 | { | ||
112 | unsigned int mask = 1 << sh7372_pd->bit_shift; | ||
113 | unsigned int retry_count; | ||
114 | int ret = 0; | ||
115 | |||
116 | if (__raw_readl(PSTR) & mask) | ||
117 | goto out; | ||
118 | |||
119 | __raw_writel(mask, SWUCR); | ||
120 | |||
121 | for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) { | ||
122 | if (!(__raw_readl(SWUCR) & mask)) | ||
123 | break; | ||
124 | if (retry_count > PSTR_RETRIES) | ||
125 | udelay(PSTR_DELAY_US); | ||
126 | else | ||
127 | cpu_relax(); | ||
128 | } | ||
129 | if (!retry_count) | ||
130 | ret = -EIO; | ||
131 | |||
132 | if (!sh7372_pd->no_debug) | ||
133 | pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n", | ||
134 | sh7372_pd->genpd.name, mask, __raw_readl(PSTR)); | ||
135 | |||
136 | out: | ||
137 | if (ret == 0 && sh7372_pd->resume && do_resume) | ||
138 | sh7372_pd->resume(); | ||
139 | |||
140 | return ret; | ||
141 | } | ||
142 | |||
143 | static int pd_power_up(struct generic_pm_domain *genpd) | ||
144 | { | ||
145 | return __pd_power_up(to_sh7372_pd(genpd), true); | ||
146 | } | ||
147 | |||
148 | static int sh7372_a4r_suspend(void) | ||
149 | { | ||
150 | sh7372_intcs_suspend(); | ||
151 | __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */ | ||
152 | return 0; | ||
153 | } | ||
154 | |||
155 | static bool pd_active_wakeup(struct device *dev) | ||
156 | { | ||
157 | bool (*active_wakeup)(struct device *dev); | ||
158 | |||
159 | active_wakeup = dev_gpd_data(dev)->ops.active_wakeup; | ||
160 | return active_wakeup ? active_wakeup(dev) : true; | ||
161 | } | ||
162 | |||
163 | static int sh7372_stop_dev(struct device *dev) | ||
164 | { | ||
165 | int (*stop)(struct device *dev); | ||
166 | |||
167 | stop = dev_gpd_data(dev)->ops.stop; | ||
168 | if (stop) { | ||
169 | int ret = stop(dev); | ||
170 | if (ret) | ||
171 | return ret; | ||
172 | } | ||
173 | return pm_clk_suspend(dev); | ||
174 | } | ||
175 | |||
176 | static int sh7372_start_dev(struct device *dev) | ||
177 | { | ||
178 | int (*start)(struct device *dev); | ||
179 | int ret; | ||
180 | |||
181 | ret = pm_clk_resume(dev); | ||
182 | if (ret) | ||
183 | return ret; | ||
184 | |||
185 | start = dev_gpd_data(dev)->ops.start; | ||
186 | if (start) | ||
187 | ret = start(dev); | ||
188 | |||
189 | return ret; | ||
190 | } | ||
191 | |||
192 | void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd) | ||
193 | { | ||
194 | struct generic_pm_domain *genpd = &sh7372_pd->genpd; | ||
195 | struct dev_power_governor *gov = sh7372_pd->gov; | ||
196 | |||
197 | pm_genpd_init(genpd, gov ? : &simple_qos_governor, false); | ||
198 | genpd->dev_ops.stop = sh7372_stop_dev; | ||
199 | genpd->dev_ops.start = sh7372_start_dev; | ||
200 | genpd->dev_ops.active_wakeup = pd_active_wakeup; | ||
201 | genpd->dev_irq_safe = true; | ||
202 | genpd->power_off = pd_power_down; | ||
203 | genpd->power_on = pd_power_up; | ||
204 | __pd_power_up(sh7372_pd, false); | ||
205 | } | ||
206 | |||
207 | void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd, | ||
208 | struct platform_device *pdev) | ||
209 | { | ||
210 | struct device *dev = &pdev->dev; | ||
211 | |||
212 | pm_genpd_add_device(&sh7372_pd->genpd, dev); | ||
213 | if (pm_clk_no_clocks(dev)) | ||
214 | pm_clk_add(dev, NULL); | ||
215 | } | ||
216 | |||
217 | void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd, | ||
218 | struct sh7372_pm_domain *sh7372_sd) | ||
219 | { | ||
220 | pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd); | ||
221 | } | ||
222 | |||
223 | struct sh7372_pm_domain sh7372_a4lc = { | ||
224 | .genpd.name = "A4LC", | 75 | .genpd.name = "A4LC", |
225 | .bit_shift = 1, | 76 | .bit_shift = 1, |
226 | }; | 77 | }; |
227 | 78 | ||
228 | struct sh7372_pm_domain sh7372_a4mp = { | 79 | struct rmobile_pm_domain sh7372_pd_a4mp = { |
229 | .genpd.name = "A4MP", | 80 | .genpd.name = "A4MP", |
230 | .bit_shift = 2, | 81 | .bit_shift = 2, |
231 | }; | 82 | }; |
232 | 83 | ||
233 | struct sh7372_pm_domain sh7372_d4 = { | 84 | struct rmobile_pm_domain sh7372_pd_d4 = { |
234 | .genpd.name = "D4", | 85 | .genpd.name = "D4", |
235 | .bit_shift = 3, | 86 | .bit_shift = 3, |
236 | }; | 87 | }; |
237 | 88 | ||
238 | struct sh7372_pm_domain sh7372_a4r = { | 89 | static int sh7372_a4r_pd_suspend(void) |
90 | { | ||
91 | sh7372_intcs_suspend(); | ||
92 | __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */ | ||
93 | return 0; | ||
94 | } | ||
95 | |||
96 | struct rmobile_pm_domain sh7372_pd_a4r = { | ||
239 | .genpd.name = "A4R", | 97 | .genpd.name = "A4R", |
240 | .bit_shift = 5, | 98 | .bit_shift = 5, |
241 | .suspend = sh7372_a4r_suspend, | 99 | .suspend = sh7372_a4r_pd_suspend, |
242 | .resume = sh7372_intcs_resume, | 100 | .resume = sh7372_intcs_resume, |
243 | }; | 101 | }; |
244 | 102 | ||
245 | struct sh7372_pm_domain sh7372_a3rv = { | 103 | struct rmobile_pm_domain sh7372_pd_a3rv = { |
246 | .genpd.name = "A3RV", | 104 | .genpd.name = "A3RV", |
247 | .bit_shift = 6, | 105 | .bit_shift = 6, |
248 | }; | 106 | }; |
249 | 107 | ||
250 | struct sh7372_pm_domain sh7372_a3ri = { | 108 | struct rmobile_pm_domain sh7372_pd_a3ri = { |
251 | .genpd.name = "A3RI", | 109 | .genpd.name = "A3RI", |
252 | .bit_shift = 8, | 110 | .bit_shift = 8, |
253 | }; | 111 | }; |
254 | 112 | ||
255 | static int sh7372_a4s_suspend(void) | 113 | static int sh7372_pd_a4s_suspend(void) |
256 | { | 114 | { |
257 | /* | 115 | /* |
258 | * The A4S domain contains the CPU core and therefore it should | 116 | * The A4S domain contains the CPU core and therefore it should |
@@ -261,15 +119,15 @@ static int sh7372_a4s_suspend(void) | |||
261 | return -EBUSY; | 119 | return -EBUSY; |
262 | } | 120 | } |
263 | 121 | ||
264 | struct sh7372_pm_domain sh7372_a4s = { | 122 | struct rmobile_pm_domain sh7372_pd_a4s = { |
265 | .genpd.name = "A4S", | 123 | .genpd.name = "A4S", |
266 | .bit_shift = 10, | 124 | .bit_shift = 10, |
267 | .gov = &pm_domain_always_on_gov, | 125 | .gov = &pm_domain_always_on_gov, |
268 | .no_debug = true, | 126 | .no_debug = true, |
269 | .suspend = sh7372_a4s_suspend, | 127 | .suspend = sh7372_pd_a4s_suspend, |
270 | }; | 128 | }; |
271 | 129 | ||
272 | static int sh7372_a3sp_suspend(void) | 130 | static int sh7372_a3sp_pd_suspend(void) |
273 | { | 131 | { |
274 | /* | 132 | /* |
275 | * Serial consoles make use of SCIF hardware located in A3SP, | 133 | * Serial consoles make use of SCIF hardware located in A3SP, |
@@ -278,32 +136,22 @@ static int sh7372_a3sp_suspend(void) | |||
278 | return console_suspend_enabled ? 0 : -EBUSY; | 136 | return console_suspend_enabled ? 0 : -EBUSY; |
279 | } | 137 | } |
280 | 138 | ||
281 | struct sh7372_pm_domain sh7372_a3sp = { | 139 | struct rmobile_pm_domain sh7372_pd_a3sp = { |
282 | .genpd.name = "A3SP", | 140 | .genpd.name = "A3SP", |
283 | .bit_shift = 11, | 141 | .bit_shift = 11, |
284 | .gov = &pm_domain_always_on_gov, | 142 | .gov = &pm_domain_always_on_gov, |
285 | .no_debug = true, | 143 | .no_debug = true, |
286 | .suspend = sh7372_a3sp_suspend, | 144 | .suspend = sh7372_a3sp_pd_suspend, |
287 | }; | 145 | }; |
288 | 146 | ||
289 | struct sh7372_pm_domain sh7372_a3sg = { | 147 | struct rmobile_pm_domain sh7372_pd_a3sg = { |
290 | .genpd.name = "A3SG", | 148 | .genpd.name = "A3SG", |
291 | .bit_shift = 13, | 149 | .bit_shift = 13, |
292 | }; | 150 | }; |
293 | 151 | ||
294 | #else /* !CONFIG_PM */ | 152 | #endif /* CONFIG_PM */ |
295 | |||
296 | static inline void sh7372_a3sp_init(void) {} | ||
297 | |||
298 | #endif /* !CONFIG_PM */ | ||
299 | 153 | ||
300 | #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) | 154 | #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) |
301 | static int sh7372_do_idle_core_standby(unsigned long unused) | ||
302 | { | ||
303 | cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */ | ||
304 | return 0; | ||
305 | } | ||
306 | |||
307 | static void sh7372_set_reset_vector(unsigned long address) | 155 | static void sh7372_set_reset_vector(unsigned long address) |
308 | { | 156 | { |
309 | /* set reset vector, translate 4k */ | 157 | /* set reset vector, translate 4k */ |
@@ -311,21 +159,6 @@ static void sh7372_set_reset_vector(unsigned long address) | |||
311 | __raw_writel(0, APARMBAREA); | 159 | __raw_writel(0, APARMBAREA); |
312 | } | 160 | } |
313 | 161 | ||
314 | static void sh7372_enter_core_standby(void) | ||
315 | { | ||
316 | sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc)); | ||
317 | |||
318 | /* enter sleep mode with SYSTBCR to 0x10 */ | ||
319 | __raw_writel(0x10, SYSTBCR); | ||
320 | cpu_suspend(0, sh7372_do_idle_core_standby); | ||
321 | __raw_writel(0, SYSTBCR); | ||
322 | |||
323 | /* disable reset vector translation */ | ||
324 | __raw_writel(0, SBAR); | ||
325 | } | ||
326 | #endif | ||
327 | |||
328 | #ifdef CONFIG_SUSPEND | ||
329 | static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode) | 162 | static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode) |
330 | { | 163 | { |
331 | if (pllc0_on) | 164 | if (pllc0_on) |
@@ -465,22 +298,42 @@ static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2) | |||
465 | 298 | ||
466 | static void sh7372_enter_a3sm_common(int pllc0_on) | 299 | static void sh7372_enter_a3sm_common(int pllc0_on) |
467 | { | 300 | { |
301 | /* use INTCA together with SYSC for wakeup */ | ||
302 | sh7372_setup_sysc(1 << 0, 0); | ||
468 | sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc)); | 303 | sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc)); |
469 | sh7372_enter_sysc(pllc0_on, 1 << 12); | 304 | sh7372_enter_sysc(pllc0_on, 1 << 12); |
470 | } | 305 | } |
306 | #endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */ | ||
471 | 307 | ||
472 | static void sh7372_enter_a4s_common(int pllc0_on) | 308 | #ifdef CONFIG_CPU_IDLE |
309 | static int sh7372_do_idle_core_standby(unsigned long unused) | ||
473 | { | 310 | { |
474 | sh7372_intca_suspend(); | 311 | cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */ |
475 | memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100); | 312 | return 0; |
476 | sh7372_set_reset_vector(SMFRAM); | ||
477 | sh7372_enter_sysc(pllc0_on, 1 << 10); | ||
478 | sh7372_intca_resume(); | ||
479 | } | 313 | } |
480 | 314 | ||
481 | #endif | 315 | static void sh7372_enter_core_standby(void) |
316 | { | ||
317 | sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc)); | ||
482 | 318 | ||
483 | #ifdef CONFIG_CPU_IDLE | 319 | /* enter sleep mode with SYSTBCR to 0x10 */ |
320 | __raw_writel(0x10, SYSTBCR); | ||
321 | cpu_suspend(0, sh7372_do_idle_core_standby); | ||
322 | __raw_writel(0, SYSTBCR); | ||
323 | |||
324 | /* disable reset vector translation */ | ||
325 | __raw_writel(0, SBAR); | ||
326 | } | ||
327 | |||
328 | static void sh7372_enter_a3sm_pll_on(void) | ||
329 | { | ||
330 | sh7372_enter_a3sm_common(1); | ||
331 | } | ||
332 | |||
333 | static void sh7372_enter_a3sm_pll_off(void) | ||
334 | { | ||
335 | sh7372_enter_a3sm_common(0); | ||
336 | } | ||
484 | 337 | ||
485 | static void sh7372_cpuidle_setup(struct cpuidle_driver *drv) | 338 | static void sh7372_cpuidle_setup(struct cpuidle_driver *drv) |
486 | { | 339 | { |
@@ -492,7 +345,24 @@ static void sh7372_cpuidle_setup(struct cpuidle_driver *drv) | |||
492 | state->target_residency = 20 + 10; | 345 | state->target_residency = 20 + 10; |
493 | state->flags = CPUIDLE_FLAG_TIME_VALID; | 346 | state->flags = CPUIDLE_FLAG_TIME_VALID; |
494 | shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby; | 347 | shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby; |
348 | drv->state_count++; | ||
349 | |||
350 | state = &drv->states[drv->state_count]; | ||
351 | snprintf(state->name, CPUIDLE_NAME_LEN, "C3"); | ||
352 | strncpy(state->desc, "A3SM PLL ON", CPUIDLE_DESC_LEN); | ||
353 | state->exit_latency = 20; | ||
354 | state->target_residency = 30 + 20; | ||
355 | state->flags = CPUIDLE_FLAG_TIME_VALID; | ||
356 | shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_on; | ||
357 | drv->state_count++; | ||
495 | 358 | ||
359 | state = &drv->states[drv->state_count]; | ||
360 | snprintf(state->name, CPUIDLE_NAME_LEN, "C4"); | ||
361 | strncpy(state->desc, "A3SM PLL OFF", CPUIDLE_DESC_LEN); | ||
362 | state->exit_latency = 120; | ||
363 | state->target_residency = 30 + 120; | ||
364 | state->flags = CPUIDLE_FLAG_TIME_VALID; | ||
365 | shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_off; | ||
496 | drv->state_count++; | 366 | drv->state_count++; |
497 | } | 367 | } |
498 | 368 | ||
@@ -505,6 +375,14 @@ static void sh7372_cpuidle_init(void) {} | |||
505 | #endif | 375 | #endif |
506 | 376 | ||
507 | #ifdef CONFIG_SUSPEND | 377 | #ifdef CONFIG_SUSPEND |
378 | static void sh7372_enter_a4s_common(int pllc0_on) | ||
379 | { | ||
380 | sh7372_intca_suspend(); | ||
381 | memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100); | ||
382 | sh7372_set_reset_vector(SMFRAM); | ||
383 | sh7372_enter_sysc(pllc0_on, 1 << 10); | ||
384 | sh7372_intca_resume(); | ||
385 | } | ||
508 | 386 | ||
509 | static int sh7372_enter_suspend(suspend_state_t suspend_state) | 387 | static int sh7372_enter_suspend(suspend_state_t suspend_state) |
510 | { | 388 | { |
@@ -512,24 +390,21 @@ static int sh7372_enter_suspend(suspend_state_t suspend_state) | |||
512 | 390 | ||
513 | /* check active clocks to determine potential wakeup sources */ | 391 | /* check active clocks to determine potential wakeup sources */ |
514 | if (sh7372_sysc_valid(&msk, &msk2)) { | 392 | if (sh7372_sysc_valid(&msk, &msk2)) { |
515 | /* convert INTC mask and sense to SYSC mask and sense */ | ||
516 | sh7372_setup_sysc(msk, msk2); | ||
517 | |||
518 | if (!console_suspend_enabled && | 393 | if (!console_suspend_enabled && |
519 | sh7372_a4s.genpd.status == GPD_STATE_POWER_OFF) { | 394 | sh7372_pd_a4s.genpd.status == GPD_STATE_POWER_OFF) { |
395 | /* convert INTC mask/sense to SYSC mask/sense */ | ||
396 | sh7372_setup_sysc(msk, msk2); | ||
397 | |||
520 | /* enter A4S sleep with PLLC0 off */ | 398 | /* enter A4S sleep with PLLC0 off */ |
521 | pr_debug("entering A4S\n"); | 399 | pr_debug("entering A4S\n"); |
522 | sh7372_enter_a4s_common(0); | 400 | sh7372_enter_a4s_common(0); |
523 | } else { | 401 | return 0; |
524 | /* enter A3SM sleep with PLLC0 off */ | ||
525 | pr_debug("entering A3SM\n"); | ||
526 | sh7372_enter_a3sm_common(0); | ||
527 | } | 402 | } |
528 | } else { | ||
529 | /* default to Core Standby that supports all wakeup sources */ | ||
530 | pr_debug("entering Core Standby\n"); | ||
531 | sh7372_enter_core_standby(); | ||
532 | } | 403 | } |
404 | |||
405 | /* default to enter A3SM sleep with PLLC0 off */ | ||
406 | pr_debug("entering A3SM\n"); | ||
407 | sh7372_enter_a3sm_common(0); | ||
533 | return 0; | 408 | return 0; |
534 | } | 409 | } |
535 | 410 | ||
@@ -550,7 +425,7 @@ static int sh7372_pm_notifier_fn(struct notifier_block *notifier, | |||
550 | * executed during system suspend and resume, respectively, so | 425 | * executed during system suspend and resume, respectively, so |
551 | * that those functions don't crash while accessing the INTCS. | 426 | * that those functions don't crash while accessing the INTCS. |
552 | */ | 427 | */ |
553 | pm_genpd_poweron(&sh7372_a4r.genpd); | 428 | pm_genpd_poweron(&sh7372_pd_a4r.genpd); |
554 | break; | 429 | break; |
555 | case PM_POST_SUSPEND: | 430 | case PM_POST_SUSPEND: |
556 | pm_genpd_poweroff_unused(); | 431 | pm_genpd_poweroff_unused(); |
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index fafce9ce8218..838a87be1d5c 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c | |||
@@ -33,6 +33,7 @@ | |||
33 | #include <linux/sh_timer.h> | 33 | #include <linux/sh_timer.h> |
34 | #include <linux/pm_domain.h> | 34 | #include <linux/pm_domain.h> |
35 | #include <linux/dma-mapping.h> | 35 | #include <linux/dma-mapping.h> |
36 | #include <mach/dma-register.h> | ||
36 | #include <mach/hardware.h> | 37 | #include <mach/hardware.h> |
37 | #include <mach/irqs.h> | 38 | #include <mach/irqs.h> |
38 | #include <mach/sh7372.h> | 39 | #include <mach/sh7372.h> |
@@ -335,151 +336,126 @@ static struct platform_device iic1_device = { | |||
335 | }; | 336 | }; |
336 | 337 | ||
337 | /* DMA */ | 338 | /* DMA */ |
338 | /* Transmit sizes and respective CHCR register values */ | ||
339 | enum { | ||
340 | XMIT_SZ_8BIT = 0, | ||
341 | XMIT_SZ_16BIT = 1, | ||
342 | XMIT_SZ_32BIT = 2, | ||
343 | XMIT_SZ_64BIT = 7, | ||
344 | XMIT_SZ_128BIT = 3, | ||
345 | XMIT_SZ_256BIT = 4, | ||
346 | XMIT_SZ_512BIT = 5, | ||
347 | }; | ||
348 | |||
349 | /* log2(size / 8) - used to calculate number of transfers */ | ||
350 | #define TS_SHIFT { \ | ||
351 | [XMIT_SZ_8BIT] = 0, \ | ||
352 | [XMIT_SZ_16BIT] = 1, \ | ||
353 | [XMIT_SZ_32BIT] = 2, \ | ||
354 | [XMIT_SZ_64BIT] = 3, \ | ||
355 | [XMIT_SZ_128BIT] = 4, \ | ||
356 | [XMIT_SZ_256BIT] = 5, \ | ||
357 | [XMIT_SZ_512BIT] = 6, \ | ||
358 | } | ||
359 | |||
360 | #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \ | ||
361 | (((i) & 0xc) << (20 - 2))) | ||
362 | |||
363 | static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { | 339 | static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { |
364 | { | 340 | { |
365 | .slave_id = SHDMA_SLAVE_SCIF0_TX, | 341 | .slave_id = SHDMA_SLAVE_SCIF0_TX, |
366 | .addr = 0xe6c40020, | 342 | .addr = 0xe6c40020, |
367 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 343 | .chcr = CHCR_TX(XMIT_SZ_8BIT), |
368 | .mid_rid = 0x21, | 344 | .mid_rid = 0x21, |
369 | }, { | 345 | }, { |
370 | .slave_id = SHDMA_SLAVE_SCIF0_RX, | 346 | .slave_id = SHDMA_SLAVE_SCIF0_RX, |
371 | .addr = 0xe6c40024, | 347 | .addr = 0xe6c40024, |
372 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 348 | .chcr = CHCR_RX(XMIT_SZ_8BIT), |
373 | .mid_rid = 0x22, | 349 | .mid_rid = 0x22, |
374 | }, { | 350 | }, { |
375 | .slave_id = SHDMA_SLAVE_SCIF1_TX, | 351 | .slave_id = SHDMA_SLAVE_SCIF1_TX, |
376 | .addr = 0xe6c50020, | 352 | .addr = 0xe6c50020, |
377 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 353 | .chcr = CHCR_TX(XMIT_SZ_8BIT), |
378 | .mid_rid = 0x25, | 354 | .mid_rid = 0x25, |
379 | }, { | 355 | }, { |
380 | .slave_id = SHDMA_SLAVE_SCIF1_RX, | 356 | .slave_id = SHDMA_SLAVE_SCIF1_RX, |
381 | .addr = 0xe6c50024, | 357 | .addr = 0xe6c50024, |
382 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 358 | .chcr = CHCR_RX(XMIT_SZ_8BIT), |
383 | .mid_rid = 0x26, | 359 | .mid_rid = 0x26, |
384 | }, { | 360 | }, { |
385 | .slave_id = SHDMA_SLAVE_SCIF2_TX, | 361 | .slave_id = SHDMA_SLAVE_SCIF2_TX, |
386 | .addr = 0xe6c60020, | 362 | .addr = 0xe6c60020, |
387 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 363 | .chcr = CHCR_TX(XMIT_SZ_8BIT), |
388 | .mid_rid = 0x29, | 364 | .mid_rid = 0x29, |
389 | }, { | 365 | }, { |
390 | .slave_id = SHDMA_SLAVE_SCIF2_RX, | 366 | .slave_id = SHDMA_SLAVE_SCIF2_RX, |
391 | .addr = 0xe6c60024, | 367 | .addr = 0xe6c60024, |
392 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 368 | .chcr = CHCR_RX(XMIT_SZ_8BIT), |
393 | .mid_rid = 0x2a, | 369 | .mid_rid = 0x2a, |
394 | }, { | 370 | }, { |
395 | .slave_id = SHDMA_SLAVE_SCIF3_TX, | 371 | .slave_id = SHDMA_SLAVE_SCIF3_TX, |
396 | .addr = 0xe6c70020, | 372 | .addr = 0xe6c70020, |
397 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 373 | .chcr = CHCR_TX(XMIT_SZ_8BIT), |
398 | .mid_rid = 0x2d, | 374 | .mid_rid = 0x2d, |
399 | }, { | 375 | }, { |
400 | .slave_id = SHDMA_SLAVE_SCIF3_RX, | 376 | .slave_id = SHDMA_SLAVE_SCIF3_RX, |
401 | .addr = 0xe6c70024, | 377 | .addr = 0xe6c70024, |
402 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 378 | .chcr = CHCR_RX(XMIT_SZ_8BIT), |
403 | .mid_rid = 0x2e, | 379 | .mid_rid = 0x2e, |
404 | }, { | 380 | }, { |
405 | .slave_id = SHDMA_SLAVE_SCIF4_TX, | 381 | .slave_id = SHDMA_SLAVE_SCIF4_TX, |
406 | .addr = 0xe6c80020, | 382 | .addr = 0xe6c80020, |
407 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 383 | .chcr = CHCR_TX(XMIT_SZ_8BIT), |
408 | .mid_rid = 0x39, | 384 | .mid_rid = 0x39, |
409 | }, { | 385 | }, { |
410 | .slave_id = SHDMA_SLAVE_SCIF4_RX, | 386 | .slave_id = SHDMA_SLAVE_SCIF4_RX, |
411 | .addr = 0xe6c80024, | 387 | .addr = 0xe6c80024, |
412 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 388 | .chcr = CHCR_RX(XMIT_SZ_8BIT), |
413 | .mid_rid = 0x3a, | 389 | .mid_rid = 0x3a, |
414 | }, { | 390 | }, { |
415 | .slave_id = SHDMA_SLAVE_SCIF5_TX, | 391 | .slave_id = SHDMA_SLAVE_SCIF5_TX, |
416 | .addr = 0xe6cb0020, | 392 | .addr = 0xe6cb0020, |
417 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 393 | .chcr = CHCR_TX(XMIT_SZ_8BIT), |
418 | .mid_rid = 0x35, | 394 | .mid_rid = 0x35, |
419 | }, { | 395 | }, { |
420 | .slave_id = SHDMA_SLAVE_SCIF5_RX, | 396 | .slave_id = SHDMA_SLAVE_SCIF5_RX, |
421 | .addr = 0xe6cb0024, | 397 | .addr = 0xe6cb0024, |
422 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 398 | .chcr = CHCR_RX(XMIT_SZ_8BIT), |
423 | .mid_rid = 0x36, | 399 | .mid_rid = 0x36, |
424 | }, { | 400 | }, { |
425 | .slave_id = SHDMA_SLAVE_SCIF6_TX, | 401 | .slave_id = SHDMA_SLAVE_SCIF6_TX, |
426 | .addr = 0xe6c30040, | 402 | .addr = 0xe6c30040, |
427 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 403 | .chcr = CHCR_TX(XMIT_SZ_8BIT), |
428 | .mid_rid = 0x3d, | 404 | .mid_rid = 0x3d, |
429 | }, { | 405 | }, { |
430 | .slave_id = SHDMA_SLAVE_SCIF6_RX, | 406 | .slave_id = SHDMA_SLAVE_SCIF6_RX, |
431 | .addr = 0xe6c30060, | 407 | .addr = 0xe6c30060, |
432 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 408 | .chcr = CHCR_RX(XMIT_SZ_8BIT), |
433 | .mid_rid = 0x3e, | 409 | .mid_rid = 0x3e, |
434 | }, { | 410 | }, { |
435 | .slave_id = SHDMA_SLAVE_SDHI0_TX, | 411 | .slave_id = SHDMA_SLAVE_SDHI0_TX, |
436 | .addr = 0xe6850030, | 412 | .addr = 0xe6850030, |
437 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), | 413 | .chcr = CHCR_TX(XMIT_SZ_16BIT), |
438 | .mid_rid = 0xc1, | 414 | .mid_rid = 0xc1, |
439 | }, { | 415 | }, { |
440 | .slave_id = SHDMA_SLAVE_SDHI0_RX, | 416 | .slave_id = SHDMA_SLAVE_SDHI0_RX, |
441 | .addr = 0xe6850030, | 417 | .addr = 0xe6850030, |
442 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), | 418 | .chcr = CHCR_RX(XMIT_SZ_16BIT), |
443 | .mid_rid = 0xc2, | 419 | .mid_rid = 0xc2, |
444 | }, { | 420 | }, { |
445 | .slave_id = SHDMA_SLAVE_SDHI1_TX, | 421 | .slave_id = SHDMA_SLAVE_SDHI1_TX, |
446 | .addr = 0xe6860030, | 422 | .addr = 0xe6860030, |
447 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), | 423 | .chcr = CHCR_TX(XMIT_SZ_16BIT), |
448 | .mid_rid = 0xc9, | 424 | .mid_rid = 0xc9, |
449 | }, { | 425 | }, { |
450 | .slave_id = SHDMA_SLAVE_SDHI1_RX, | 426 | .slave_id = SHDMA_SLAVE_SDHI1_RX, |
451 | .addr = 0xe6860030, | 427 | .addr = 0xe6860030, |
452 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), | 428 | .chcr = CHCR_RX(XMIT_SZ_16BIT), |
453 | .mid_rid = 0xca, | 429 | .mid_rid = 0xca, |
454 | }, { | 430 | }, { |
455 | .slave_id = SHDMA_SLAVE_SDHI2_TX, | 431 | .slave_id = SHDMA_SLAVE_SDHI2_TX, |
456 | .addr = 0xe6870030, | 432 | .addr = 0xe6870030, |
457 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), | 433 | .chcr = CHCR_TX(XMIT_SZ_16BIT), |
458 | .mid_rid = 0xcd, | 434 | .mid_rid = 0xcd, |
459 | }, { | 435 | }, { |
460 | .slave_id = SHDMA_SLAVE_SDHI2_RX, | 436 | .slave_id = SHDMA_SLAVE_SDHI2_RX, |
461 | .addr = 0xe6870030, | 437 | .addr = 0xe6870030, |
462 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), | 438 | .chcr = CHCR_RX(XMIT_SZ_16BIT), |
463 | .mid_rid = 0xce, | 439 | .mid_rid = 0xce, |
464 | }, { | 440 | }, { |
465 | .slave_id = SHDMA_SLAVE_FSIA_TX, | 441 | .slave_id = SHDMA_SLAVE_FSIA_TX, |
466 | .addr = 0xfe1f0024, | 442 | .addr = 0xfe1f0024, |
467 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), | 443 | .chcr = CHCR_TX(XMIT_SZ_32BIT), |
468 | .mid_rid = 0xb1, | 444 | .mid_rid = 0xb1, |
469 | }, { | 445 | }, { |
470 | .slave_id = SHDMA_SLAVE_FSIA_RX, | 446 | .slave_id = SHDMA_SLAVE_FSIA_RX, |
471 | .addr = 0xfe1f0020, | 447 | .addr = 0xfe1f0020, |
472 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), | 448 | .chcr = CHCR_RX(XMIT_SZ_32BIT), |
473 | .mid_rid = 0xb2, | 449 | .mid_rid = 0xb2, |
474 | }, { | 450 | }, { |
475 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | 451 | .slave_id = SHDMA_SLAVE_MMCIF_TX, |
476 | .addr = 0xe6bd0034, | 452 | .addr = 0xe6bd0034, |
477 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), | 453 | .chcr = CHCR_TX(XMIT_SZ_32BIT), |
478 | .mid_rid = 0xd1, | 454 | .mid_rid = 0xd1, |
479 | }, { | 455 | }, { |
480 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | 456 | .slave_id = SHDMA_SLAVE_MMCIF_RX, |
481 | .addr = 0xe6bd0034, | 457 | .addr = 0xe6bd0034, |
482 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), | 458 | .chcr = CHCR_RX(XMIT_SZ_32BIT), |
483 | .mid_rid = 0xd2, | 459 | .mid_rid = 0xd2, |
484 | }, | 460 | }, |
485 | }; | 461 | }; |
@@ -520,19 +496,17 @@ static const struct sh_dmae_channel sh7372_dmae_channels[] = { | |||
520 | } | 496 | } |
521 | }; | 497 | }; |
522 | 498 | ||
523 | static const unsigned int ts_shift[] = TS_SHIFT; | ||
524 | |||
525 | static struct sh_dmae_pdata dma_platform_data = { | 499 | static struct sh_dmae_pdata dma_platform_data = { |
526 | .slave = sh7372_dmae_slaves, | 500 | .slave = sh7372_dmae_slaves, |
527 | .slave_num = ARRAY_SIZE(sh7372_dmae_slaves), | 501 | .slave_num = ARRAY_SIZE(sh7372_dmae_slaves), |
528 | .channel = sh7372_dmae_channels, | 502 | .channel = sh7372_dmae_channels, |
529 | .channel_num = ARRAY_SIZE(sh7372_dmae_channels), | 503 | .channel_num = ARRAY_SIZE(sh7372_dmae_channels), |
530 | .ts_low_shift = 3, | 504 | .ts_low_shift = TS_LOW_SHIFT, |
531 | .ts_low_mask = 0x18, | 505 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, |
532 | .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */ | 506 | .ts_high_shift = TS_HI_SHIFT, |
533 | .ts_high_mask = 0x00300000, | 507 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, |
534 | .ts_shift = ts_shift, | 508 | .ts_shift = dma_ts_shift, |
535 | .ts_shift_num = ARRAY_SIZE(ts_shift), | 509 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), |
536 | .dmaor_init = DMAOR_DME, | 510 | .dmaor_init = DMAOR_DME, |
537 | .chclr_present = 1, | 511 | .chclr_present = 1, |
538 | }; | 512 | }; |
@@ -654,17 +628,6 @@ static struct platform_device dma2_device = { | |||
654 | /* | 628 | /* |
655 | * USB-DMAC | 629 | * USB-DMAC |
656 | */ | 630 | */ |
657 | |||
658 | unsigned int usbts_shift[] = {3, 4, 5}; | ||
659 | |||
660 | enum { | ||
661 | XMIT_SZ_8BYTE = 0, | ||
662 | XMIT_SZ_16BYTE = 1, | ||
663 | XMIT_SZ_32BYTE = 2, | ||
664 | }; | ||
665 | |||
666 | #define USBTS_INDEX2VAL(i) (((i) & 3) << 6) | ||
667 | |||
668 | static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = { | 631 | static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = { |
669 | { | 632 | { |
670 | .offset = 0, | 633 | .offset = 0, |
@@ -677,10 +640,10 @@ static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = { | |||
677 | static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = { | 640 | static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = { |
678 | { | 641 | { |
679 | .slave_id = SHDMA_SLAVE_USB0_TX, | 642 | .slave_id = SHDMA_SLAVE_USB0_TX, |
680 | .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), | 643 | .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), |
681 | }, { | 644 | }, { |
682 | .slave_id = SHDMA_SLAVE_USB0_RX, | 645 | .slave_id = SHDMA_SLAVE_USB0_RX, |
683 | .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), | 646 | .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), |
684 | }, | 647 | }, |
685 | }; | 648 | }; |
686 | 649 | ||
@@ -689,12 +652,12 @@ static struct sh_dmae_pdata usb_dma0_platform_data = { | |||
689 | .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves), | 652 | .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves), |
690 | .channel = sh7372_usb_dmae_channels, | 653 | .channel = sh7372_usb_dmae_channels, |
691 | .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), | 654 | .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), |
692 | .ts_low_shift = 6, | 655 | .ts_low_shift = USBTS_LOW_SHIFT, |
693 | .ts_low_mask = 0xc0, | 656 | .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT, |
694 | .ts_high_shift = 0, | 657 | .ts_high_shift = USBTS_HI_SHIFT, |
695 | .ts_high_mask = 0, | 658 | .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT, |
696 | .ts_shift = usbts_shift, | 659 | .ts_shift = dma_usbts_shift, |
697 | .ts_shift_num = ARRAY_SIZE(usbts_shift), | 660 | .ts_shift_num = ARRAY_SIZE(dma_usbts_shift), |
698 | .dmaor_init = DMAOR_DME, | 661 | .dmaor_init = DMAOR_DME, |
699 | .chcr_offset = 0x14, | 662 | .chcr_offset = 0x14, |
700 | .chcr_ie_bit = 1 << 5, | 663 | .chcr_ie_bit = 1 << 5, |
@@ -739,10 +702,10 @@ static struct platform_device usb_dma0_device = { | |||
739 | static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = { | 702 | static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = { |
740 | { | 703 | { |
741 | .slave_id = SHDMA_SLAVE_USB1_TX, | 704 | .slave_id = SHDMA_SLAVE_USB1_TX, |
742 | .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), | 705 | .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), |
743 | }, { | 706 | }, { |
744 | .slave_id = SHDMA_SLAVE_USB1_RX, | 707 | .slave_id = SHDMA_SLAVE_USB1_RX, |
745 | .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), | 708 | .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), |
746 | }, | 709 | }, |
747 | }; | 710 | }; |
748 | 711 | ||
@@ -751,12 +714,12 @@ static struct sh_dmae_pdata usb_dma1_platform_data = { | |||
751 | .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves), | 714 | .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves), |
752 | .channel = sh7372_usb_dmae_channels, | 715 | .channel = sh7372_usb_dmae_channels, |
753 | .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), | 716 | .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), |
754 | .ts_low_shift = 6, | 717 | .ts_low_shift = USBTS_LOW_SHIFT, |
755 | .ts_low_mask = 0xc0, | 718 | .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT, |
756 | .ts_high_shift = 0, | 719 | .ts_high_shift = USBTS_HI_SHIFT, |
757 | .ts_high_mask = 0, | 720 | .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT, |
758 | .ts_shift = usbts_shift, | 721 | .ts_shift = dma_usbts_shift, |
759 | .ts_shift_num = ARRAY_SIZE(usbts_shift), | 722 | .ts_shift_num = ARRAY_SIZE(dma_usbts_shift), |
760 | .dmaor_init = DMAOR_DME, | 723 | .dmaor_init = DMAOR_DME, |
761 | .chcr_offset = 0x14, | 724 | .chcr_offset = 0x14, |
762 | .chcr_ie_bit = 1 << 5, | 725 | .chcr_ie_bit = 1 << 5, |
@@ -1038,21 +1001,21 @@ static struct platform_device *sh7372_late_devices[] __initdata = { | |||
1038 | 1001 | ||
1039 | void __init sh7372_add_standard_devices(void) | 1002 | void __init sh7372_add_standard_devices(void) |
1040 | { | 1003 | { |
1041 | sh7372_init_pm_domain(&sh7372_a4lc); | 1004 | rmobile_init_pm_domain(&sh7372_pd_a4lc); |
1042 | sh7372_init_pm_domain(&sh7372_a4mp); | 1005 | rmobile_init_pm_domain(&sh7372_pd_a4mp); |
1043 | sh7372_init_pm_domain(&sh7372_d4); | 1006 | rmobile_init_pm_domain(&sh7372_pd_d4); |
1044 | sh7372_init_pm_domain(&sh7372_a4r); | 1007 | rmobile_init_pm_domain(&sh7372_pd_a4r); |
1045 | sh7372_init_pm_domain(&sh7372_a3rv); | 1008 | rmobile_init_pm_domain(&sh7372_pd_a3rv); |
1046 | sh7372_init_pm_domain(&sh7372_a3ri); | 1009 | rmobile_init_pm_domain(&sh7372_pd_a3ri); |
1047 | sh7372_init_pm_domain(&sh7372_a4s); | 1010 | rmobile_init_pm_domain(&sh7372_pd_a4s); |
1048 | sh7372_init_pm_domain(&sh7372_a3sp); | 1011 | rmobile_init_pm_domain(&sh7372_pd_a3sp); |
1049 | sh7372_init_pm_domain(&sh7372_a3sg); | 1012 | rmobile_init_pm_domain(&sh7372_pd_a3sg); |
1050 | 1013 | ||
1051 | sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv); | 1014 | rmobile_pm_add_subdomain(&sh7372_pd_a4lc, &sh7372_pd_a3rv); |
1052 | sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc); | 1015 | rmobile_pm_add_subdomain(&sh7372_pd_a4r, &sh7372_pd_a4lc); |
1053 | 1016 | ||
1054 | sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg); | 1017 | rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sg); |
1055 | sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp); | 1018 | rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sp); |
1056 | 1019 | ||
1057 | platform_add_devices(sh7372_early_devices, | 1020 | platform_add_devices(sh7372_early_devices, |
1058 | ARRAY_SIZE(sh7372_early_devices)); | 1021 | ARRAY_SIZE(sh7372_early_devices)); |
@@ -1060,30 +1023,30 @@ void __init sh7372_add_standard_devices(void) | |||
1060 | platform_add_devices(sh7372_late_devices, | 1023 | platform_add_devices(sh7372_late_devices, |
1061 | ARRAY_SIZE(sh7372_late_devices)); | 1024 | ARRAY_SIZE(sh7372_late_devices)); |
1062 | 1025 | ||
1063 | sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device); | 1026 | rmobile_add_device_to_domain(&sh7372_pd_a3rv, &vpu_device); |
1064 | sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device); | 1027 | rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu0_device); |
1065 | sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device); | 1028 | rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu1_device); |
1066 | sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device); | 1029 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif0_device); |
1067 | sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device); | 1030 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif1_device); |
1068 | sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device); | 1031 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif2_device); |
1069 | sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device); | 1032 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif3_device); |
1070 | sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device); | 1033 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif4_device); |
1071 | sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device); | 1034 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif5_device); |
1072 | sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device); | 1035 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif6_device); |
1073 | sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device); | 1036 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &iic1_device); |
1074 | sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device); | 1037 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma0_device); |
1075 | sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device); | 1038 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma1_device); |
1076 | sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device); | 1039 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma2_device); |
1077 | sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device); | 1040 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma0_device); |
1078 | sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device); | 1041 | rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma1_device); |
1079 | sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device); | 1042 | rmobile_add_device_to_domain(&sh7372_pd_a4r, &iic0_device); |
1080 | sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device); | 1043 | rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu0_device); |
1081 | sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device); | 1044 | rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu1_device); |
1082 | sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device); | 1045 | rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu2_device); |
1083 | sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device); | 1046 | rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu3_device); |
1084 | sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device); | 1047 | rmobile_add_device_to_domain(&sh7372_pd_a4r, &jpu_device); |
1085 | sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device); | 1048 | rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu00_device); |
1086 | sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device); | 1049 | rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu01_device); |
1087 | } | 1050 | } |
1088 | 1051 | ||
1089 | static void __init sh7372_earlytimer_init(void) | 1052 | static void __init sh7372_earlytimer_init(void) |