diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-03-02 08:05:00 -0500 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2012-03-02 08:05:00 -0500 |
commit | 1220547bfd7f7dd97f770a04b533323e5404b8e9 (patch) | |
tree | a4231b9570f3302f032a2d757fb3af24a4238d46 /arch/arm | |
parent | a26d3c4fcd4bb875ae5adc32f27fab7a478bb00d (diff) | |
parent | f86bcc302a8c570dd0f5a50097a6af96a0e717c2 (diff) |
Merge branch 'depends/omap/gpio/runtime-pm-cleanup' into next/cleanup
Conflicts:
arch/arm/mach-omap1/gpio16xx.c
drivers/gpio/gpio-omap.c
Merge in the runtime-pm-cleanup branch from the gpio tree into
next/cleanup, this resolves a nonobvious merge conflict between
the two branches. Both branches move parts of the gpio-omap
driver into platform code, this takes the superset of both
changes.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-omap1/gpio15xx.c | 7 | ||||
-rw-r--r-- | arch/arm/mach-omap1/gpio16xx.c | 40 | ||||
-rw-r--r-- | arch/arm/mach-omap1/gpio7xx.c | 14 | ||||
-rw-r--r-- | arch/arm/mach-omap2/gpio.c | 36 | ||||
-rw-r--r-- | arch/arm/mach-omap2/pm34xx.c | 14 | ||||
-rw-r--r-- | arch/arm/plat-omap/include/plat/gpio.h | 29 |
6 files changed, 87 insertions, 53 deletions
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c index 399da4ce017b..634903ef8292 100644 --- a/arch/arm/mach-omap1/gpio15xx.c +++ b/arch/arm/mach-omap1/gpio15xx.c | |||
@@ -42,11 +42,12 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = { | |||
42 | .irqstatus = OMAP_MPUIO_GPIO_INT, | 42 | .irqstatus = OMAP_MPUIO_GPIO_INT, |
43 | .irqenable = OMAP_MPUIO_GPIO_MASKIT, | 43 | .irqenable = OMAP_MPUIO_GPIO_MASKIT, |
44 | .irqenable_inv = true, | 44 | .irqenable_inv = true, |
45 | .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE, | ||
45 | }; | 46 | }; |
46 | 47 | ||
47 | static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = { | 48 | static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = { |
48 | .virtual_irq_start = IH_MPUIO_BASE, | 49 | .virtual_irq_start = IH_MPUIO_BASE, |
49 | .bank_type = METHOD_MPUIO, | 50 | .is_mpuio = true, |
50 | .bank_width = 16, | 51 | .bank_width = 16, |
51 | .bank_stride = 1, | 52 | .bank_stride = 1, |
52 | .regs = &omap15xx_mpuio_regs, | 53 | .regs = &omap15xx_mpuio_regs, |
@@ -83,11 +84,12 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = { | |||
83 | .irqstatus = OMAP1510_GPIO_INT_STATUS, | 84 | .irqstatus = OMAP1510_GPIO_INT_STATUS, |
84 | .irqenable = OMAP1510_GPIO_INT_MASK, | 85 | .irqenable = OMAP1510_GPIO_INT_MASK, |
85 | .irqenable_inv = true, | 86 | .irqenable_inv = true, |
87 | .irqctrl = OMAP1510_GPIO_INT_CONTROL, | ||
88 | .pinctrl = OMAP1510_GPIO_PIN_CONTROL, | ||
86 | }; | 89 | }; |
87 | 90 | ||
88 | static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = { | 91 | static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = { |
89 | .virtual_irq_start = IH_GPIO_BASE, | 92 | .virtual_irq_start = IH_GPIO_BASE, |
90 | .bank_type = METHOD_GPIO_1510, | ||
91 | .bank_width = 16, | 93 | .bank_width = 16, |
92 | .regs = &omap15xx_gpio_regs, | 94 | .regs = &omap15xx_gpio_regs, |
93 | }; | 95 | }; |
@@ -115,7 +117,6 @@ static int __init omap15xx_gpio_init(void) | |||
115 | platform_device_register(&omap15xx_mpu_gpio); | 117 | platform_device_register(&omap15xx_mpu_gpio); |
116 | platform_device_register(&omap15xx_gpio); | 118 | platform_device_register(&omap15xx_gpio); |
117 | 119 | ||
118 | gpio_bank_count = 2; | ||
119 | return 0; | 120 | return 0; |
120 | } | 121 | } |
121 | postcore_initcall(omap15xx_gpio_init); | 122 | postcore_initcall(omap15xx_gpio_init); |
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c index 99cabc498ab5..1fb3b9ad496e 100644 --- a/arch/arm/mach-omap1/gpio16xx.c +++ b/arch/arm/mach-omap1/gpio16xx.c | |||
@@ -24,6 +24,9 @@ | |||
24 | #define OMAP1610_GPIO4_BASE 0xfffbbc00 | 24 | #define OMAP1610_GPIO4_BASE 0xfffbbc00 |
25 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE | 25 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE |
26 | 26 | ||
27 | /* smart idle, enable wakeup */ | ||
28 | #define SYSCONFIG_WORD 0x14 | ||
29 | |||
27 | /* mpu gpio */ | 30 | /* mpu gpio */ |
28 | static struct __initdata resource omap16xx_mpu_gpio_resources[] = { | 31 | static struct __initdata resource omap16xx_mpu_gpio_resources[] = { |
29 | { | 32 | { |
@@ -45,11 +48,12 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = { | |||
45 | .irqstatus = OMAP_MPUIO_GPIO_INT, | 48 | .irqstatus = OMAP_MPUIO_GPIO_INT, |
46 | .irqenable = OMAP_MPUIO_GPIO_MASKIT, | 49 | .irqenable = OMAP_MPUIO_GPIO_MASKIT, |
47 | .irqenable_inv = true, | 50 | .irqenable_inv = true, |
51 | .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE, | ||
48 | }; | 52 | }; |
49 | 53 | ||
50 | static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { | 54 | static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { |
51 | .virtual_irq_start = IH_MPUIO_BASE, | 55 | .virtual_irq_start = IH_MPUIO_BASE, |
52 | .bank_type = METHOD_MPUIO, | 56 | .is_mpuio = true, |
53 | .bank_width = 16, | 57 | .bank_width = 16, |
54 | .bank_stride = 1, | 58 | .bank_stride = 1, |
55 | .regs = &omap16xx_mpuio_regs, | 59 | .regs = &omap16xx_mpuio_regs, |
@@ -89,11 +93,13 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = { | |||
89 | .irqenable = OMAP1610_GPIO_IRQENABLE1, | 93 | .irqenable = OMAP1610_GPIO_IRQENABLE1, |
90 | .set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1, | 94 | .set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1, |
91 | .clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1, | 95 | .clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1, |
96 | .wkup_en = OMAP1610_GPIO_WAKEUPENABLE, | ||
97 | .edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1, | ||
98 | .edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2, | ||
92 | }; | 99 | }; |
93 | 100 | ||
94 | static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { | 101 | static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { |
95 | .virtual_irq_start = IH_GPIO_BASE, | 102 | .virtual_irq_start = IH_GPIO_BASE, |
96 | .bank_type = METHOD_GPIO_1610, | ||
97 | .bank_width = 16, | 103 | .bank_width = 16, |
98 | .regs = &omap16xx_gpio_regs, | 104 | .regs = &omap16xx_gpio_regs, |
99 | }; | 105 | }; |
@@ -123,7 +129,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = { | |||
123 | 129 | ||
124 | static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { | 130 | static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { |
125 | .virtual_irq_start = IH_GPIO_BASE + 16, | 131 | .virtual_irq_start = IH_GPIO_BASE + 16, |
126 | .bank_type = METHOD_GPIO_1610, | ||
127 | .bank_width = 16, | 132 | .bank_width = 16, |
128 | .regs = &omap16xx_gpio_regs, | 133 | .regs = &omap16xx_gpio_regs, |
129 | }; | 134 | }; |
@@ -153,7 +158,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = { | |||
153 | 158 | ||
154 | static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { | 159 | static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { |
155 | .virtual_irq_start = IH_GPIO_BASE + 32, | 160 | .virtual_irq_start = IH_GPIO_BASE + 32, |
156 | .bank_type = METHOD_GPIO_1610, | ||
157 | .bank_width = 16, | 161 | .bank_width = 16, |
158 | .regs = &omap16xx_gpio_regs, | 162 | .regs = &omap16xx_gpio_regs, |
159 | }; | 163 | }; |
@@ -183,7 +187,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = { | |||
183 | 187 | ||
184 | static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { | 188 | static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { |
185 | .virtual_irq_start = IH_GPIO_BASE + 48, | 189 | .virtual_irq_start = IH_GPIO_BASE + 48, |
186 | .bank_type = METHOD_GPIO_1610, | ||
187 | .bank_width = 16, | 190 | .bank_width = 16, |
188 | .regs = &omap16xx_gpio_regs, | 191 | .regs = &omap16xx_gpio_regs, |
189 | }; | 192 | }; |
@@ -214,6 +217,10 @@ static struct __initdata platform_device * omap16xx_gpio_dev[] = { | |||
214 | static int __init omap16xx_gpio_init(void) | 217 | static int __init omap16xx_gpio_init(void) |
215 | { | 218 | { |
216 | int i; | 219 | int i; |
220 | void __iomem *base; | ||
221 | struct resource *res; | ||
222 | struct platform_device *pdev; | ||
223 | struct omap_gpio_platform_data *pdata; | ||
217 | 224 | ||
218 | if (!cpu_is_omap16xx()) | 225 | if (!cpu_is_omap16xx()) |
219 | return -EINVAL; | 226 | return -EINVAL; |
@@ -225,10 +232,27 @@ static int __init omap16xx_gpio_init(void) | |||
225 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, | 232 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, |
226 | ULPD_CAM_CLK_CTRL); | 233 | ULPD_CAM_CLK_CTRL); |
227 | 234 | ||
228 | for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) | 235 | for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) { |
229 | platform_device_register(omap16xx_gpio_dev[i]); | 236 | pdev = omap16xx_gpio_dev[i]; |
237 | pdata = pdev->dev.platform_data; | ||
238 | |||
239 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
240 | if (unlikely(!res)) { | ||
241 | dev_err(&pdev->dev, "Invalid mem resource.\n"); | ||
242 | return -ENODEV; | ||
243 | } | ||
230 | 244 | ||
231 | gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev); | 245 | base = ioremap(res->start, resource_size(res)); |
246 | if (unlikely(!base)) { | ||
247 | dev_err(&pdev->dev, "ioremap failed.\n"); | ||
248 | return -ENOMEM; | ||
249 | } | ||
250 | |||
251 | __raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG); | ||
252 | iounmap(base); | ||
253 | |||
254 | platform_device_register(omap16xx_gpio_dev[i]); | ||
255 | } | ||
232 | 256 | ||
233 | return 0; | 257 | return 0; |
234 | } | 258 | } |
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c index 5ab63eab0ff5..4771d6b68b96 100644 --- a/arch/arm/mach-omap1/gpio7xx.c +++ b/arch/arm/mach-omap1/gpio7xx.c | |||
@@ -47,12 +47,13 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = { | |||
47 | .irqstatus = OMAP_MPUIO_GPIO_INT / 2, | 47 | .irqstatus = OMAP_MPUIO_GPIO_INT / 2, |
48 | .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2, | 48 | .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2, |
49 | .irqenable_inv = true, | 49 | .irqenable_inv = true, |
50 | .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1, | ||
50 | }; | 51 | }; |
51 | 52 | ||
52 | static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { | 53 | static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { |
53 | .virtual_irq_start = IH_MPUIO_BASE, | 54 | .virtual_irq_start = IH_MPUIO_BASE, |
54 | .bank_type = METHOD_MPUIO, | 55 | .is_mpuio = true, |
55 | .bank_width = 32, | 56 | .bank_width = 16, |
56 | .bank_stride = 2, | 57 | .bank_stride = 2, |
57 | .regs = &omap7xx_mpuio_regs, | 58 | .regs = &omap7xx_mpuio_regs, |
58 | }; | 59 | }; |
@@ -88,11 +89,11 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = { | |||
88 | .irqstatus = OMAP7XX_GPIO_INT_STATUS, | 89 | .irqstatus = OMAP7XX_GPIO_INT_STATUS, |
89 | .irqenable = OMAP7XX_GPIO_INT_MASK, | 90 | .irqenable = OMAP7XX_GPIO_INT_MASK, |
90 | .irqenable_inv = true, | 91 | .irqenable_inv = true, |
92 | .irqctrl = OMAP7XX_GPIO_INT_CONTROL, | ||
91 | }; | 93 | }; |
92 | 94 | ||
93 | static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { | 95 | static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { |
94 | .virtual_irq_start = IH_GPIO_BASE, | 96 | .virtual_irq_start = IH_GPIO_BASE, |
95 | .bank_type = METHOD_GPIO_7XX, | ||
96 | .bank_width = 32, | 97 | .bank_width = 32, |
97 | .regs = &omap7xx_gpio_regs, | 98 | .regs = &omap7xx_gpio_regs, |
98 | }; | 99 | }; |
@@ -122,7 +123,6 @@ static struct __initdata resource omap7xx_gpio2_resources[] = { | |||
122 | 123 | ||
123 | static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = { | 124 | static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = { |
124 | .virtual_irq_start = IH_GPIO_BASE + 32, | 125 | .virtual_irq_start = IH_GPIO_BASE + 32, |
125 | .bank_type = METHOD_GPIO_7XX, | ||
126 | .bank_width = 32, | 126 | .bank_width = 32, |
127 | .regs = &omap7xx_gpio_regs, | 127 | .regs = &omap7xx_gpio_regs, |
128 | }; | 128 | }; |
@@ -152,7 +152,6 @@ static struct __initdata resource omap7xx_gpio3_resources[] = { | |||
152 | 152 | ||
153 | static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = { | 153 | static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = { |
154 | .virtual_irq_start = IH_GPIO_BASE + 64, | 154 | .virtual_irq_start = IH_GPIO_BASE + 64, |
155 | .bank_type = METHOD_GPIO_7XX, | ||
156 | .bank_width = 32, | 155 | .bank_width = 32, |
157 | .regs = &omap7xx_gpio_regs, | 156 | .regs = &omap7xx_gpio_regs, |
158 | }; | 157 | }; |
@@ -182,7 +181,6 @@ static struct __initdata resource omap7xx_gpio4_resources[] = { | |||
182 | 181 | ||
183 | static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = { | 182 | static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = { |
184 | .virtual_irq_start = IH_GPIO_BASE + 96, | 183 | .virtual_irq_start = IH_GPIO_BASE + 96, |
185 | .bank_type = METHOD_GPIO_7XX, | ||
186 | .bank_width = 32, | 184 | .bank_width = 32, |
187 | .regs = &omap7xx_gpio_regs, | 185 | .regs = &omap7xx_gpio_regs, |
188 | }; | 186 | }; |
@@ -212,7 +210,6 @@ static struct __initdata resource omap7xx_gpio5_resources[] = { | |||
212 | 210 | ||
213 | static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = { | 211 | static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = { |
214 | .virtual_irq_start = IH_GPIO_BASE + 128, | 212 | .virtual_irq_start = IH_GPIO_BASE + 128, |
215 | .bank_type = METHOD_GPIO_7XX, | ||
216 | .bank_width = 32, | 213 | .bank_width = 32, |
217 | .regs = &omap7xx_gpio_regs, | 214 | .regs = &omap7xx_gpio_regs, |
218 | }; | 215 | }; |
@@ -242,7 +239,6 @@ static struct __initdata resource omap7xx_gpio6_resources[] = { | |||
242 | 239 | ||
243 | static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = { | 240 | static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = { |
244 | .virtual_irq_start = IH_GPIO_BASE + 160, | 241 | .virtual_irq_start = IH_GPIO_BASE + 160, |
245 | .bank_type = METHOD_GPIO_7XX, | ||
246 | .bank_width = 32, | 242 | .bank_width = 32, |
247 | .regs = &omap7xx_gpio_regs, | 243 | .regs = &omap7xx_gpio_regs, |
248 | }; | 244 | }; |
@@ -282,8 +278,6 @@ static int __init omap7xx_gpio_init(void) | |||
282 | for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++) | 278 | for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++) |
283 | platform_device_register(omap7xx_gpio_dev[i]); | 279 | platform_device_register(omap7xx_gpio_dev[i]); |
284 | 280 | ||
285 | gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev); | ||
286 | |||
287 | return 0; | 281 | return 0; |
288 | } | 282 | } |
289 | postcore_initcall(omap7xx_gpio_init); | 283 | postcore_initcall(omap7xx_gpio_init); |
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 8cbfbc2918ce..1e0b750afcaa 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c | |||
@@ -23,6 +23,9 @@ | |||
23 | 23 | ||
24 | #include <plat/omap_hwmod.h> | 24 | #include <plat/omap_hwmod.h> |
25 | #include <plat/omap_device.h> | 25 | #include <plat/omap_device.h> |
26 | #include <plat/omap-pm.h> | ||
27 | |||
28 | #include "powerdomain.h" | ||
26 | 29 | ||
27 | static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | 30 | static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) |
28 | { | 31 | { |
@@ -31,6 +34,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | |||
31 | struct omap_gpio_dev_attr *dev_attr; | 34 | struct omap_gpio_dev_attr *dev_attr; |
32 | char *name = "omap_gpio"; | 35 | char *name = "omap_gpio"; |
33 | int id; | 36 | int id; |
37 | struct powerdomain *pwrdm; | ||
34 | 38 | ||
35 | /* | 39 | /* |
36 | * extract the device id from name field available in the | 40 | * extract the device id from name field available in the |
@@ -52,7 +56,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | |||
52 | pdata->bank_width = dev_attr->bank_width; | 56 | pdata->bank_width = dev_attr->bank_width; |
53 | pdata->dbck_flag = dev_attr->dbck_flag; | 57 | pdata->dbck_flag = dev_attr->dbck_flag; |
54 | pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1); | 58 | pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1); |
55 | 59 | pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; | |
56 | pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); | 60 | pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); |
57 | if (!pdata) { | 61 | if (!pdata) { |
58 | pr_err("gpio%d: Memory allocation failed\n", id); | 62 | pr_err("gpio%d: Memory allocation failed\n", id); |
@@ -61,8 +65,15 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | |||
61 | 65 | ||
62 | switch (oh->class->rev) { | 66 | switch (oh->class->rev) { |
63 | case 0: | 67 | case 0: |
68 | if (id == 1) | ||
69 | /* non-wakeup GPIO pins for OMAP2 Bank1 */ | ||
70 | pdata->non_wakeup_gpios = 0xe203ffc0; | ||
71 | else if (id == 2) | ||
72 | /* non-wakeup GPIO pins for OMAP2 Bank2 */ | ||
73 | pdata->non_wakeup_gpios = 0x08700040; | ||
74 | /* fall through */ | ||
75 | |||
64 | case 1: | 76 | case 1: |
65 | pdata->bank_type = METHOD_GPIO_24XX; | ||
66 | pdata->regs->revision = OMAP24XX_GPIO_REVISION; | 77 | pdata->regs->revision = OMAP24XX_GPIO_REVISION; |
67 | pdata->regs->direction = OMAP24XX_GPIO_OE; | 78 | pdata->regs->direction = OMAP24XX_GPIO_OE; |
68 | pdata->regs->datain = OMAP24XX_GPIO_DATAIN; | 79 | pdata->regs->datain = OMAP24XX_GPIO_DATAIN; |
@@ -72,13 +83,19 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | |||
72 | pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1; | 83 | pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1; |
73 | pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2; | 84 | pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2; |
74 | pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1; | 85 | pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1; |
86 | pdata->regs->irqenable2 = OMAP24XX_GPIO_IRQENABLE2; | ||
75 | pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1; | 87 | pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1; |
76 | pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1; | 88 | pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1; |
77 | pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL; | 89 | pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL; |
78 | pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN; | 90 | pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN; |
91 | pdata->regs->ctrl = OMAP24XX_GPIO_CTRL; | ||
92 | pdata->regs->wkup_en = OMAP24XX_GPIO_WAKE_EN; | ||
93 | pdata->regs->leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0; | ||
94 | pdata->regs->leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1; | ||
95 | pdata->regs->risingdetect = OMAP24XX_GPIO_RISINGDETECT; | ||
96 | pdata->regs->fallingdetect = OMAP24XX_GPIO_FALLINGDETECT; | ||
79 | break; | 97 | break; |
80 | case 2: | 98 | case 2: |
81 | pdata->bank_type = METHOD_GPIO_44XX; | ||
82 | pdata->regs->revision = OMAP4_GPIO_REVISION; | 99 | pdata->regs->revision = OMAP4_GPIO_REVISION; |
83 | pdata->regs->direction = OMAP4_GPIO_OE; | 100 | pdata->regs->direction = OMAP4_GPIO_OE; |
84 | pdata->regs->datain = OMAP4_GPIO_DATAIN; | 101 | pdata->regs->datain = OMAP4_GPIO_DATAIN; |
@@ -88,10 +105,17 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | |||
88 | pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0; | 105 | pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0; |
89 | pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1; | 106 | pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1; |
90 | pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0; | 107 | pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0; |
108 | pdata->regs->irqenable2 = OMAP4_GPIO_IRQSTATUSSET1; | ||
91 | pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0; | 109 | pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0; |
92 | pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0; | 110 | pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0; |
93 | pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME; | 111 | pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME; |
94 | pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE; | 112 | pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE; |
113 | pdata->regs->ctrl = OMAP4_GPIO_CTRL; | ||
114 | pdata->regs->wkup_en = OMAP4_GPIO_IRQWAKEN0; | ||
115 | pdata->regs->leveldetect0 = OMAP4_GPIO_LEVELDETECT0; | ||
116 | pdata->regs->leveldetect1 = OMAP4_GPIO_LEVELDETECT1; | ||
117 | pdata->regs->risingdetect = OMAP4_GPIO_RISINGDETECT; | ||
118 | pdata->regs->fallingdetect = OMAP4_GPIO_FALLINGDETECT; | ||
95 | break; | 119 | break; |
96 | default: | 120 | default: |
97 | WARN(1, "Invalid gpio bank_type\n"); | 121 | WARN(1, "Invalid gpio bank_type\n"); |
@@ -99,6 +123,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | |||
99 | return -EINVAL; | 123 | return -EINVAL; |
100 | } | 124 | } |
101 | 125 | ||
126 | pwrdm = omap_hwmod_get_pwrdm(oh); | ||
127 | pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); | ||
128 | |||
102 | pdev = omap_device_build(name, id - 1, oh, pdata, | 129 | pdev = omap_device_build(name, id - 1, oh, pdata, |
103 | sizeof(*pdata), NULL, 0, false); | 130 | sizeof(*pdata), NULL, 0, false); |
104 | kfree(pdata); | 131 | kfree(pdata); |
@@ -109,9 +136,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | |||
109 | return PTR_ERR(pdev); | 136 | return PTR_ERR(pdev); |
110 | } | 137 | } |
111 | 138 | ||
112 | omap_device_disable_idle_on_suspend(pdev); | ||
113 | |||
114 | gpio_bank_count++; | ||
115 | return 0; | 139 | return 0; |
116 | } | 140 | } |
117 | 141 | ||
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index b77df735fa6c..816c7940d301 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
@@ -75,16 +75,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm; | |||
75 | static struct powerdomain *core_pwrdm, *per_pwrdm; | 75 | static struct powerdomain *core_pwrdm, *per_pwrdm; |
76 | static struct powerdomain *cam_pwrdm; | 76 | static struct powerdomain *cam_pwrdm; |
77 | 77 | ||
78 | static inline void omap3_per_save_context(void) | ||
79 | { | ||
80 | omap_gpio_save_context(); | ||
81 | } | ||
82 | |||
83 | static inline void omap3_per_restore_context(void) | ||
84 | { | ||
85 | omap_gpio_restore_context(); | ||
86 | } | ||
87 | |||
88 | static void omap3_enable_io_chain(void) | 78 | static void omap3_enable_io_chain(void) |
89 | { | 79 | { |
90 | int timeout = 0; | 80 | int timeout = 0; |
@@ -332,8 +322,6 @@ void omap_sram_idle(void) | |||
332 | if (per_next_state < PWRDM_POWER_ON) { | 322 | if (per_next_state < PWRDM_POWER_ON) { |
333 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; | 323 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; |
334 | omap2_gpio_prepare_for_idle(per_going_off); | 324 | omap2_gpio_prepare_for_idle(per_going_off); |
335 | if (per_next_state == PWRDM_POWER_OFF) | ||
336 | omap3_per_save_context(); | ||
337 | } | 325 | } |
338 | 326 | ||
339 | /* CORE */ | 327 | /* CORE */ |
@@ -399,8 +387,6 @@ void omap_sram_idle(void) | |||
399 | if (per_next_state < PWRDM_POWER_ON) { | 387 | if (per_next_state < PWRDM_POWER_ON) { |
400 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); | 388 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); |
401 | omap2_gpio_resume_after_idle(); | 389 | omap2_gpio_resume_after_idle(); |
402 | if (per_prev_state == PWRDM_POWER_OFF) | ||
403 | omap3_per_restore_context(); | ||
404 | } | 390 | } |
405 | 391 | ||
406 | /* Disable IO-PAD and IO-CHAIN wakeup */ | 392 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index 9e86ee0aed0a..cb75b657b04b 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h | |||
@@ -162,13 +162,6 @@ | |||
162 | IH_MPUIO_BASE + ((nr) & 0x0f) : \ | 162 | IH_MPUIO_BASE + ((nr) & 0x0f) : \ |
163 | IH_GPIO_BASE + (nr)) | 163 | IH_GPIO_BASE + (nr)) |
164 | 164 | ||
165 | #define METHOD_MPUIO 0 | ||
166 | #define METHOD_GPIO_1510 1 | ||
167 | #define METHOD_GPIO_1610 2 | ||
168 | #define METHOD_GPIO_7XX 3 | ||
169 | #define METHOD_GPIO_24XX 5 | ||
170 | #define METHOD_GPIO_44XX 6 | ||
171 | |||
172 | struct omap_gpio_dev_attr { | 165 | struct omap_gpio_dev_attr { |
173 | int bank_width; /* GPIO bank width */ | 166 | int bank_width; /* GPIO bank width */ |
174 | bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ | 167 | bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ |
@@ -184,10 +177,21 @@ struct omap_gpio_reg_offs { | |||
184 | u16 irqstatus; | 177 | u16 irqstatus; |
185 | u16 irqstatus2; | 178 | u16 irqstatus2; |
186 | u16 irqenable; | 179 | u16 irqenable; |
180 | u16 irqenable2; | ||
187 | u16 set_irqenable; | 181 | u16 set_irqenable; |
188 | u16 clr_irqenable; | 182 | u16 clr_irqenable; |
189 | u16 debounce; | 183 | u16 debounce; |
190 | u16 debounce_en; | 184 | u16 debounce_en; |
185 | u16 ctrl; | ||
186 | u16 wkup_en; | ||
187 | u16 leveldetect0; | ||
188 | u16 leveldetect1; | ||
189 | u16 risingdetect; | ||
190 | u16 fallingdetect; | ||
191 | u16 irqctrl; | ||
192 | u16 edgectrl1; | ||
193 | u16 edgectrl2; | ||
194 | u16 pinctrl; | ||
191 | 195 | ||
192 | bool irqenable_inv; | 196 | bool irqenable_inv; |
193 | }; | 197 | }; |
@@ -198,19 +202,20 @@ struct omap_gpio_platform_data { | |||
198 | int bank_width; /* GPIO bank width */ | 202 | int bank_width; /* GPIO bank width */ |
199 | int bank_stride; /* Only needed for omap1 MPUIO */ | 203 | int bank_stride; /* Only needed for omap1 MPUIO */ |
200 | bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ | 204 | bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ |
205 | bool loses_context; /* whether the bank would ever lose context */ | ||
206 | bool is_mpuio; /* whether the bank is of type MPUIO */ | ||
207 | u32 non_wakeup_gpios; | ||
201 | 208 | ||
202 | struct omap_gpio_reg_offs *regs; | 209 | struct omap_gpio_reg_offs *regs; |
203 | }; | ||
204 | 210 | ||
205 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ | 211 | /* Return context loss count due to PM states changing */ |
206 | extern int gpio_bank_count; | 212 | int (*get_context_loss_count)(struct device *dev); |
213 | }; | ||
207 | 214 | ||
208 | extern void omap2_gpio_prepare_for_idle(int off_mode); | 215 | extern void omap2_gpio_prepare_for_idle(int off_mode); |
209 | extern void omap2_gpio_resume_after_idle(void); | 216 | extern void omap2_gpio_resume_after_idle(void); |
210 | extern void omap_set_gpio_debounce(int gpio, int enable); | 217 | extern void omap_set_gpio_debounce(int gpio, int enable); |
211 | extern void omap_set_gpio_debounce_time(int gpio, int enable); | 218 | extern void omap_set_gpio_debounce_time(int gpio, int enable); |
212 | extern void omap_gpio_save_context(void); | ||
213 | extern void omap_gpio_restore_context(void); | ||
214 | /*-------------------------------------------------------------------------*/ | 219 | /*-------------------------------------------------------------------------*/ |
215 | 220 | ||
216 | /* Wrappers for "new style" GPIO calls, using the new infrastructure | 221 | /* Wrappers for "new style" GPIO calls, using the new infrastructure |