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authorLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 19:17:43 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 19:17:43 -0400
commit4f2d658b2f09c41677871a4285a09cf35f954dad (patch)
treeec0a626a598530203871bbc37a340224e5ac87ad /arch/arm/plat-samsung
parente66d637134b7045ea6f14bdd416cd3695f73ed42 (diff)
parent1fc5f7d5c680ac36bd41e13a3d77cbe2eaa312e0 (diff)
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc device tree description updates from Arnd Bergmann: "This branch contains two kinds of updates: Some platforms in the process of getting converted to device tree based booting, and the platform specific patches necessary for that are included here. Other platforms are already converted, so we just need to update the actual device tree source files and the binding documents to add support for new board and new drivers. In the future we will probably separate those into two branches, and in the long run, the plan is to move the device tree source files out of the kernel repository, but that has to wait until we have completed a much larger portion of the binding documents." Fix up trivial conflicts in arch/arm/mach-imx/clk-imx6q.c due to newly added clkdev registers next to a few removed unnecessary ones. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits) ARM: LPC32xx: Add PWM to base dts file ARM: EXYNOS: mark the DMA channel binding for SPI as preliminary ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS5 platforms ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOS5 ARM: EXYNOS: Add spi clock support for EXYNOS5 ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS4 platforms ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOX4 ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock ARM: ux500: Remove PMU platform registration when booting with DT ARM: ux500: Remove temporary snowball_of_platform_devs enablement structure ARM: ux500: Ensure vendor specific properties have the vendor's identifier pinctrl: pinctrl-nomadik: Append sleepmode property with vendor specific prefixes ARM: ux500: Move rtc-pl031 registration to Device Tree when enabled ARM: ux500: Enable the AB8500 RTC for all DT:ed DB8500 based devices ARM: ux500: Correctly reference IRQs supplied by the AB8500 from Device Tree ARM: ux500: Apply ab8500-debug node do the db8500 DT structure ARM: ux500: Add a ab8500-usb Device Tree node for db8500 based devices ARM: ux500: Add db8500 Device Tree node for misc/ab8500-pwm ARM: ux500: Add db8500 Device Tree node for ab8500-sysctrl ARM: ux500: Enable LED heartbeat functionality on Snowbal via DT ...
Diffstat (limited to 'arch/arm/plat-samsung')
-rw-r--r--arch/arm/plat-samsung/devs.c60
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h39
2 files changed, 34 insertions, 65 deletions
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 6303974c2ee0..74e31ce35538 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1513,7 +1513,7 @@ static struct resource s3c64xx_spi0_resource[] = {
1513}; 1513};
1514 1514
1515struct platform_device s3c64xx_device_spi0 = { 1515struct platform_device s3c64xx_device_spi0 = {
1516 .name = "s3c64xx-spi", 1516 .name = "s3c6410-spi",
1517 .id = 0, 1517 .id = 0,
1518 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), 1518 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
1519 .resource = s3c64xx_spi0_resource, 1519 .resource = s3c64xx_spi0_resource,
@@ -1523,13 +1523,10 @@ struct platform_device s3c64xx_device_spi0 = {
1523 }, 1523 },
1524}; 1524};
1525 1525
1526void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, 1526void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1527 int src_clk_nr, int num_cs) 1527 int num_cs)
1528{ 1528{
1529 if (!pd) { 1529 struct s3c64xx_spi_info pd;
1530 pr_err("%s:Need to pass platform data\n", __func__);
1531 return;
1532 }
1533 1530
1534 /* Reject invalid configuration */ 1531 /* Reject invalid configuration */
1535 if (!num_cs || src_clk_nr < 0) { 1532 if (!num_cs || src_clk_nr < 0) {
@@ -1537,12 +1534,11 @@ void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
1537 return; 1534 return;
1538 } 1535 }
1539 1536
1540 pd->num_cs = num_cs; 1537 pd.num_cs = num_cs;
1541 pd->src_clk_nr = src_clk_nr; 1538 pd.src_clk_nr = src_clk_nr;
1542 if (!pd->cfg_gpio) 1539 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
1543 pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
1544 1540
1545 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0); 1541 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
1546} 1542}
1547#endif /* CONFIG_S3C64XX_DEV_SPI0 */ 1543#endif /* CONFIG_S3C64XX_DEV_SPI0 */
1548 1544
@@ -1555,7 +1551,7 @@ static struct resource s3c64xx_spi1_resource[] = {
1555}; 1551};
1556 1552
1557struct platform_device s3c64xx_device_spi1 = { 1553struct platform_device s3c64xx_device_spi1 = {
1558 .name = "s3c64xx-spi", 1554 .name = "s3c6410-spi",
1559 .id = 1, 1555 .id = 1,
1560 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), 1556 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
1561 .resource = s3c64xx_spi1_resource, 1557 .resource = s3c64xx_spi1_resource,
@@ -1565,26 +1561,20 @@ struct platform_device s3c64xx_device_spi1 = {
1565 }, 1561 },
1566}; 1562};
1567 1563
1568void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, 1564void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1569 int src_clk_nr, int num_cs) 1565 int num_cs)
1570{ 1566{
1571 if (!pd) {
1572 pr_err("%s:Need to pass platform data\n", __func__);
1573 return;
1574 }
1575
1576 /* Reject invalid configuration */ 1567 /* Reject invalid configuration */
1577 if (!num_cs || src_clk_nr < 0) { 1568 if (!num_cs || src_clk_nr < 0) {
1578 pr_err("%s: Invalid SPI configuration\n", __func__); 1569 pr_err("%s: Invalid SPI configuration\n", __func__);
1579 return; 1570 return;
1580 } 1571 }
1581 1572
1582 pd->num_cs = num_cs; 1573 pd.num_cs = num_cs;
1583 pd->src_clk_nr = src_clk_nr; 1574 pd.src_clk_nr = src_clk_nr;
1584 if (!pd->cfg_gpio) 1575 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
1585 pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
1586 1576
1587 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1); 1577 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
1588} 1578}
1589#endif /* CONFIG_S3C64XX_DEV_SPI1 */ 1579#endif /* CONFIG_S3C64XX_DEV_SPI1 */
1590 1580
@@ -1597,7 +1587,7 @@ static struct resource s3c64xx_spi2_resource[] = {
1597}; 1587};
1598 1588
1599struct platform_device s3c64xx_device_spi2 = { 1589struct platform_device s3c64xx_device_spi2 = {
1600 .name = "s3c64xx-spi", 1590 .name = "s3c6410-spi",
1601 .id = 2, 1591 .id = 2,
1602 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource), 1592 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
1603 .resource = s3c64xx_spi2_resource, 1593 .resource = s3c64xx_spi2_resource,
@@ -1607,13 +1597,10 @@ struct platform_device s3c64xx_device_spi2 = {
1607 }, 1597 },
1608}; 1598};
1609 1599
1610void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, 1600void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1611 int src_clk_nr, int num_cs) 1601 int num_cs)
1612{ 1602{
1613 if (!pd) { 1603 struct s3c64xx_spi_info pd;
1614 pr_err("%s:Need to pass platform data\n", __func__);
1615 return;
1616 }
1617 1604
1618 /* Reject invalid configuration */ 1605 /* Reject invalid configuration */
1619 if (!num_cs || src_clk_nr < 0) { 1606 if (!num_cs || src_clk_nr < 0) {
@@ -1621,11 +1608,10 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
1621 return; 1608 return;
1622 } 1609 }
1623 1610
1624 pd->num_cs = num_cs; 1611 pd.num_cs = num_cs;
1625 pd->src_clk_nr = src_clk_nr; 1612 pd.src_clk_nr = src_clk_nr;
1626 if (!pd->cfg_gpio) 1613 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
1627 pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
1628 1614
1629 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2); 1615 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
1630} 1616}
1631#endif /* CONFIG_S3C64XX_DEV_SPI2 */ 1617#endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index fa95e9a00972..ceba18d23a5a 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -18,7 +18,6 @@ struct platform_device;
18 * @fb_delay: Slave specific feedback delay. 18 * @fb_delay: Slave specific feedback delay.
19 * Refer to FB_CLK_SEL register definition in SPI chapter. 19 * Refer to FB_CLK_SEL register definition in SPI chapter.
20 * @line: Custom 'identity' of the CS line. 20 * @line: Custom 'identity' of the CS line.
21 * @set_level: CS line control.
22 * 21 *
23 * This is per SPI-Slave Chipselect information. 22 * This is per SPI-Slave Chipselect information.
24 * Allocate and initialize one in machine init code and make the 23 * Allocate and initialize one in machine init code and make the
@@ -27,57 +26,41 @@ struct platform_device;
27struct s3c64xx_spi_csinfo { 26struct s3c64xx_spi_csinfo {
28 u8 fb_delay; 27 u8 fb_delay;
29 unsigned line; 28 unsigned line;
30 void (*set_level)(unsigned line_id, int lvl);
31}; 29};
32 30
33/** 31/**
34 * struct s3c64xx_spi_info - SPI Controller defining structure 32 * struct s3c64xx_spi_info - SPI Controller defining structure
35 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. 33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
36 * @clk_from_cmu: If the SPI clock/prescalar control block is present
37 * by the platform's clock-management-unit and not in SPI controller.
38 * @num_cs: Number of CS this controller emulates. 34 * @num_cs: Number of CS this controller emulates.
39 * @cfg_gpio: Configure pins for this SPI controller. 35 * @cfg_gpio: Configure pins for this SPI controller.
40 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
41 * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
42 * @high_speed: If the controller supports HIGH_SPEED_EN bit
43 * @tx_st_done: Depends on tx fifo_lvl field
44 */ 36 */
45struct s3c64xx_spi_info { 37struct s3c64xx_spi_info {
46 int src_clk_nr; 38 int src_clk_nr;
47 bool clk_from_cmu;
48
49 int num_cs; 39 int num_cs;
50 40 int (*cfg_gpio)(void);
51 int (*cfg_gpio)(struct platform_device *pdev);
52
53 /* Following two fields are for future compatibility */
54 int fifo_lvl_mask;
55 int rx_lvl_offset;
56 int high_speed;
57 int tx_st_done;
58}; 41};
59 42
60/** 43/**
61 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board 44 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
62 * initialization code. 45 * initialization code.
63 * @pd: SPI platform data to set. 46 * @cfg_gpio: Pointer to gpio setup function.
64 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. 47 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
65 * @num_cs: Number of elements in the 'cs' array. 48 * @num_cs: Number of elements in the 'cs' array.
66 * 49 *
67 * Call this from machine init code for each SPI Controller that 50 * Call this from machine init code for each SPI Controller that
68 * has some chips attached to it. 51 * has some chips attached to it.
69 */ 52 */
70extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, 53extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
71 int src_clk_nr, int num_cs); 54 int num_cs);
72extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, 55extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
73 int src_clk_nr, int num_cs); 56 int num_cs);
74extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, 57extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
75 int src_clk_nr, int num_cs); 58 int num_cs);
76 59
77/* defined by architecture to configure gpio */ 60/* defined by architecture to configure gpio */
78extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev); 61extern int s3c64xx_spi0_cfg_gpio(void);
79extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev); 62extern int s3c64xx_spi1_cfg_gpio(void);
80extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev); 63extern int s3c64xx_spi2_cfg_gpio(void);
81 64
82extern struct s3c64xx_spi_info s3c64xx_spi0_pdata; 65extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
83extern struct s3c64xx_spi_info s3c64xx_spi1_pdata; 66extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;