[ARM] S3C: Merge next-s3c64xx-dma2 into for-rmk-devel

Merge branch 'next-s3c64xx-dma2' into for-rmk-devel

Conflicts:

	arch/arm/plat-s3c64xx/Makefile

4 files changed, 209 insertions, 100 deletions

diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 2c8a2f5d75ff..5b0bc914f58e 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -71,6 +71,7 @@ config PM_SIMTEC
 config S3C2410_DMA
         bool "S3C2410 DMA support"
         depends on ARCH_S3C2410
+        select S3C_DMA
         help
           S3C2410 DMA support. This is needed for drivers like sound which
           use the S3C2410's DMA system to move data to and from the
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index aee2aeb46c60..b07fec01ab47 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -31,10 +31,10 @@
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/dma.h>
-
 #include <mach/map.h>
 
-#include <plat/dma.h>
+#include <plat/dma-plat.h>
+#include <plat/regs-dma.h>
 
 /* io map for dma */
 static void __iomem *dma_base;
@@ -44,8 +44,6 @@ static int dma_channels;
 
 static struct s3c24xx_dma_selection dma_sel;
 
-/* dma channel state information */
-struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
 
 /* debugging functions */
 
@@ -135,21 +133,6 @@ dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
 #define dbg_showchan(chan) do { } while(0)
 #endif /* CONFIG_S3C2410_DMA_DEBUG */
 
-static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
-
-/* lookup_dma_channel
- *
- * change the dma channel number given into a real dma channel id
-*/
-
-static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
-{
-        if (channel & DMACH_LOW_LEVEL)
-                return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
-        else
-                return dma_chan_map[channel];
-}
-
 /* s3c2410_dma_stats_timeout
  *
  * Update DMA stats from timeout info
@@ -214,8 +197,6 @@ s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
         return 0;
 }
 
-
-
 /* s3c2410_dma_loadbuffer
  *
  * load a buffer, and update the channel state
@@ -453,7 +434,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
 int s3c2410_dma_enqueue(unsigned int channel, void *id,
                         dma_addr_t data, int size)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
         struct s3c2410_dma_buf *buf;
         unsigned long flags;
 
@@ -804,7 +785,7 @@ EXPORT_SYMBOL(s3c2410_dma_request);
 
 int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
         unsigned long flags;
 
         if (chan == NULL)
@@ -836,7 +817,7 @@ int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
         chan->irq_claimed = 0;
 
         if (!(channel & DMACH_LOW_LEVEL))
-                dma_chan_map[channel] = NULL;
+                s3c_dma_chan_map[channel] = NULL;
 
         local_irq_restore(flags);
 
@@ -995,7 +976,7 @@ static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
 int
 s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 
         if (chan == NULL)
                 return -EINVAL;
@@ -1038,14 +1019,13 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl);
 /* s3c2410_dma_config
  *
  * xfersize:     size of unit in bytes (1,2,4)
- * dcon:         base value of the DCONx register
 */
 
 int s3c2410_dma_config(unsigned int channel,
-                       int xferunit,
-                       int dcon)
+                       int xferunit)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        unsigned int dcon;
 
         pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
                  __func__, channel, xferunit, dcon);
@@ -1055,10 +1035,33 @@ int s3c2410_dma_config(unsigned int channel,
 
         pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
 
-        dcon |= chan->dcon & dma_sel.dcon_mask;
+        dcon = chan->dcon & dma_sel.dcon_mask;
 
         pr_debug("%s: New dcon is %08x\n", __func__, dcon);
 
+        switch (chan->req_ch) {
+        case DMACH_I2S_IN:
+        case DMACH_I2S_OUT:
+        case DMACH_PCM_IN:
+        case DMACH_PCM_OUT:
+        case DMACH_MIC_IN:
+        default:
+                dcon |= S3C2410_DCON_HANDSHAKE;
+                dcon |= S3C2410_DCON_SYNC_PCLK;
+                break;
+
+        case DMACH_SDI:
+                /* note, ensure if need HANDSHAKE or not */
+                dcon |= S3C2410_DCON_SYNC_PCLK;
+                break;
+
+        case DMACH_XD0:
+        case DMACH_XD1:
+                dcon |= S3C2410_DCON_HANDSHAKE;
+                dcon |= S3C2410_DCON_SYNC_HCLK;
+                break;
+        }
+
         switch (xferunit) {
         case 1:
                 dcon |= S3C2410_DCON_BYTE;
@@ -1090,58 +1093,6 @@ int s3c2410_dma_config(unsigned int channel,
 
 EXPORT_SYMBOL(s3c2410_dma_config);
 
-int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
-{
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
-
-        if (chan == NULL)
-                return -EINVAL;
-
-        pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
-
-        chan->flags = flags;
-
-        return 0;
-}
-
-EXPORT_SYMBOL(s3c2410_dma_setflags);
-
-
-/* do we need to protect the settings of the fields from
- * irq?
-*/
-
-int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
-{
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
-
-        if (chan == NULL)
-                return -EINVAL;
-
-        pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
-
-        chan->op_fn = rtn;
-
-        return 0;
-}
-
-EXPORT_SYMBOL(s3c2410_dma_set_opfn);
-
-int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
-{
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
-
-        if (chan == NULL)
-                return -EINVAL;
-
-        pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
-
-        chan->callback_fn = rtn;
-
-        return 0;
-}
-
-EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
 
 /* s3c2410_dma_devconfig
  *
@@ -1150,29 +1101,38 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
  * source:    S3C2410_DMASRC_HW: source is hardware
  *            S3C2410_DMASRC_MEM: source is memory
  *
- * hwcfg:     the value for xxxSTCn register,
- *            bit 0: 0=increment pointer, 1=leave pointer
- *            bit 1: 0=source is AHB, 1=source is APB
- *
  * devaddr:   physical address of the source
 */
 
 int s3c2410_dma_devconfig(int channel,
                           enum s3c2410_dmasrc source,
-                          int hwcfg,
                           unsigned long devaddr)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        unsigned int hwcfg;
 
         if (chan == NULL)
                 return -EINVAL;
 
-        pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
-                 __func__, (int)source, hwcfg, devaddr);
+        pr_debug("%s: source=%d, devaddr=%08lx\n",
+                 __func__, (int)source, devaddr);
 
         chan->source = source;
         chan->dev_addr = devaddr;
-        chan->hw_cfg = hwcfg;
+
+        switch (chan->req_ch) {
+        case DMACH_XD0:
+        case DMACH_XD1:
+                hwcfg = 0; /* AHB */
+                break;
+
+        default:
+                hwcfg = S3C2410_DISRCC_APB;
+        }
+
+        /* always assume our peripheral desintation is a fixed
+         * address in memory. */
+         hwcfg |= S3C2410_DISRCC_INC;
 
         switch (source) {
         case S3C2410_DMASRC_HW:
@@ -1219,7 +1179,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
 
 int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 
         if (chan == NULL)
                 return -EINVAL;
@@ -1278,8 +1238,8 @@ static int s3c2410_dma_resume(struct sys_device *dev)
 
         printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
 
-        s3c2410_dma_config(no, cp->xfer_unit, cp->dcon);
-        s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr);
+        s3c2410_dma_config(no, cp->xfer_unit);
+        s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
 
         /* re-select the dma source for this channel */
 
@@ -1476,7 +1436,8 @@ static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
  found:
         dmach = &s3c2410_chans[ch];
         dmach->map = ch_map;
-        dma_chan_map[channel] = dmach;
+        dmach->req_ch = channel;
+        s3c_dma_chan_map[channel] = dmach;
 
         /* select the channel */
 
diff --git a/arch/arm/plat-s3c24xx/include/plat/dma.h b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
index c78efe316fc8..9565ead1bc9b 100644
--- a/arch/arm/plat-s3c24xx/include/plat/dma.h
+++ b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/plat-s3c24xx/dma.h
+/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
  *
  * Copyright (C) 2006 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
@@ -10,8 +10,10 @@
  * published by the Free Software Foundation.
 */
 
+#include <plat/dma-core.h>
+
 extern struct sysdev_class dma_sysclass;
-extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
+extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
 
 #define DMA_CH_VALID            (1<<31)
 #define DMA_CH_NEVER            (1<<30)
@@ -31,8 +33,8 @@ struct s3c24xx_dma_map {
         const char              *name;
         struct s3c24xx_dma_addr  hw_addr;
 
-        unsigned long            channels[S3C2410_DMA_CHANNELS];
-        unsigned long            channels_rx[S3C2410_DMA_CHANNELS];
+        unsigned long            channels[S3C_DMA_CHANNELS];
+        unsigned long            channels_rx[S3C_DMA_CHANNELS];
 };
 
 struct s3c24xx_dma_selection {
@@ -58,7 +60,7 @@ extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
 */
 
 struct s3c24xx_dma_order_ch {
-        unsigned int    list[S3C2410_DMA_CHANNELS];     /* list of channels */
+        unsigned int    list[S3C_DMA_CHANNELS]; /* list of channels */
         unsigned int    flags;                          /* flags */
 };
 
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
new file mode 100644
index 000000000000..3bc0a216df97
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
@@ -0,0 +1,145 @@
+/* arch/arm/mach-s3c2410/include/mach/dma.h
+ *
+ * Copyright (C) 2003,2004,2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C24XX DMA support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* DMA Register definitions */
+
+#define S3C2410_DMA_DISRC               (0x00)
+#define S3C2410_DMA_DISRCC              (0x04)
+#define S3C2410_DMA_DIDST               (0x08)
+#define S3C2410_DMA_DIDSTC              (0x0C)
+#define S3C2410_DMA_DCON                (0x10)
+#define S3C2410_DMA_DSTAT               (0x14)
+#define S3C2410_DMA_DCSRC               (0x18)
+#define S3C2410_DMA_DCDST               (0x1C)
+#define S3C2410_DMA_DMASKTRIG           (0x20)
+#define S3C2412_DMA_DMAREQSEL           (0x24)
+#define S3C2443_DMA_DMAREQSEL           (0x24)
+
+#define S3C2410_DISRCC_INC              (1<<0)
+#define S3C2410_DISRCC_APB              (1<<1)
+
+#define S3C2410_DMASKTRIG_STOP          (1<<2)
+#define S3C2410_DMASKTRIG_ON            (1<<1)
+#define S3C2410_DMASKTRIG_SWTRIG        (1<<0)
+
+#define S3C2410_DCON_DEMAND             (0<<31)
+#define S3C2410_DCON_HANDSHAKE          (1<<31)
+#define S3C2410_DCON_SYNC_PCLK          (0<<30)
+#define S3C2410_DCON_SYNC_HCLK          (1<<30)
+
+#define S3C2410_DCON_INTREQ             (1<<29)
+
+#define S3C2410_DCON_CH0_XDREQ0         (0<<24)
+#define S3C2410_DCON_CH0_UART0          (1<<24)
+#define S3C2410_DCON_CH0_SDI            (2<<24)
+#define S3C2410_DCON_CH0_TIMER          (3<<24)
+#define S3C2410_DCON_CH0_USBEP1         (4<<24)
+
+#define S3C2410_DCON_CH1_XDREQ1         (0<<24)
+#define S3C2410_DCON_CH1_UART1          (1<<24)
+#define S3C2410_DCON_CH1_I2SSDI         (2<<24)
+#define S3C2410_DCON_CH1_SPI            (3<<24)
+#define S3C2410_DCON_CH1_USBEP2         (4<<24)
+
+#define S3C2410_DCON_CH2_I2SSDO         (0<<24)
+#define S3C2410_DCON_CH2_I2SSDI         (1<<24)
+#define S3C2410_DCON_CH2_SDI            (2<<24)
+#define S3C2410_DCON_CH2_TIMER          (3<<24)
+#define S3C2410_DCON_CH2_USBEP3         (4<<24)
+
+#define S3C2410_DCON_CH3_UART2          (0<<24)
+#define S3C2410_DCON_CH3_SDI            (1<<24)
+#define S3C2410_DCON_CH3_SPI            (2<<24)
+#define S3C2410_DCON_CH3_TIMER          (3<<24)
+#define S3C2410_DCON_CH3_USBEP4         (4<<24)
+
+#define S3C2410_DCON_SRCSHIFT           (24)
+#define S3C2410_DCON_SRCMASK            (7<<24)
+
+#define S3C2410_DCON_BYTE               (0<<20)
+#define S3C2410_DCON_HALFWORD           (1<<20)
+#define S3C2410_DCON_WORD               (2<<20)
+
+#define S3C2410_DCON_AUTORELOAD         (0<<22)
+#define S3C2410_DCON_NORELOAD           (1<<22)
+#define S3C2410_DCON_HWTRIG             (1<<23)
+
+#ifdef CONFIG_CPU_S3C2440
+#define S3C2440_DIDSTC_CHKINT           (1<<2)
+
+#define S3C2440_DCON_CH0_I2SSDO         (5<<24)
+#define S3C2440_DCON_CH0_PCMIN          (6<<24)
+
+#define S3C2440_DCON_CH1_PCMOUT         (5<<24)
+#define S3C2440_DCON_CH1_SDI            (6<<24)
+
+#define S3C2440_DCON_CH2_PCMIN          (5<<24)
+#define S3C2440_DCON_CH2_MICIN          (6<<24)
+
+#define S3C2440_DCON_CH3_MICIN          (5<<24)
+#define S3C2440_DCON_CH3_PCMOUT         (6<<24)
+#endif
+
+#ifdef CONFIG_CPU_S3C2412
+
+#define S3C2412_DMAREQSEL_SRC(x)        ((x)<<1)
+
+#define S3C2412_DMAREQSEL_HW            (1)
+
+#define S3C2412_DMAREQSEL_SPI0TX        S3C2412_DMAREQSEL_SRC(0)
+#define S3C2412_DMAREQSEL_SPI0RX        S3C2412_DMAREQSEL_SRC(1)
+#define S3C2412_DMAREQSEL_SPI1TX        S3C2412_DMAREQSEL_SRC(2)
+#define S3C2412_DMAREQSEL_SPI1RX        S3C2412_DMAREQSEL_SRC(3)
+#define S3C2412_DMAREQSEL_I2STX         S3C2412_DMAREQSEL_SRC(4)
+#define S3C2412_DMAREQSEL_I2SRX         S3C2412_DMAREQSEL_SRC(5)
+#define S3C2412_DMAREQSEL_TIMER         S3C2412_DMAREQSEL_SRC(9)
+#define S3C2412_DMAREQSEL_SDI           S3C2412_DMAREQSEL_SRC(10)
+#define S3C2412_DMAREQSEL_USBEP1        S3C2412_DMAREQSEL_SRC(13)
+#define S3C2412_DMAREQSEL_USBEP2        S3C2412_DMAREQSEL_SRC(14)
+#define S3C2412_DMAREQSEL_USBEP3        S3C2412_DMAREQSEL_SRC(15)
+#define S3C2412_DMAREQSEL_USBEP4        S3C2412_DMAREQSEL_SRC(16)
+#define S3C2412_DMAREQSEL_XDREQ0        S3C2412_DMAREQSEL_SRC(17)
+#define S3C2412_DMAREQSEL_XDREQ1        S3C2412_DMAREQSEL_SRC(18)
+#define S3C2412_DMAREQSEL_UART0_0       S3C2412_DMAREQSEL_SRC(19)
+#define S3C2412_DMAREQSEL_UART0_1       S3C2412_DMAREQSEL_SRC(20)
+#define S3C2412_DMAREQSEL_UART1_0       S3C2412_DMAREQSEL_SRC(21)
+#define S3C2412_DMAREQSEL_UART1_1       S3C2412_DMAREQSEL_SRC(22)
+#define S3C2412_DMAREQSEL_UART2_0       S3C2412_DMAREQSEL_SRC(23)
+#define S3C2412_DMAREQSEL_UART2_1       S3C2412_DMAREQSEL_SRC(24)
+
+#endif
+
+#define S3C2443_DMAREQSEL_SRC(x)        ((x)<<1)
+
+#define S3C2443_DMAREQSEL_HW            (1)
+
+#define S3C2443_DMAREQSEL_SPI0TX        S3C2443_DMAREQSEL_SRC(0)
+#define S3C2443_DMAREQSEL_SPI0RX        S3C2443_DMAREQSEL_SRC(1)
+#define S3C2443_DMAREQSEL_SPI1TX        S3C2443_DMAREQSEL_SRC(2)
+#define S3C2443_DMAREQSEL_SPI1RX        S3C2443_DMAREQSEL_SRC(3)
+#define S3C2443_DMAREQSEL_I2STX         S3C2443_DMAREQSEL_SRC(4)
+#define S3C2443_DMAREQSEL_I2SRX         S3C2443_DMAREQSEL_SRC(5)
+#define S3C2443_DMAREQSEL_TIMER         S3C2443_DMAREQSEL_SRC(9)
+#define S3C2443_DMAREQSEL_SDI           S3C2443_DMAREQSEL_SRC(10)
+#define S3C2443_DMAREQSEL_XDREQ0        S3C2443_DMAREQSEL_SRC(17)
+#define S3C2443_DMAREQSEL_XDREQ1        S3C2443_DMAREQSEL_SRC(18)
+#define S3C2443_DMAREQSEL_UART0_0       S3C2443_DMAREQSEL_SRC(19)
+#define S3C2443_DMAREQSEL_UART0_1       S3C2443_DMAREQSEL_SRC(20)
+#define S3C2443_DMAREQSEL_UART1_0       S3C2443_DMAREQSEL_SRC(21)
+#define S3C2443_DMAREQSEL_UART1_1       S3C2443_DMAREQSEL_SRC(22)
+#define S3C2443_DMAREQSEL_UART2_0       S3C2443_DMAREQSEL_SRC(23)
+#define S3C2443_DMAREQSEL_UART2_1       S3C2443_DMAREQSEL_SRC(24)
+#define S3C2443_DMAREQSEL_UART3_0       S3C2443_DMAREQSEL_SRC(25)
+#define S3C2443_DMAREQSEL_UART3_1       S3C2443_DMAREQSEL_SRC(26)
+#define S3C2443_DMAREQSEL_PCMOUT        S3C2443_DMAREQSEL_SRC(27)
+#define S3C2443_DMAREQSEL_PCMIN         S3C2443_DMAREQSEL_SRC(28)
+#define S3C2443_DMAREQSEL_MICIN         S3C2443_DMAREQSEL_SRC(29)