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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-26 15:31:49 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-26 15:31:49 -0400
commit2c757fd5d1a92086f225a75a8fac7cab242d11b0 (patch)
treed150ea105242d551f6959c2525472295e151144c /arch/arm/plat-omap
parentce53044c68cf4fb6c50a2a0d88786be65fae7235 (diff)
parent424663566c43ce87e8b33228860bf882f1ea61bf (diff)
Merge tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc cleanups (part 2) from Olof Johansson: "More cleanups, continuing an earlier set with omap and samsung specific cleanups. These could not go into the first set because they have dependencies on various other series that in turn depend on the first cleanups." Fixed up conflicts in arch/arm/plat-omap/counter_32k.c due to commit bd0493eaaf5c: "move read_{boot,persistent}_clock to the architecture level" that changed how the persistent clocks were handled. And trivial conflicts in arch/arm/mach-omap1/common.h due to just independent changes close to each other. * tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (35 commits) ARM: SAMSUNG: merge plat-s5p into plat-samsung ARM: SAMSUNG: move options for common s5p into plat-samsung/Kconfig ARM: SAMSUNG: move setup code for s5p mfc and mipiphy into plat-samsung ARM: SAMSUNG: move platform device for s5p uart into plat-samsung ARM: SAMSUNG: move hr timer for common s5p into plat-samsung ARM: SAMSUNG: move pm part for common s5p into plat-samsung ARM: SAMSUNG: move interrupt part for common s5p into plat-samsung ARM: SAMSUNG: move clock part for common s5p into plat-samsung ARM: S3C24XX: Use common macro to define resources on dev-uart.c ARM: S3C24XX: move common clock init into common.c ARM: S3C24XX: move common power-management code to mach-s3c24xx ARM: S3C24XX: move plat-s3c24xx/dev-uart.c into common.c ARM: S3C24XX: move plat-s3c24xx/cpu.c ARM: OMAP2+: Kconfig: convert SOC_OMAPAM33XX to SOC_AM33XX ARM: OMAP2+: Kconfig: convert SOC_OMAPTI81XX to SOC_TI81XX GPMC: add ECC control definitions ARM: OMAP2+: dmtimer: remove redundant sysconfig context restore ARM: OMAP: AM35xx: convert 3517 detection/flags to AM35xx ARM: OMAP: AM35xx: remove redunant cpu_is checks for AM3505 ARM: OMAP1: Pass dma request lines in platform data to MMC driver ...
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/counter_32k.c93
-rw-r--r--arch/arm/plat-omap/devices.c122
-rw-r--r--arch/arm/plat-omap/dma.c4
-rw-r--r--arch/arm/plat-omap/dmtimer.c2
-rw-r--r--arch/arm/plat-omap/include/plat/common.h2
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h8
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h5
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h1
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h9
9 files changed, 56 insertions, 190 deletions
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 44ae077dbc28..2132c4f389e1 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -28,19 +28,20 @@
28 28
29#include <plat/clock.h> 29#include <plat/clock.h>
30 30
31/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
32#define OMAP2_32KSYNCNT_CR_OFF 0x10
33
31/* 34/*
32 * 32KHz clocksource ... always available, on pretty most chips except 35 * 32KHz clocksource ... always available, on pretty most chips except
33 * OMAP 730 and 1510. Other timers could be used as clocksources, with 36 * OMAP 730 and 1510. Other timers could be used as clocksources, with
34 * higher resolution in free-running counter modes (e.g. 12 MHz xtal), 37 * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
35 * but systems won't necessarily want to spend resources that way. 38 * but systems won't necessarily want to spend resources that way.
36 */ 39 */
37static void __iomem *timer_32k_base; 40static void __iomem *sync32k_cnt_reg;
38
39#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
40 41
41static u32 notrace omap_32k_read_sched_clock(void) 42static u32 notrace omap_32k_read_sched_clock(void)
42{ 43{
43 return timer_32k_base ? __raw_readl(timer_32k_base) : 0; 44 return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
44} 45}
45 46
46/** 47/**
@@ -60,7 +61,7 @@ static void omap_read_persistent_clock(struct timespec *ts)
60 struct timespec *tsp = &persistent_ts; 61 struct timespec *tsp = &persistent_ts;
61 62
62 last_cycles = cycles; 63 last_cycles = cycles;
63 cycles = timer_32k_base ? __raw_readl(timer_32k_base) : 0; 64 cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
64 delta = cycles - last_cycles; 65 delta = cycles - last_cycles;
65 66
66 nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift); 67 nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift);
@@ -69,55 +70,41 @@ static void omap_read_persistent_clock(struct timespec *ts)
69 *ts = *tsp; 70 *ts = *tsp;
70} 71}
71 72
72int __init omap_init_clocksource_32k(void) 73/**
74 * omap_init_clocksource_32k - setup and register counter 32k as a
75 * kernel clocksource
76 * @pbase: base addr of counter_32k module
77 * @size: size of counter_32k to map
78 *
79 * Returns 0 upon success or negative error code upon failure.
80 *
81 */
82int __init omap_init_clocksource_32k(void __iomem *vbase)
73{ 83{
74 static char err[] __initdata = KERN_ERR 84 int ret;
75 "%s: can't register clocksource!\n"; 85
76 86 /*
77 if (cpu_is_omap16xx() || cpu_class_is_omap2()) { 87 * 32k sync Counter register offset is at 0x10
78 u32 pbase; 88 */
79 unsigned long size = SZ_4K; 89 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF;
80 void __iomem *base; 90
81 struct clk *sync_32k_ick; 91 /*
82 92 * 120000 rough estimate from the calculations in
83 if (cpu_is_omap16xx()) { 93 * __clocksource_updatefreq_scale.
84 pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED; 94 */
85 size = SZ_1K; 95 clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
86 } else if (cpu_is_omap2420()) 96 32768, NSEC_PER_SEC, 120000);
87 pbase = OMAP2420_32KSYNCT_BASE + 0x10; 97
88 else if (cpu_is_omap2430()) 98 ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
89 pbase = OMAP2430_32KSYNCT_BASE + 0x10; 99 250, 32, clocksource_mmio_readl_up);
90 else if (cpu_is_omap34xx()) 100 if (ret) {
91 pbase = OMAP3430_32KSYNCT_BASE + 0x10; 101 pr_err("32k_counter: can't register clocksource\n");
92 else if (cpu_is_omap44xx()) 102 return ret;
93 pbase = OMAP4430_32KSYNCT_BASE + 0x10;
94 else
95 return -ENODEV;
96
97 /* For this to work we must have a static mapping in io.c for this area */
98 base = ioremap(pbase, size);
99 if (!base)
100 return -ENODEV;
101
102 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
103 if (!IS_ERR(sync_32k_ick))
104 clk_enable(sync_32k_ick);
105
106 timer_32k_base = base;
107
108 /*
109 * 120000 rough estimate from the calculations in
110 * __clocksource_updatefreq_scale.
111 */
112 clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
113 32768, NSEC_PER_SEC, 120000);
114
115 if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
116 clocksource_mmio_readl_up))
117 printk(err, "32k_counter");
118
119 setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
120 register_persistent_clock(NULL, omap_read_persistent_clock);
121 } 103 }
104
105 setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
106 register_persistent_clock(NULL, omap_read_persistent_clock);
107 pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
108
122 return 0; 109 return 0;
123} 110}
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 09b07d252892..1cba9273d2cb 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -28,54 +28,6 @@
28#include <plat/menelaus.h> 28#include <plat/menelaus.h>
29#include <plat/omap44xx.h> 29#include <plat/omap44xx.h>
30 30
31#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
32 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
33
34#define OMAP_MMC_NR_RES 2
35
36/*
37 * Register MMC devices. Called from mach-omap1 and mach-omap2 device init.
38 */
39int __init omap_mmc_add(const char *name, int id, unsigned long base,
40 unsigned long size, unsigned int irq,
41 struct omap_mmc_platform_data *data)
42{
43 struct platform_device *pdev;
44 struct resource res[OMAP_MMC_NR_RES];
45 int ret;
46
47 pdev = platform_device_alloc(name, id);
48 if (!pdev)
49 return -ENOMEM;
50
51 memset(res, 0, OMAP_MMC_NR_RES * sizeof(struct resource));
52 res[0].start = base;
53 res[0].end = base + size - 1;
54 res[0].flags = IORESOURCE_MEM;
55 res[1].start = res[1].end = irq;
56 res[1].flags = IORESOURCE_IRQ;
57
58 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
59 if (ret == 0)
60 ret = platform_device_add_data(pdev, data, sizeof(*data));
61 if (ret)
62 goto fail;
63
64 ret = platform_device_add(pdev);
65 if (ret)
66 goto fail;
67
68 /* return device handle to board setup code */
69 data->dev = &pdev->dev;
70 return 0;
71
72fail:
73 platform_device_put(pdev);
74 return ret;
75}
76
77#endif
78
79/*-------------------------------------------------------------------------*/ 31/*-------------------------------------------------------------------------*/
80 32
81#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) 33#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
@@ -109,79 +61,6 @@ static void omap_init_rng(void)
109static inline void omap_init_rng(void) {} 61static inline void omap_init_rng(void) {}
110#endif 62#endif
111 63
112/*-------------------------------------------------------------------------*/
113
114/* Numbering for the SPI-capable controllers when used for SPI:
115 * spi = 1
116 * uwire = 2
117 * mmc1..2 = 3..4
118 * mcbsp1..3 = 5..7
119 */
120
121#if defined(CONFIG_SPI_OMAP_UWIRE) || defined(CONFIG_SPI_OMAP_UWIRE_MODULE)
122
123#define OMAP_UWIRE_BASE 0xfffb3000
124
125static struct resource uwire_resources[] = {
126 {
127 .start = OMAP_UWIRE_BASE,
128 .end = OMAP_UWIRE_BASE + 0x20,
129 .flags = IORESOURCE_MEM,
130 },
131};
132
133static struct platform_device omap_uwire_device = {
134 .name = "omap_uwire",
135 .id = -1,
136 .num_resources = ARRAY_SIZE(uwire_resources),
137 .resource = uwire_resources,
138};
139
140static void omap_init_uwire(void)
141{
142 /* FIXME define and use a boot tag; not all boards will be hooking
143 * up devices to the microwire controller, and multi-board configs
144 * mean that CONFIG_SPI_OMAP_UWIRE may be configured anyway...
145 */
146
147 /* board-specific code must configure chipselects (only a few
148 * are normally used) and SCLK/SDI/SDO (each has two choices).
149 */
150 (void) platform_device_register(&omap_uwire_device);
151}
152#else
153static inline void omap_init_uwire(void) {}
154#endif
155
156#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
157
158static phys_addr_t omap_dsp_phys_mempool_base;
159
160void __init omap_dsp_reserve_sdram_memblock(void)
161{
162 phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
163 phys_addr_t paddr;
164
165 if (!size)
166 return;
167
168 paddr = arm_memblock_steal(size, SZ_1M);
169 if (!paddr) {
170 pr_err("%s: failed to reserve %llx bytes\n",
171 __func__, (unsigned long long)size);
172 return;
173 }
174
175 omap_dsp_phys_mempool_base = paddr;
176}
177
178phys_addr_t omap_dsp_get_mempool_base(void)
179{
180 return omap_dsp_phys_mempool_base;
181}
182EXPORT_SYMBOL(omap_dsp_get_mempool_base);
183#endif
184
185/* 64/*
186 * This gets called after board-specific INIT_MACHINE, and initializes most 65 * This gets called after board-specific INIT_MACHINE, and initializes most
187 * on-chip peripherals accessible on this board (except for few like USB): 66 * on-chip peripherals accessible on this board (except for few like USB):
@@ -208,7 +87,6 @@ static int __init omap_init_devices(void)
208 * in alphabetical order so they're easier to sort through. 87 * in alphabetical order so they're easier to sort through.
209 */ 88 */
210 omap_init_rng(); 89 omap_init_rng();
211 omap_init_uwire();
212 return 0; 90 return 0;
213} 91}
214arch_initcall(omap_init_devices); 92arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 987e6101267d..cb16ade437cb 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -852,7 +852,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
852 } 852 }
853 l = p->dma_read(CCR, lch); 853 l = p->dma_read(CCR, lch);
854 l &= ~((1 << 6) | (1 << 26)); 854 l &= ~((1 << 6) | (1 << 26));
855 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) 855 if (cpu_class_is_omap2() && !cpu_is_omap242x())
856 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); 856 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
857 else 857 else
858 l |= ((read_prio & 0x1) << 6); 858 l |= ((read_prio & 0x1) << 6);
@@ -2080,7 +2080,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2080 } 2080 }
2081 } 2081 }
2082 2082
2083 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) 2083 if (cpu_class_is_omap2() && !cpu_is_omap242x())
2084 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, 2084 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2085 DMA_DEFAULT_FIFO_DEPTH, 0); 2085 DMA_DEFAULT_FIFO_DEPTH, 0);
2086 2086
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index c4ed35e89fbd..3b0cfeb33d05 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -82,8 +82,6 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
82 82
83static void omap_timer_restore_context(struct omap_dm_timer *timer) 83static void omap_timer_restore_context(struct omap_dm_timer *timer)
84{ 84{
85 __raw_writel(timer->context.tiocp_cfg,
86 timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
87 if (timer->revision == 1) 85 if (timer->revision == 1)
88 __raw_writel(timer->context.tistat, timer->sys_stat); 86 __raw_writel(timer->context.tistat, timer->sys_stat);
89 87
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index a557b8484e6c..d1cb6f527b7e 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -30,7 +30,7 @@
30#include <plat/i2c.h> 30#include <plat/i2c.h>
31#include <plat/omap_hwmod.h> 31#include <plat/omap_hwmod.h>
32 32
33extern int __init omap_init_clocksource_32k(void); 33extern int __init omap_init_clocksource_32k(void __iomem *vbase);
34 34
35extern void __init omap_check_revision(void); 35extern void __init omap_check_revision(void);
36 36
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 4bdf14ec6747..297245dba66e 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -121,6 +121,7 @@ IS_OMAP_CLASS(16xx, 0x16)
121IS_OMAP_CLASS(24xx, 0x24) 121IS_OMAP_CLASS(24xx, 0x24)
122IS_OMAP_CLASS(34xx, 0x34) 122IS_OMAP_CLASS(34xx, 0x34)
123IS_OMAP_CLASS(44xx, 0x44) 123IS_OMAP_CLASS(44xx, 0x44)
124IS_AM_CLASS(35xx, 0x35)
124IS_AM_CLASS(33xx, 0x33) 125IS_AM_CLASS(33xx, 0x33)
125 126
126IS_TI_CLASS(81xx, 0x81) 127IS_TI_CLASS(81xx, 0x81)
@@ -148,6 +149,7 @@ IS_AM_SUBCLASS(335x, 0x335)
148#define cpu_is_ti81xx() 0 149#define cpu_is_ti81xx() 0
149#define cpu_is_ti816x() 0 150#define cpu_is_ti816x() 0
150#define cpu_is_ti814x() 0 151#define cpu_is_ti814x() 0
152#define soc_is_am35xx() 0
151#define cpu_is_am33xx() 0 153#define cpu_is_am33xx() 0
152#define cpu_is_am335x() 0 154#define cpu_is_am335x() 0
153#define cpu_is_omap44xx() 0 155#define cpu_is_omap44xx() 0
@@ -357,6 +359,7 @@ IS_OMAP_TYPE(3517, 0x3517)
357# undef cpu_is_ti81xx 359# undef cpu_is_ti81xx
358# undef cpu_is_ti816x 360# undef cpu_is_ti816x
359# undef cpu_is_ti814x 361# undef cpu_is_ti814x
362# undef soc_is_am35xx
360# undef cpu_is_am33xx 363# undef cpu_is_am33xx
361# undef cpu_is_am335x 364# undef cpu_is_am335x
362# define cpu_is_omap3430() is_omap3430() 365# define cpu_is_omap3430() is_omap3430()
@@ -378,6 +381,7 @@ IS_OMAP_TYPE(3517, 0x3517)
378# define cpu_is_ti81xx() is_ti81xx() 381# define cpu_is_ti81xx() is_ti81xx()
379# define cpu_is_ti816x() is_ti816x() 382# define cpu_is_ti816x() is_ti816x()
380# define cpu_is_ti814x() is_ti814x() 383# define cpu_is_ti814x() is_ti814x()
384# define soc_is_am35xx() is_am35xx()
381# define cpu_is_am33xx() is_am33xx() 385# define cpu_is_am33xx() is_am33xx()
382# define cpu_is_am335x() is_am335x() 386# define cpu_is_am335x() is_am335x()
383#endif 387#endif
@@ -433,6 +437,10 @@ IS_OMAP_TYPE(3517, 0x3517)
433#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8)) 437#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8))
434#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8)) 438#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8))
435 439
440#define AM35XX_CLASS 0x35170034
441#define AM35XX_REV_ES1_0 AM35XX_CLASS
442#define AM35XX_REV_ES1_1 (AM35XX_CLASS | (0x1 << 8))
443
436#define AM335X_CLASS 0x33500034 444#define AM335X_CLASS 0x33500034
437#define AM335X_REV_ES1_0 AM335X_CLASS 445#define AM335X_REV_ES1_0 AM335X_CLASS
438 446
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 42afb4c45517..c5811d4409b0 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -312,6 +312,11 @@
312#define CLEAR_CSR_ON_READ BIT(0xC) 312#define CLEAR_CSR_ON_READ BIT(0xC)
313#define IS_WORD_16 BIT(0xD) 313#define IS_WORD_16 BIT(0xD)
314 314
315/* Defines for DMA Capabilities */
316#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
317#define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
318#define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
319
315enum omap_reg_offsets { 320enum omap_reg_offsets {
316 321
317GCR, GSCR, GRST1, HW_ID, 322GCR, GSCR, GRST1, HW_ID,
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index bdf871a84d62..5da73562e486 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -75,7 +75,6 @@ struct clk;
75 75
76struct timer_regs { 76struct timer_regs {
77 u32 tidr; 77 u32 tidr;
78 u32 tiocp_cfg;
79 u32 tistat; 78 u32 tistat;
80 u32 tisr; 79 u32 tisr;
81 u32 tier; 80 u32 tier;
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 3e7ae0f0215f..a7754a886d42 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -177,9 +177,6 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
177void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, 177void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
178 int nr_controllers); 178 int nr_controllers);
179void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data); 179void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
180int omap_mmc_add(const char *name, int id, unsigned long base,
181 unsigned long size, unsigned int irq,
182 struct omap_mmc_platform_data *data);
183#else 180#else
184static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, 181static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
185 int nr_controllers) 182 int nr_controllers)
@@ -188,12 +185,6 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
188static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) 185static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
189{ 186{
190} 187}
191static inline int omap_mmc_add(const char *name, int id, unsigned long base,
192 unsigned long size, unsigned int irq,
193 struct omap_mmc_platform_data *data)
194{
195 return 0;
196}
197 188
198#endif 189#endif
199 190