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authorR Sricharan <r.sricharan@ti.com>2012-06-05 06:51:32 -0400
committerSantosh Shilimkar <santosh.shilimkar@ti.com>2012-07-09 09:44:39 -0400
commit05e152c76a1efaa3165afecf5acf535c8283f386 (patch)
treeb8f78f3fb8612bc007855964823ddca2490911bc /arch/arm/plat-omap/sram.c
parentb13e80a8bfe442406495a2fc9e7cbb79d33df48a (diff)
ARM: OMAP5: Add minimal support for OMAP5430 SOC
OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and with an integrated L2 cache controller. OMAP5432 is another variant of OMAP5430, with a memory controller supporting DDR3 and SATA. Patch includes: - The machine specific headers and sources updates. - Platform header updates. - Minimum initialisation support for serial. - IO table init Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/plat-omap/sram.c')
-rw-r--r--arch/arm/plat-omap/sram.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 70cf825bdd87..766181cb5c95 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -6,8 +6,8 @@
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com> 7 * Written by Tony Lindgren <tony@atomide.com>
8 * 8 *
9 * Copyright (C) 2009 Texas Instruments 9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
@@ -44,6 +44,7 @@
44#else 44#else
45#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) 45#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
46#endif 46#endif
47#define OMAP5_SRAM_PA 0x40300000
47 48
48#if defined(CONFIG_ARCH_OMAP2PLUS) 49#if defined(CONFIG_ARCH_OMAP2PLUS)
49#define SRAM_BOOTLOADER_SZ 0x00 50#define SRAM_BOOTLOADER_SZ 0x00
@@ -118,6 +119,9 @@ static void __init omap_detect_sram(void)
118 } else if (cpu_is_omap44xx()) { 119 } else if (cpu_is_omap44xx()) {
119 omap_sram_start = OMAP4_SRAM_PUB_PA; 120 omap_sram_start = OMAP4_SRAM_PUB_PA;
120 omap_sram_size = 0xa000; /* 40K */ 121 omap_sram_size = 0xa000; /* 40K */
122 } else if (soc_is_omap54xx()) {
123 omap_sram_start = OMAP5_SRAM_PA;
124 omap_sram_size = SZ_128K; /* 128KB */
121 } else { 125 } else {
122 omap_sram_start = OMAP2_SRAM_PUB_PA; 126 omap_sram_start = OMAP2_SRAM_PUB_PA;
123 omap_sram_size = 0x800; /* 2K */ 127 omap_sram_size = 0x800; /* 2K */
@@ -132,6 +136,9 @@ static void __init omap_detect_sram(void)
132 } else if (cpu_is_omap44xx()) { 136 } else if (cpu_is_omap44xx()) {
133 omap_sram_start = OMAP4_SRAM_PA; 137 omap_sram_start = OMAP4_SRAM_PA;
134 omap_sram_size = 0xe000; /* 56K */ 138 omap_sram_size = 0xe000; /* 56K */
139 } else if (soc_is_omap54xx()) {
140 omap_sram_start = OMAP5_SRAM_PA;
141 omap_sram_size = SZ_128K; /* 128KB */
135 } else { 142 } else {
136 omap_sram_start = OMAP2_SRAM_PA; 143 omap_sram_start = OMAP2_SRAM_PA;
137 if (cpu_is_omap242x()) 144 if (cpu_is_omap242x())