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authorEero Nurkkala <ext-eero.nurkkala@nokia.com>2009-08-20 09:18:15 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-08-20 15:10:27 -0400
commit2122fdc629f05634537e796c0630028e4db76953 (patch)
tree08f4d6f4a71e88cc7d93763e725c0892aa41df54 /arch/arm/plat-omap/include/mach/mcbsp.h
parent98cb20e88957faf9c99e194242caac7f55dd47e4 (diff)
OMAP: McBSP: Wakeups utilized
This patch enables the smart idle mode while McBPS is being utilized. Once it's done, force idle mode is taken instead. Apart of it, it also configures what signals will wake mcbsp up. Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'arch/arm/plat-omap/include/mach/mcbsp.h')
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index bd5b759991c8..333061d4f4a7 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -138,6 +138,7 @@
138#define OMAP_MCBSP_REG_THRSH1 0x94 138#define OMAP_MCBSP_REG_THRSH1 0x94
139#define OMAP_MCBSP_REG_IRQST 0xA0 139#define OMAP_MCBSP_REG_IRQST 0xA0
140#define OMAP_MCBSP_REG_IRQEN 0xA4 140#define OMAP_MCBSP_REG_IRQEN 0xA4
141#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
141#define OMAP_MCBSP_REG_XCCR 0xAC 142#define OMAP_MCBSP_REG_XCCR 0xAC
142#define OMAP_MCBSP_REG_RCCR 0xB0 143#define OMAP_MCBSP_REG_RCCR 0xB0
143 144
@@ -253,6 +254,8 @@
253#define RDISABLE 0x0001 254#define RDISABLE 0x0001
254 255
255/********************** McBSP SYSCONFIG bit definitions ********************/ 256/********************** McBSP SYSCONFIG bit definitions ********************/
257#define SIDLEMODE(value) ((value)<<3)
258#define ENAWAKEUP 0x0004
256#define SOFTRST 0x0002 259#define SOFTRST 0x0002
257 260
258/********************** McBSP DMA operating modes **************************/ 261/********************** McBSP DMA operating modes **************************/
@@ -260,6 +263,20 @@
260#define MCBSP_DMA_MODE_THRESHOLD 1 263#define MCBSP_DMA_MODE_THRESHOLD 1
261#define MCBSP_DMA_MODE_FRAME 2 264#define MCBSP_DMA_MODE_FRAME 2
262 265
266/********************** McBSP WAKEUPEN bit definitions *********************/
267#define XEMPTYEOFEN 0x4000
268#define XRDYEN 0x0400
269#define XEOFEN 0x0200
270#define XFSXEN 0x0100
271#define XSYNCERREN 0x0080
272#define RRDYEN 0x0008
273#define REOFEN 0x0004
274#define RFSREN 0x0002
275#define RSYNCERREN 0x0001
276#define WAKEUPEN_ALL (XEMPTYEOFEN | XRDYEN | XEOFEN | XFSXEN | \
277 XSYNCERREN | RRDYEN | REOFEN | RFSREN | \
278 RSYNCERREN)
279
263/* we don't do multichannel for now */ 280/* we don't do multichannel for now */
264struct omap_mcbsp_reg_cfg { 281struct omap_mcbsp_reg_cfg {
265 u16 spcr2; 282 u16 spcr2;