ARM: OMAP3: Add minimal omap3430 support

Add minimal omap3430 support based on earlier patches from
Syed Mohammed Khasim. Also merge in omap34xx SRAM support
from Karthik Dasu and use consistent naming for sram init
functions.

Also do following changes that make 34xx support usable:

- Remove unused sram.c functions for 34xx

- Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally
  in entry-macro.S

- Update mach-omap2/io.c to support 2420, 2430, and 34xx

- Also merge in 34xx GPMC changes to add fields wr_access and
  wr_data_mux_bus from Adrian Hunter

- Remove memory initialization call omap2_init_memory() until
  until more generic memory initialization patches are posted.
  It's OK to rely on bootloader initialization until then.

Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com>
Signed-off-by: Karthik Dasu<karthik-dp@ti.com>
Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

1 files changed, 35 insertions, 0 deletions

diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index e9fd63055cb2..9ee04969d366 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -286,6 +286,41 @@
 #define INT_24XX_USB_IRQ_OTG    80
 #define INT_24XX_MMC_IRQ        83
 
+#define INT_34XX_BENCH_MPU_EMUL 3
+#define INT_34XX_ST_MCBSP2_IRQ  4
+#define INT_34XX_ST_MCBSP3_IRQ  5
+#define INT_34XX_SSM_ABORT_IRQ  6
+#define INT_34XX_SYS_NIRQ       7
+#define INT_34XX_D2D_FW_IRQ     8
+#define INT_34XX_PRCM_MPU_IRQ   11
+#define INT_34XX_MCBSP1_IRQ     16
+#define INT_34XX_MCBSP2_IRQ     17
+#define INT_34XX_MCBSP3_IRQ     22
+#define INT_34XX_MCBSP4_IRQ     23
+#define INT_34XX_CAM_IRQ        24
+#define INT_34XX_MCBSP5_IRQ     27
+#define INT_34XX_GPIO_BANK1     29
+#define INT_34XX_GPIO_BANK2     30
+#define INT_34XX_GPIO_BANK3     31
+#define INT_34XX_GPIO_BANK4     32
+#define INT_34XX_GPIO_BANK5     33
+#define INT_34XX_GPIO_BANK6     34
+#define INT_34XX_USIM_IRQ       35
+#define INT_34XX_WDT3_IRQ       36
+#define INT_34XX_SPI4_IRQ       48
+#define INT_34XX_SHA1MD52_IRQ   49
+#define INT_34XX_FPKA_READY_IRQ 50
+#define INT_34XX_SHA1MD51_IRQ   51
+#define INT_34XX_RNG_IRQ        52
+#define INT_34XX_I2C3_IRQ       61
+#define INT_34XX_FPKA_ERROR_IRQ 64
+#define INT_34XX_PBIAS_IRQ      75
+#define INT_34XX_OHCI_IRQ       76
+#define INT_34XX_EHCI_IRQ       77
+#define INT_34XX_TLL_IRQ        78
+#define INT_34XX_PARTHASH_IRQ   79
+#define INT_34XX_MMC3_IRQ       94
+#define INT_34XX_GPT12_IRQ      95
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
  * 16 MPUIO lines */
 #define OMAP_MAX_GPIO_LINES     192