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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2009-10-19 20:25:57 -0400
committerTony Lindgren <tony@atomide.com>2009-10-19 20:25:57 -0400
commitf5d2d659450f8e68675124b879e7de82600b77ba (patch)
tree199f30ee76b270c758df4d72e712e0d04ef45883 /arch/arm/plat-omap/include/mach/io.h
parentb4224b236b0325ae678fa6b70bd3798dbd93a475 (diff)
omap: Add OMAP4 L3 and L4 peripherals.
This patch adds few necessary peripherals for OMAP4. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/include/mach/io.h')
-rw-r--r--arch/arm/plat-omap/include/mach/io.h29
1 files changed, 26 insertions, 3 deletions
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index a8f931a58f80..7e5319f907d1 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -66,15 +66,19 @@
66#define OMAP2_L3_IO_OFFSET 0x90000000 66#define OMAP2_L3_IO_OFFSET 0x90000000
67#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ 67#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
68 68
69
70#define OMAP2_L4_IO_OFFSET 0xb2000000
71#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
72
69#define OMAP4_L3_IO_OFFSET 0xb4000000 73#define OMAP4_L3_IO_OFFSET 0xb4000000
70#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ 74#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
71 75
76#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
77#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
78
72#define OMAP4_GPMC_IO_OFFSET 0xa9000000 79#define OMAP4_GPMC_IO_OFFSET 0xa9000000
73#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET) 80#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
74 81
75#define OMAP2_L4_IO_OFFSET 0xb2000000
76#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
77
78#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ 82#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
79#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) 83#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
80 84
@@ -214,6 +218,11 @@
214#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) 218#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
215#define L4_PER_44XX_SIZE SZ_4M 219#define L4_PER_44XX_SIZE SZ_4M
216 220
221#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
222 /* 0x49000000 --> 0xfb000000 */
223#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
224#define L4_ABE_44XX_SIZE SZ_1M
225
217#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE 226#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
218 /* 0x54000000 --> 0xfe800000 */ 227 /* 0x54000000 --> 0xfe800000 */
219#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET) 228#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
@@ -225,6 +234,20 @@
225#define OMAP44XX_GPMC_SIZE SZ_1M 234#define OMAP44XX_GPMC_SIZE SZ_1M
226 235
227 236
237#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
238 /* 0x4c000000 --> 0xfd100000 */
239#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
240#define OMAP44XX_EMIF1_SIZE SZ_1M
241
242#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
243 /* 0x4d000000 --> 0xfd200000 */
244#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
245#define OMAP44XX_EMIF2_SIZE SZ_1M
246
247#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
248 /* 0x4e000000 --> 0xfd300000 */
249#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
250#define OMAP44XX_DMM_SIZE SZ_1M
228/* 251/*
229 * ---------------------------------------------------------------------------- 252 * ----------------------------------------------------------------------------
230 * Omap specific register access 253 * Omap specific register access