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authorLinus Torvalds <torvalds@linux-foundation.org>2010-07-14 20:28:13 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-07-14 20:28:13 -0400
commit2f7989efd4398d92b8adffce2e07dd043a0895fe (patch)
tree8acbc880a8908ea18d724f747ea26d0afc2160bf /arch/arm/mm
parent6f7dd68b755b215deda5188a2c13c00f4776ea66 (diff)
parent0ebe25f90cd99bb1bcf622ec8a841421d48380d6 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6226/1: fix kprobe bug in ldr instruction emulation ARM: Update mach-types ARM: lockdep: fix unannotated irqs-on ARM: 6184/2: ux500: use neutral PRCMU base ARM: 6212/1: atomic ops: add memory constraints to inline asm ARM: 6211/1: atomic ops: fix register constraints for atomic64_add_unless ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRL
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/cache-l2x0.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 9819869d2bc9..df4955885b21 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -218,6 +218,9 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
218 cache_id = readl(l2x0_base + L2X0_CACHE_ID); 218 cache_id = readl(l2x0_base + L2X0_CACHE_ID);
219 aux = readl(l2x0_base + L2X0_AUX_CTRL); 219 aux = readl(l2x0_base + L2X0_AUX_CTRL);
220 220
221 aux &= aux_mask;
222 aux |= aux_val;
223
221 /* Determine the number of ways */ 224 /* Determine the number of ways */
222 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 225 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
223 case L2X0_CACHE_ID_PART_L310: 226 case L2X0_CACHE_ID_PART_L310:
@@ -248,8 +251,6 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
248 if (!(readl(l2x0_base + L2X0_CTRL) & 1)) { 251 if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
249 252
250 /* l2x0 controller is disabled */ 253 /* l2x0 controller is disabled */
251 aux &= aux_mask;
252 aux |= aux_val;
253 writel(aux, l2x0_base + L2X0_AUX_CTRL); 254 writel(aux, l2x0_base + L2X0_AUX_CTRL);
254 255
255 l2x0_inv_all(); 256 l2x0_inv_all();