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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-07-26 07:22:12 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-07-27 05:48:42 -0400
commit9ca03a21e320a6bf44559323527aba704bcc8772 (patch)
treec3422c49decfdca220c0088938546c49ee71ba64 /arch/arm/mm/proc-v6.S
parentb8ab5397bcbd92e3fd4a9770e0bf59315fa38dab (diff)
ARM: Factor out common code from cpu_proc_fin()
All implementations of cpu_proc_fin() start by disabling interrupts and then flush caches. Rather than have every processors proc_fin() implementation do this, move it out into generic code - and move the cache flush past setup_mm_for_reboot() (so it can benefit from having caches still enabled.) This allows cpu_proc_fin() to become independent of the L1/L2 cache types, and eventually move the L2 cache flushing into the L2 support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
-rw-r--r--arch/arm/mm/proc-v6.S5
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 2f5a3c23a0fe..22aac8515196 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -42,14 +42,11 @@ ENTRY(cpu_v6_proc_init)
42 mov pc, lr 42 mov pc, lr
43 43
44ENTRY(cpu_v6_proc_fin) 44ENTRY(cpu_v6_proc_fin)
45 stmfd sp!, {lr}
46 cpsid if @ disable interrupts
47 bl v6_flush_kern_cache_all
48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 45 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 bic r0, r0, #0x1000 @ ...i............ 46 bic r0, r0, #0x1000 @ ...i............
50 bic r0, r0, #0x0006 @ .............ca. 47 bic r0, r0, #0x0006 @ .............ca.
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 48 mcr p15, 0, r0, c1, c0, 0 @ disable caches
52 ldmfd sp!, {pc} 49 mov pc, lr
53 50
54/* 51/*
55 * cpu_v6_reset(loc) 52 * cpu_v6_reset(loc)