aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/proc-arm6_7.S
diff options
context:
space:
mode:
authorRussell King <rmk+kernel@arm.linux.org.uk>2011-06-26 11:01:26 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-07-02 05:56:11 -0400
commitda7404725781bc7c736e10cae5521e5604e222a5 (patch)
treee816cd79e1b09ddcbd41b7cd5b3c6c9c9bd5eb98 /arch/arm/mm/proc-arm6_7.S
parent0d147db0c127c561f8f9ead9f3c1ec38f89f1040 (diff)
ARM: entry: data abort: tail-call the main data abort handler
Tail-call the main C data abort handler code from the per-CPU helper code. Update the comments in the code wrt the new calling and return register state. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm6_7.S')
-rw-r--r--arch/arm/mm/proc-arm6_7.S29
1 files changed, 14 insertions, 15 deletions
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index d4c328ecf3ba..d755d5b83898 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -29,7 +29,8 @@ ENTRY(cpu_arm7_dcache_clean_area)
29/* 29/*
30 * Function: arm6_7_data_abort () 30 * Function: arm6_7_data_abort ()
31 * 31 *
32 * Params : r4 = aborted context pc 32 * Params : r2 = pt_regs
33 * : r4 = aborted context pc
33 * : r5 = aborted context psr 34 * : r5 = aborted context psr
34 * 35 *
35 * Purpose : obtain information about current aborted instruction 36 * Purpose : obtain information about current aborted instruction
@@ -49,7 +50,7 @@ ENTRY(cpu_arm7_data_abort)
49 nop 50 nop
50 51
51/* 0 */ b .data_unknown 52/* 0 */ b .data_unknown
52/* 1 */ mov pc, lr @ swp 53/* 1 */ b do_DataAbort @ swp
53/* 2 */ b .data_unknown 54/* 2 */ b .data_unknown
54/* 3 */ b .data_unknown 55/* 3 */ b .data_unknown
55/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m 56/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
@@ -60,16 +61,14 @@ ENTRY(cpu_arm7_data_abort)
60/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist> 61/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
61/* a */ b .data_unknown 62/* a */ b .data_unknown
62/* b */ b .data_unknown 63/* b */ b .data_unknown
63/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m 64/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
64/* d */ mov pc, lr @ ldc rd, [rn, #m] 65/* d */ b do_DataAbort @ ldc rd, [rn, #m]
65/* e */ b .data_unknown 66/* e */ b .data_unknown
66/* f */ 67/* f */
67.data_unknown: @ Part of jumptable 68.data_unknown: @ Part of jumptable
68 mov r0, r4 69 mov r0, r4
69 mov r1, r8 70 mov r1, r8
70 mov r2, sp 71 b baddataabort
71 bl baddataabort
72 b ret_from_exception
73 72
74ENTRY(cpu_arm6_data_abort) 73ENTRY(cpu_arm6_data_abort)
75 mrc p15, 0, r1, c5, c0, 0 @ get FSR 74 mrc p15, 0, r1, c5, c0, 0 @ get FSR
@@ -79,11 +78,11 @@ ENTRY(cpu_arm6_data_abort)
79 orreq r1, r1, #1 << 11 @ yes. 78 orreq r1, r1, #1 << 11 @ yes.
80 and r7, r8, #14 << 24 79 and r7, r8, #14 << 24
81 teq r7, #8 << 24 @ was it ldm/stm 80 teq r7, #8 << 24 @ was it ldm/stm
82 movne pc, lr 81 bne do_DataAbort
83 82
84.data_arm_ldmstm: 83.data_arm_ldmstm:
85 tst r8, #1 << 21 @ check writeback bit 84 tst r8, #1 << 21 @ check writeback bit
86 moveq pc, lr @ no writeback -> no fixup 85 beq do_DataAbort @ no writeback -> no fixup
87 mov r7, #0x11 86 mov r7, #0x11
88 orr r7, r7, #0x1100 87 orr r7, r7, #0x1100
89 and r6, r8, r7 88 and r6, r8, r7
@@ -102,7 +101,7 @@ ENTRY(cpu_arm6_data_abort)
102 subne r7, r7, r6, lsl #2 @ Undo increment 101 subne r7, r7, r6, lsl #2 @ Undo increment
103 addeq r7, r7, r6, lsl #2 @ Undo decrement 102 addeq r7, r7, r6, lsl #2 @ Undo decrement
104 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 103 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
105 mov pc, lr 104 b do_DataAbort
106 105
107.data_arm_apply_r6_and_rn: 106.data_arm_apply_r6_and_rn:
108 and r5, r8, #15 << 16 @ Extract 'n' from instruction 107 and r5, r8, #15 << 16 @ Extract 'n' from instruction
@@ -111,25 +110,25 @@ ENTRY(cpu_arm6_data_abort)
111 subne r7, r7, r6 @ Undo incrmenet 110 subne r7, r7, r6 @ Undo incrmenet
112 addeq r7, r7, r6 @ Undo decrement 111 addeq r7, r7, r6 @ Undo decrement
113 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 112 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
114 mov pc, lr 113 b do_DataAbort
115 114
116.data_arm_lateldrpreconst: 115.data_arm_lateldrpreconst:
117 tst r8, #1 << 21 @ check writeback bit 116 tst r8, #1 << 21 @ check writeback bit
118 moveq pc, lr @ no writeback -> no fixup 117 beq do_DataAbort @ no writeback -> no fixup
119.data_arm_lateldrpostconst: 118.data_arm_lateldrpostconst:
120 movs r9, r8, lsl #20 @ Get offset 119 movs r9, r8, lsl #20 @ Get offset
121 moveq pc, lr @ zero -> no fixup 120 beq do_DataAbort @ zero -> no fixup
122 and r5, r8, #15 << 16 @ Extract 'n' from instruction 121 and r5, r8, #15 << 16 @ Extract 'n' from instruction
123 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 122 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
124 tst r8, #1 << 23 @ Check U bit 123 tst r8, #1 << 23 @ Check U bit
125 subne r7, r7, r9, lsr #20 @ Undo increment 124 subne r7, r7, r9, lsr #20 @ Undo increment
126 addeq r7, r7, r9, lsr #20 @ Undo decrement 125 addeq r7, r7, r9, lsr #20 @ Undo decrement
127 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 126 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
128 mov pc, lr 127 b do_DataAbort
129 128
130.data_arm_lateldrprereg: 129.data_arm_lateldrprereg:
131 tst r8, #1 << 21 @ check writeback bit 130 tst r8, #1 << 21 @ check writeback bit
132 moveq pc, lr @ no writeback -> no fixup 131 beq do_DataAbort @ no writeback -> no fixup
133.data_arm_lateldrpostreg: 132.data_arm_lateldrpostreg:
134 and r7, r8, #15 @ Extract 'm' from instruction 133 and r7, r8, #15 @ Extract 'm' from instruction
135 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm' 134 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-20 10:05:14 -0500