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authorStephen Warren <swarren@nvidia.com>2012-09-25 17:54:56 -0400
committerStephen Warren <swarren@nvidia.com>2012-11-16 14:22:18 -0500
commit460678035247a9f72a4401dfeb6513ee495bf975 (patch)
tree4529e3199c7755ab7bf87e5003e389d0054d9a36 /arch/arm/mach-tegra
parent7a28106509463529d7b0408d3f5a0ab99f6810ee (diff)
ARM: tegra: move debug-macro.S to include/debug
Move Tegra's debug-macro.S over to the common debug macro directory. Move Tegra's debug UART selection menu into ARM's Kconfig.debug, so that all related options are selected in the same place. Tegra's uncompress.h is left in mach-tegra/include/mach; it will be removed whenever Tegra is converted to multi-platform. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/Kconfig29
-rw-r--r--arch/arm/mach-tegra/include/mach/debug-macro.S225
2 files changed, 0 insertions, 254 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 97fcd16e2dab..e426d1b7747e 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -57,35 +57,6 @@ config TEGRA_AHB
57 which controls AHB bus master arbitration and some 57 which controls AHB bus master arbitration and some
58 perfomance parameters(priority, prefech size). 58 perfomance parameters(priority, prefech size).
59 59
60choice
61 prompt "Low-level debug console UART"
62
63config TEGRA_DEBUG_UART_AUTO_ODMDATA
64 bool "Via ODMDATA"
65 help
66 Automatically determines which UART to use for low-level debug based
67 on the ODMDATA value. This value is part of the BCT, and is written
68 to the boot memory device using nvflash, or other flashing tool.
69 When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
70 0/1/2/3/4 are UART A/B/C/D/E.
71
72config TEGRA_DEBUG_UARTA
73 bool "UART-A"
74
75config TEGRA_DEBUG_UARTB
76 bool "UART-B"
77
78config TEGRA_DEBUG_UARTC
79 bool "UART-C"
80
81config TEGRA_DEBUG_UARTD
82 bool "UART-D"
83
84config TEGRA_DEBUG_UARTE
85 bool "UART-E"
86
87endchoice
88
89config TEGRA_EMC_SCALING_ENABLE 60config TEGRA_EMC_SCALING_ENABLE
90 bool "Enable scaling the memory frequency" 61 bool "Enable scaling the memory frequency"
91 62
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
deleted file mode 100644
index f67fd6df0e2f..000000000000
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ /dev/null
@@ -1,225 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/debug-macro.S
3 *
4 * Copyright (C) 2010,2011 Google, Inc.
5 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 * Erik Gilling <konkers@google.com>
10 * Doug Anderson <dianders@chromium.org>
11 * Stephen Warren <swarren@nvidia.com>
12 *
13 * Portions based on mach-omap2's debug-macro.S
14 * Copyright (C) 1994-1999 Russell King
15 *
16 * This software is licensed under the terms of the GNU General Public
17 * License version 2, as published by the Free Software Foundation, and
18 * may be copied, distributed, and modified under those terms.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 */
26
27#include <linux/serial_reg.h>
28
29#define UART_SHIFT 2
30
31/* Physical addresses */
32#define TEGRA_CLK_RESET_BASE 0x60006000
33#define TEGRA_APB_MISC_BASE 0x70000000
34#define TEGRA_UARTA_BASE 0x70006000
35#define TEGRA_UARTB_BASE 0x70006040
36#define TEGRA_UARTC_BASE 0x70006200
37#define TEGRA_UARTD_BASE 0x70006300
38#define TEGRA_UARTE_BASE 0x70006400
39#define TEGRA_PMC_BASE 0x7000e400
40
41#define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
42#define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
43#define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
44#define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
45#define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
46#define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
47#define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
48#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
49
50/*
51 * Must be 1MB-aligned since a 1MB mapping is used early on.
52 * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
53 */
54#define UART_VIRTUAL_BASE 0xfe100000
55
56#define checkuart(rp, rv, lhu, bit, uart) \
57 /* Load address of CLK_RST register */ \
58 movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
59 movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
60 /* Load value from CLK_RST register */ \
61 ldr rp, [rp, #0] ; \
62 /* Test UART's reset bit */ \
63 tst rp, #(1 << bit) ; \
64 /* If set, can't use UART; jump to save no UART */ \
65 bne 90f ; \
66 /* Load address of CLK_OUT_ENB register */ \
67 movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
68 movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
69 /* Load value from CLK_OUT_ENB register */ \
70 ldr rp, [rp, #0] ; \
71 /* Test UART's clock enable bit */ \
72 tst rp, #(1 << bit) ; \
73 /* If clear, can't use UART; jump to save no UART */ \
74 beq 90f ; \
75 /* Passed all tests, load address of UART registers */ \
76 movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
77 movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
78 /* Jump to save UART address */ \
79 b 91f
80
81 .macro addruart, rp, rv, tmp
82 adr \rp, 99f @ actual addr of 99f
83 ldr \rv, [\rp] @ linked addr is stored there
84 sub \rv, \rv, \rp @ offset between the two
85 ldr \rp, [\rp, #4] @ linked tegra_uart_config
86 sub \tmp, \rp, \rv @ actual tegra_uart_config
87 ldr \rp, [\tmp] @ Load tegra_uart_config
88 cmp \rp, #1 @ needs initialization?
89 bne 100f @ no; go load the addresses
90 mov \rv, #0 @ yes; record init is done
91 str \rv, [\tmp]
92
93#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
94 /* Check ODMDATA */
9510: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
96 movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
97 ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
98 ubfx \rv, \rp, #18, #2 @ 19:18 are console type
99 cmp \rv, #2 @ 2 and 3 mean DCC, UART
100 beq 11f @ some boards swap the meaning
101 cmp \rv, #3 @ so accept either
102 bne 90f
10311: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
104 cmp \rv, #0 @ UART 0?
105 beq 20f
106 cmp \rv, #1 @ UART 1?
107 beq 21f
108 cmp \rv, #2 @ UART 2?
109 beq 22f
110 cmp \rv, #3 @ UART 3?
111 beq 23f
112 cmp \rv, #4 @ UART 4?
113 beq 24f
114 b 90f @ invalid
115#endif
116
117#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
118 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
119 /* Check UART A validity */
12020: checkuart(\rp, \rv, L, 6, A)
121#endif
122
123#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
124 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
125 /* Check UART B validity */
12621: checkuart(\rp, \rv, L, 7, B)
127#endif
128
129#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
130 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
131 /* Check UART C validity */
13222: checkuart(\rp, \rv, H, 23, C)
133#endif
134
135#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
136 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
137 /* Check UART D validity */
13823: checkuart(\rp, \rv, U, 1, D)
139#endif
140
141#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
142 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
143 /* Check UART E validity */
14424:
145 checkuart(\rp, \rv, U, 2, E)
146#endif
147
148 /* No valid UART found */
14990: mov \rp, #0
150 /* fall through */
151
152 /* Record whichever UART we chose */
15391: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
154 cmp \rp, #0 @ Valid UART address?
155 bne 92f @ Yes, go process it
156 str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt
157 b 100f @ Done
15892: and \rv, \rp, #0xffffff @ offset within 1MB section
159 add \rv, \rv, #UART_VIRTUAL_BASE
160 str \rv, [\tmp, #8] @ Store in tegra_uart_virt
161 movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
162 movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
163 ldr \rv, [\rv, #0] @ Load HIDREV
164 ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
165 cmp \rv, #0x20 @ Tegra20?
166 moveq \rv, #0x75 @ Tegra20 divisor
167 movne \rv, #0xdd @ Tegra30 divisor
168 str \rv, [\tmp, #12] @ Save divisor to scratch
169 /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
170 mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
171 str \rv, [\rp, #UART_LCR << UART_SHIFT]
172 /* uart[UART_DLL] = div & 0xff; */
173 ldr \rv, [\tmp, #12]
174 and \rv, \rv, #0xff
175 str \rv, [\rp, #UART_DLL << UART_SHIFT]
176 /* uart[UART_DLM] = div >> 8; */
177 ldr \rv, [\tmp, #12]
178 lsr \rv, \rv, #8
179 str \rv, [\rp, #UART_DLM << UART_SHIFT]
180 /* uart[UART_LCR] = UART_LCR_WLEN8; */
181 mov \rv, #UART_LCR_WLEN8
182 str \rv, [\rp, #UART_LCR << UART_SHIFT]
183 b 100f
184
185 .align
18699: .word .
187 .word tegra_uart_config
188 .ltorg
189
190 /* Load previously selected UART address */
191100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
192 ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
193 .endm
194
195/*
196 * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
197 * check to make sure that the UART address is actually valid.
198 */
199
200 .macro senduart, rd, rx
201 cmp \rx, #0
202 strneb \rd, [\rx, #UART_TX << UART_SHIFT]
2031001:
204 .endm
205
206 .macro busyuart, rd, rx
207 cmp \rx, #0
208 beq 1002f
2091001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
210 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
211 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
212 bne 1001b
2131002:
214 .endm
215
216 .macro waituart, rd, rx
217#ifdef FLOW_CONTROL
218 cmp \rx, #0
219 beq 1002f
2201001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
221 tst \rd, #UART_MSR_CTS
222 beq 1001b
2231002:
224#endif
225 .endm
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