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authorRob Herring <rob.herring@calxeda.com>2012-03-09 18:16:40 -0500
committerRob Herring <rob.herring@calxeda.com>2012-03-13 22:25:21 -0400
commita2a47ca36642e3995e982957bc42678cf11ca6ac (patch)
tree6b6a034d2d61c4b0f0f3bb59c673dd7b16d19c11 /arch/arm/mach-shmobile/smp-sh73a0.c
parent6f6f6a70295c6a4f89c7aca015c5db247a79d609 (diff)
ARM: __io abuse cleanup
Several platforms incorrectly use __io() for casting to 'void __iomem *'. This converts all of those uses to use the common IOMEM macro. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Anton Vorontsov <cbouatmailru@gmail.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-sh@vger.kernel.org Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-shmobile/smp-sh73a0.c')
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 0d159d64a345..667d53dd7012 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -28,11 +28,11 @@
28#include <asm/smp_twd.h> 28#include <asm/smp_twd.h>
29#include <asm/hardware/gic.h> 29#include <asm/hardware/gic.h>
30 30
31#define WUPCR 0xe6151010 31#define WUPCR IOMEM(0xe6151010)
32#define SRESCR 0xe6151018 32#define SRESCR IOMEM(0xe6151018)
33#define PSTR 0xe6151040 33#define PSTR IOMEM(0xe6151040)
34#define SBAR 0xe6180020 34#define SBAR IOMEM(0xe6180020)
35#define APARMBAREA 0xe6f10020 35#define APARMBAREA IOMEM(0xe6f10020)
36 36
37static void __iomem *scu_base_addr(void) 37static void __iomem *scu_base_addr(void)
38{ 38{
@@ -80,10 +80,10 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
80 /* enable cache coherency */ 80 /* enable cache coherency */
81 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 81 modify_scu_cpu_psr(0, 3 << (cpu * 8));
82 82
83 if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3) 83 if (((__raw_readw(PSTR) >> (4 * cpu)) & 3) == 3)
84 __raw_writel(1 << cpu, __io(WUPCR)); /* wake up */ 84 __raw_writel(1 << cpu, WUPCR); /* wake up */
85 else 85 else
86 __raw_writel(1 << cpu, __io(SRESCR)); /* reset */ 86 __raw_writel(1 << cpu, SRESCR); /* reset */
87 87
88 return 0; 88 return 0;
89} 89}
@@ -95,8 +95,8 @@ void __init sh73a0_smp_prepare_cpus(void)
95 scu_enable(scu_base_addr()); 95 scu_enable(scu_base_addr());
96 96
97 /* Map the reset vector (in headsmp.S) */ 97 /* Map the reset vector (in headsmp.S) */
98 __raw_writel(0, __io(APARMBAREA)); /* 4k */ 98 __raw_writel(0, APARMBAREA); /* 4k */
99 __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR)); 99 __raw_writel(__pa(shmobile_secondary_vector), SBAR);
100 100
101 /* enable cache coherency on CPU0 */ 101 /* enable cache coherency on CPU0 */
102 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 102 modify_scu_cpu_psr(0, 3 << (cpu * 8));