aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-shmobile/pm-r8a7779.c
diff options
context:
space:
mode:
authorMagnus Damm <damm@opensource.se>2012-01-10 03:44:39 -0500
committerPaul Mundt <lethal@linux-sh.org>2012-01-11 21:00:27 -0500
commitf40aaf6da14a4043d6361e0c7d74ada18e866059 (patch)
tree655a02f6a7a0ef50772c13c00fef992924bdeb78 /arch/arm/mach-shmobile/pm-r8a7779.c
parentf0a217a31a745421df98db0d14ebdadef11d734c (diff)
ARM: mach-shmobile: r8a7779 SMP support V3
This patch contains r8a7779 SMP support V3 - now including CPU hotplug offine and online support. The r8a7779 power domain code is tied together with SMP glue code which allows us to control the power domains via CPU hotplug. At this point the kernel boots with the 4 Cortex-A9 cores in SMP mode and all CPU cores except CPU0 can be hotplugged. The code in platsmp.c is quite far from pretty, but it is kept like that intentionally to avoid creating layers of code that will go away in the near future anyway. The code needs to be updated when some per-SoC handling code will be added to the ARM architecture, see the following patch for more information: "[RFC PATCH 0/3] Per SoC descriptor" Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/arm/mach-shmobile/pm-r8a7779.c')
-rw-r--r--arch/arm/mach-shmobile/pm-r8a7779.c30
1 files changed, 22 insertions, 8 deletions
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index d9c56fe067a5..c38ba7b43ef8 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -48,7 +48,9 @@ static void __iomem *r8a7779_sysc_base;
48#define SYSCISR_RETRIES 1000 48#define SYSCISR_RETRIES 1000
49#define SYSCISR_DELAY_US 1 49#define SYSCISR_DELAY_US 1
50 50
51#ifdef CONFIG_PM 51#if defined(CONFIG_PM) || defined(CONFIG_SMP)
52
53static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */
52 54
53static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch, 55static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch,
54 int sr_bit, int reg_offs) 56 int sr_bit, int reg_offs)
@@ -86,9 +88,12 @@ static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
86 unsigned int isr_mask = 1 << r8a7779_ch->isr_bit; 88 unsigned int isr_mask = 1 << r8a7779_ch->isr_bit;
87 unsigned int chan_mask = 1 << r8a7779_ch->chan_bit; 89 unsigned int chan_mask = 1 << r8a7779_ch->chan_bit;
88 unsigned int status; 90 unsigned int status;
91 unsigned long flags;
89 int ret = 0; 92 int ret = 0;
90 int k; 93 int k;
91 94
95 spin_lock_irqsave(&r8a7779_sysc_lock, flags);
96
92 iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); 97 iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
93 98
94 do { 99 do {
@@ -112,6 +117,8 @@ static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
112 iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); 117 iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
113 118
114 out: 119 out:
120 spin_unlock_irqrestore(&r8a7779_sysc_lock, flags);
121
115 pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n", 122 pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n",
116 r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0), 123 r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0),
117 ioread32(r8a7779_sysc_base + PWRSR1), 124 ioread32(r8a7779_sysc_base + PWRSR1),
@@ -121,12 +128,12 @@ static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
121 return ret; 128 return ret;
122} 129}
123 130
124static int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch) 131int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
125{ 132{
126 return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off); 133 return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off);
127} 134}
128 135
129static int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch) 136int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
130{ 137{
131 return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on); 138 return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on);
132} 139}
@@ -142,6 +149,14 @@ static void __init r8a7779_sysc_init(void)
142 iowrite32(0, r8a7779_sysc_base + SYSCIMR); 149 iowrite32(0, r8a7779_sysc_base + SYSCIMR);
143} 150}
144 151
152#else /* CONFIG_PM || CONFIG_SMP */
153
154static inline void r8a7779_sysc_init(void) {}
155
156#endif /* CONFIG_PM || CONFIG_SMP */
157
158#ifdef CONFIG_PM
159
145static int pd_power_down(struct generic_pm_domain *genpd) 160static int pd_power_down(struct generic_pm_domain *genpd)
146{ 161{
147 return r8a7779_sysc_power_down(to_r8a7779_ch(genpd)); 162 return r8a7779_sysc_power_down(to_r8a7779_ch(genpd));
@@ -223,13 +238,12 @@ struct r8a7779_pm_domain r8a7779_impx3 = {
223 } 238 }
224}; 239};
225 240
226#else /* CONFIG_PM */
227
228static inline void r8a7779_sysc_init(void) {}
229
230#endif /* CONFIG_PM */ 241#endif /* CONFIG_PM */
231 242
232void __init r8a7779_pm_init(void) 243void __init r8a7779_pm_init(void)
233{ 244{
234 r8a7779_sysc_init(); 245 static int once;
246
247 if (!once++)
248 r8a7779_sysc_init();
235} 249}