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authorThomas Abraham <thomas.abraham@linaro.org>2012-07-12 18:15:14 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-07-13 02:23:46 -0400
commita5238e360b715e9a1bb39d7d3537f78cc9e9e286 (patch)
treeb6503a7429b93b7c15f90d5e3b0124a191215423 /arch/arm/mach-s5pv210/clock.c
parent2b54be661191532ddf1628c3b151b81ae8743caa (diff)
spi: s3c64xx: move controller information into driver data
Platform data is used to specify controller hardware specific information such as the tx/rx fifo level mask and bit offset of rx fifo level. Such information is not suitable to be supplied from device tree. Instead, it can be moved into the driver data and removed from platform data. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pv210/clock.c')
-rw-r--r--arch/arm/mach-s5pv210/clock.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 09609d50961d..fcdf52dbcc49 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = {
445 .ctrlbit = (1 << 11), 445 .ctrlbit = (1 << 11),
446 }, { 446 }, {
447 .name = "spi", 447 .name = "spi",
448 .devname = "s3c64xx-spi.0", 448 .devname = "s5pv210-spi.0",
449 .parent = &clk_pclk_psys.clk, 449 .parent = &clk_pclk_psys.clk,
450 .enable = s5pv210_clk_ip3_ctrl, 450 .enable = s5pv210_clk_ip3_ctrl,
451 .ctrlbit = (1<<12), 451 .ctrlbit = (1<<12),
452 }, { 452 }, {
453 .name = "spi", 453 .name = "spi",
454 .devname = "s3c64xx-spi.1", 454 .devname = "s5pv210-spi.1",
455 .parent = &clk_pclk_psys.clk, 455 .parent = &clk_pclk_psys.clk,
456 .enable = s5pv210_clk_ip3_ctrl, 456 .enable = s5pv210_clk_ip3_ctrl,
457 .ctrlbit = (1<<13), 457 .ctrlbit = (1<<13),
458 }, { 458 }, {
459 .name = "spi", 459 .name = "spi",
460 .devname = "s3c64xx-spi.2", 460 .devname = "s5pv210-spi.2",
461 .parent = &clk_pclk_psys.clk, 461 .parent = &clk_pclk_psys.clk,
462 .enable = s5pv210_clk_ip3_ctrl, 462 .enable = s5pv210_clk_ip3_ctrl,
463 .ctrlbit = (1<<14), 463 .ctrlbit = (1<<14),
@@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = {
1035static struct clksrc_clk clk_sclk_spi0 = { 1035static struct clksrc_clk clk_sclk_spi0 = {
1036 .clk = { 1036 .clk = {
1037 .name = "sclk_spi", 1037 .name = "sclk_spi",
1038 .devname = "s3c64xx-spi.0", 1038 .devname = "s5pv210-spi.0",
1039 .enable = s5pv210_clk_mask0_ctrl, 1039 .enable = s5pv210_clk_mask0_ctrl,
1040 .ctrlbit = (1 << 16), 1040 .ctrlbit = (1 << 16),
1041 }, 1041 },
@@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
1047static struct clksrc_clk clk_sclk_spi1 = { 1047static struct clksrc_clk clk_sclk_spi1 = {
1048 .clk = { 1048 .clk = {
1049 .name = "sclk_spi", 1049 .name = "sclk_spi",
1050 .devname = "s3c64xx-spi.1", 1050 .devname = "s5pv210-spi.1",
1051 .enable = s5pv210_clk_mask0_ctrl, 1051 .enable = s5pv210_clk_mask0_ctrl,
1052 .ctrlbit = (1 << 17), 1052 .ctrlbit = (1 << 17),
1053 }, 1053 },
@@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
1331 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 1331 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1332 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), 1332 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1333 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 1333 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1334 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 1334 CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1335 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 1335 CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1336}; 1336};
1337 1337
1338void __init s5pv210_register_clocks(void) 1338void __init s5pv210_register_clocks(void)